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2006

Alberto D. Pascual-Montano, Pedro Carmona-Saez, Monica Chagoyen, Francisco Tirado, José María Carazo, Roberto D. Pascual-Marqui, bioNMF: a versatile tool for non-negative matrix factorization in biology., BMC Bioinformatics 7: 366 (2006)
Andreas Hansson, Lars Niklasson, Using Segmentation to Control the Retrieval of Data., IJCNN 2006: 1764-1769
Andreas Persson, Lars Bengtsson, Reverse conversion architectures for signed-digit residue number systems., ISCAS 2006
Andrzej Bednarski, Christoph W. Kessler, Optimal Integrated VLIW Code Generation with Integer Linear Programming., Euro-Par 2006: 461-472
Anila Usman, Mikel Luján, Len Freeman, John R. Gurd, Performance Evaluation of Storage Formats for Sparse Matrices in Fortran., HPCC 2006: 160-169
Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Evaluating SoC Network Performance in MPEG-4 Encoder., SiPS 2006: 250-255
Christoph W. Keßler, Andrzej Bednarski, Optimal integrated code generation for VLIW architectures., Concurrency and Computation: Practice and Experience 18(11): 1353-1390 (2006)
Christoph W. Kessler, Peter Fritzson, Mattias V. Eriksson, NestStepModelica - Mathematical Modeling and Bulk-Synchronous Parallel Simulation., PARA 2006: 1006-1015
Dionisios N. Pnevmatikatos, Aggelos Arelakis, , Variable-Length Hashing for Exact Pattern Matching., FPL 2006: 1-6
Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak Sen, Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts., ASAP 2006: 186-190
George A. Constantinides, Word-length optimization for differentiable nonlinear systems., ACM Trans. Design Autom. Electr. Syst. 11(1): 26-43 (2006)
Giovanni Agosta, Stefano Crespi-Reghizzi, P. Palumbo, Martino Sykora, Selective compilation via fast code analysis and bytecode tracing., SAC 2006: 906-911
Heikki Hurskainen, Jari Nurmi, SystemC Model of an Interoperative GPS/Galileo Code Correlator Channel., SiPS 2006: 327-332
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere, Efficient Automated Synthesis Programing and Implementation of Multi-Processor Platforms on FPGA Chips., FPL 2006: 1-6
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere, Multi-processor system design with ESPAM., CODES+ISSS 2006: 211-216
Jérôme Lemaitre, Ed F. Deprettere, FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications., Euro-Par 2006: 1192-1203
Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere, Requirements for Interfacing IP-Components in Re-configurable Platforms., VLSI Signal Processing 43(2-3): 173-184 (2006)
Jonathan A. Clarke, George A. Constantinides, High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic., FPL 2006: 1-2
Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Leong, FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach., FPL 2006: 1-6
Konstantinos Masselos, George A. Constantinides, Qiang Liu, Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm., FPL 2006: 1-6
Lily R. Liang, Shiyong Lu, Xuena Wang, Yi Lu, Vinay Mandal, Dorrelyn Patacsil, Deepak Kumar, FM-test: a fuzzy-set-theory-based approach to differential gene expression data analysis., BMC Bioinformatics 7(S-4): (2006)
Marco Alexandre Cravo Gomes, Gabriel Falcão Paiva Fernandes, João Gonçalves, Vítor Manuel Mendes da Silva, Miguel Falcão, Pedro Faia, , HDL Library of Processing Units for Generic and DVB-S2 LDPC Decoding., SIGMAP 2006: 17-24
Mattias V. Eriksson, Christoph W. Keßler, Mikhail Chalabine, Load balancing of irregular parallel divide-and-conquer algorithms in group-SPMD programming environments., ARCS Workshops 2006: 313-322
Mikhail Chalabine, Christoph W. Keßler, Peter Bunus, Automated Round-trip Software Engineering in Aspect Weaving Systems., ASE 2006: 305-308
Mikhail Chalabine, Christoph W. Kessler, Crosscutting Concerns in Parallelization by Invasive Software Composition and Aspect Weaving., HICSS 2006
P. Bougas, A. Tsirikos, K. Anagnostopoulos, Isidoros Sideris, Kiamal Z. Pekmestzi, , Segmentation based design of serial parallel multipliers., ISCAS 2006
Su-Shin Ang, George A. Constantinides, Dynamic Memory Sub-System for Reconfigurable Platforms., FPL 2006: 1-2
Timo Vogt, Norbert Wehn, A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding., SiPS 2006: 142-147
Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck, Instruction Transfer And Storage Exploration for Low Energy VLIWs., SiPS 2006: 292-297
Yuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Alastair Reid, Krisztián Flautner, Design and Implementation of Turbo Decoders for Software Defined Radio., SiPS 2006: 22-27
Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser, Real-time systems for multiprocessor architectures., IPDPS 2006
A. de Dios, B. Sahelices, Pablo Ibáñez, Víctor Viñals, José M. Llabería, Speeding-Up Synchronizations in DSM Multiprocessors., Euro-Par 2006: 473-484
A. Jimeno, J. L. Sánchez, H. Mora, J. Mora, J. M. García-Chamizo, FPGA-based tool path computation: an application for shoe last machining on CNC lathes, Computers in Industry , Volume 57 Issue 2, Elsevier Science Publishers B. V., February 2006
A. Mejia, Jose Flich, José Duato, Sven-Arne Reinemo, Tor Skeie, Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori., IPDPS 2006
Abbas Bigdeli, Morteza Biglari-Abhari, Zoran Salcic, Yat Tin Lai, A new pipelined systolic array-based architecture for matrix inversion in FPGAS with Kalman filter case study, EURASIP Journal on Applied Signal Processing , Volume 2006 Issue 1, Hindawi Publishing Corp., January 2006
Abid M. Malik, Jim McInnes, Peter van Beek, Optimal Basic Block Instruction Scheduling for Multiple-Issue Processors Using Constraing Programming., ICTAI 2006: 279-287
Adam Betts, Guillem Bernat, Tree-Based WCET Analysis on Instrumentation Point Graphs., ISORC 2006: 558-565
Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson, A universal performance factor for multi-criteria evaluation of multistage interconnection networks., Future Generation Comp. Syst. 22(7): 794-804 (2006)
Ahmad Zmily, Christos Kozyrakis, Simultaneously improving code size performance and energy in embedded processors., DATE 2006: 224-229
Ahmad Zmily, Christos Kozyrakis, Block-aware instruction set architecture., TACO 3(3): 327-357 (2006)
Ahmed Abdel-Hafez, Ali Miri, Luis Orozco-Barbosa, Scalable and fault-tolerant key agreement protocol for dynamic groups., Int. Journal of Network Management 16(3): 185-202 (2006)
Ajay Joshi, Aashish Phansalkar, Lieven Eeckhout, Lizy Kurian John, Measuring Benchmark Similarity Using Inherent Program Characteristics., IEEE Trans. Computers 55(6): 769-782 (2006)
Ajay Joshi, Joshua J. Yi, Robert H. Bell Jr., Lieven Eeckhout, Lizy Kurian John, David J. Lilja, Evaluating the efficacy of statistical simulation for design space exploration., ISPASS 2006: 70-79
Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John, Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks., IISWC 2006: 105-115
Ajay K. Verma, Paolo Ienne, Towards the automatic exploration of arithmetic-circuit architectures., DAC 2006: 445-450
Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha, Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip., ESTImedia 2006: 33-38
Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha, Global Analysis of Resource Arbitration for MPSoC., DSD 2006: 71-78
Alan Fern, Robert Givan, Babak Falsafi, T. N. Vijaykumar, Dynamic feature selection for hardware prediction., Journal of Systems Architecture 52(4): 213-234 (2006)
Alan Mycroft, Andreas Zeller, Compiler Construction 15th International Conference CC 2006 Held as Part of the Joint European Conferences on Theory and Practice of Software ETAPS 2006 Vienna Austria March 30-31 2006 Proceedings, Springer 2006
Alastair F. Donaldson, Alice Miller, Exact and Approximate Strategies for Symmetry Reduction in Model Checking., FM 2006: 541-556
Alastair F. Donaldson, Alice Miller, Symmetry Reduction for Probabilistic Model Checking Using Generic Representatives., ATVA 2006: 9-23
Alastair F. Donaldson, Alice Miller, A Computational Group Theoretic Symmetry Reduction Package for the Spin Model Checker., AMAST 2006: 374-380
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung, A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design., FPL 2006: 1-6
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung, A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design., FCCM 2006: 275-276
Albert Cohen, Marc Duranton, Christine Eisenbeis, Claire Pagetti, Florence Plateau, Marc Pouzet, N-synchronous Kahn networks: a relaxed model of synchrony for real-time systems., POPL 2006: 180-193
Albert Cohen, Sébastien Donadio, María Jesús Garzarán, Christoph Armin Herrmann, Oleg Kiselyov, David A. Padua, In search of a program generator to implement generic transformations for high-performance computing., Sci. Comput. Program. 62(1): 25-46 (2006)
Alberto Ros, Manuel E. Acacio, José M. García, An efficient cache design for scalable glueless shared-memory multiprocessors, CF '06: Proceedings of the 3rd conference on Computing frontiers, ACM, May 2006
Alberto Ros, Manuel E. Acacio, José M. García, An efficient cache design for scalable glueless shared-memory multiprocessors., Conf. Computing Frontiers 2006: 321-330
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato, Full QoS Support with 2 VCs for Single-chip Switches., NCA 2006: 239-242
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato, Scalable Low-Cost QoS Support for Single-chip Switches., ICPADS (1) 2006: 439-446
Alejandro Martínez, George Apostolopoulos, Francisco José Alfaro, José L. Sánchez, José Duato, QoS Support for Video Transmission in High-Speed Interconnects., HPCC 2006: 631-641
Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, Jose Flich, Francisco J. Quiles, José Duato, Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support., Euro-Par 2006: 884-895
Alessandro Bardine, Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete, Analysis of embedded video coder systems: a system-level approach, MEDEA '05: Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture, ACM, March 2006
Alessandro G. Di Nuovo, Knowledge Base Extraction for Fuzzy Diagnosis of Mental Retardation Level., STAIRS 2006: 50-61
Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, An Hybrid Soft Computing Approach for Automated Computer Design., STAIRS 2006: 84-95
Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania, Fuzzy decision making in embedded system design., CODES+ISSS 2006: 223-228
Alessandro G. Di Nuovo, Vincenzo Catania, Maurizio Palesi, The hybrid genetic fuzzy C-means: a reasoned implementation, FS'06: Proceedings of the 7th WSEAS International Conference on Fuzzy Systems, World Scientific and Engineering Academy and Society (WSEAS), June 2006
Alessandro G. Di Nuovo, Vincenzo Catania, Santo Di Nuovo, Serafino Buono, Evolving Fuzzy C-Means: An intelligent technique for efficient diagnosis of children mental retardation level from databases with missing values., IC-AI 2006: 290-296
Alessio Bechini, François Bodin, Cosimo Antonio Prete, Editorial message for the special track on embedded systems: applications solutions and techniques., SAC 2006: 889-890
Alex Gontmakher, Assaf Schuster, Avi Mendelson, Inthreads: a low granularity parallelization model, SIGARCH Computer Architecture News , Volume 34 Issue 1, ACM, March 2006
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gregory Shklover, Speculative synchronization and thread management for fine granularity threads., HPCA 2006: 278-287
Alexander Gendler, Avi Mendelson, Yitzhak Birk, A PAB-Based Multi-Prefetcher Mechanism., International Journal of Parallel Programming 34(2): 171-188 (2006)
Alexander Mendiburu, José Miguel-Alonso, José Antonio Lozano, Implementation and Performance Evaluation of a Parallelization of Estimation of Bayesian Network Algorithms., Parallel Processing Letters 16(1): 133-148 (2006)
Alexander Mendiburu, José Miguel-Alonso, José Antonio Lozano, Evaluation of Parallel EDAs to Create Chemical Calibration Models., e-Science 2006: 118
Alexander Mendiburu, José Miguel-Alonso, José Antonio Lozano, M. Ostra, C. Ubide, Parallel EDAs to create multivariate calibration models for quantitative chemical applications., J. Parallel Distrib. Comput. 66(8): 1002-1013 (2006)
Alexander Sayenko, Olli Alanen, Juha Karhula, Timo Hämäläinen, Ensuring the QoS requirements in 802.16 scheduling., MSWiM 2006: 108-117
Alexander Sayenko, Olli Alanen, O. Karppinen, Timo Hämäläinen, Analysis and Simulation of the Signaling Protocols for the DiffServ Framework., NEW2AN 2006: 566-579
Alexander Sayenko, Timo Hämäläinen, Jyrki Joutsensalo, Lari Kannisto, Comparison and analysis of the revenue-based adaptive queuing models., Computer Networks 50(8): 1040-1058 (2006)
Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes, Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism., European Test Symposium 2006: 213-218
Alexandros Bartzas, M. Peón, Stylianos Mamagkakis, David Atienza, F. Catthoort, Dimitrios Soudris, M. Mendias, Systematic design flow for dynamic data management in visual texture decoder of MPEG-4., ISCAS 2006
Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis, Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications., DATE 2006: 740-745
Alfredo Remón, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Cholesky Factorization of Band Matrices Using Multithreaded BLAS., PARA 2006: 608-616
Alfredo Remón, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Parallel LU Factorization of Band Matrices on SMP Systems., HPCC 2006: 110-118
Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha, Unlocking concurrency., ACM Queue 4(10): 24-33 (2006)
Alice Miller, Alastair F. Donaldson, Muffy Calder, Symmetry in temporal logic model checking., ACM Comput. Surv. 38(3): (2006)
Alok Garg, Fernando Castro, Michael C. Huang, Daniel Chaver, Luis Piñuel, Manuel Prieto, Substituting associative load queue with simple hash tables in out-of-order microprocessors., ISLPED 2006: 268-273
Amund Kvalbein, Audun Fosselie Hansen, Tarik Cicic, Stein Gjessing, Olav Lysne, Fast IP Network Recovery Using Multiple Routing Configurations., INFOCOM 2006
Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. van Gemund, PAM-SoC: A Toolchain for Predicting MPSoC Performance., Euro-Par 2006: 111-123
Ana Lucia Varbanescu, Maik Nijhuis, Arturo González-Escribano, Henk J. Sips, Herbert Bos, Henri E. Bal, SP@CE - An SP-Based Programming Model for Consumer Electronics Streaming Applications., LCPC 2006: 33-48
Anastasios Gounaris, Norman W. Paton, Rizos Sakellariou, Alvaro A. A. Fernandes, Jim Smith, Paul Watson, Modular Adaptive Query Processing for Service-Based Grids., ICAC 2006: 295-296
Anastasios Gounaris, Rizos Sakellariou, Norman W. Paton, Alvaro A. A. Fernandes, A novel approach to resource scheduling for parallel query processing on computational grids., Distributed and Parallel Databases 19(2-3): 87-106 (2006)
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven, Compositional efficient caches for a chip multi-processor., DATE 2006: 345-350
Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven, Static cache partitioning robustness analysis for embedded on-chip multi-processors., Conf. Computing Frontiers 2006: 353-360
Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven, Throughput optimization via cache partitioning for embedded multiprocessors., ICSAMOS 2006: 185-192
Andreas Fidjeland, Wayne Luk, Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming., FPL 2006: 1-6
Andreas Pietzowski, Benjamin Satzger, Wolfgang Trumler, Theo Ungerer, A Bio-inspired Approach for Self-protecting an Organic Middleware with Artificial Antibodies., IWSOS/EuroNGI 2006: 202-215
Andreas Pietzowski, Benjamin Satzger, Wolfgang Trumler, Theo Ungerer, Using Positive and Negative from Immunology for Detection of Anomalies in a Self-Protecting Middleware., GI Jahrestagung (1) 2006: 161-168
Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer, An artificial immune system and its integration into an organic middleware for self-protection., GECCO 2006: 129-130
Andreas S. Andreou, Dimitrios G. Vogiatzis, George A. Papadopoulos, Intelligent Classification and Retrieval of Software Components, COMPSAC '06: Proceedings of the 30th Annual International Computer Software and Applications Conference (COMPSAC'06) - Volume 02 , Volume 02, IEEE Computer Society, September 2006
Andres Mejia, Jose Flich, José Duato, Sven-Arne Reinemo, Tor Skeie, Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori., IPDPS 2006
Andy D. Pimentel, Cagkan Erbas, Simon Polstra, A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels., IEEE Trans. Computers 55(2): 99-112 (2006)
Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas, On the Calibration of Abstract Performance Models for System-level Design Space Exploration., ICSAMOS 2006: 71-77
Andy D. Pimentel, Stamatis Vassiliadis, Editorial., VLSI Signal Processing 43(2-3): 111 (2006)
Angelo Duarte, Dolores Rexachs, Emilio Luque, Increasing the cluster availability using RADIC., CLUSTER 2006
Angelo Duarte, Dolores Rexachs, Emilio Luque, An Intelligent Management of Fault Tolerance in Cluster Using RADICMPI., PVM/MPI 2006: 150-157
Anthony Discolo, Tim Harris, Simon Marlow, Simon L. Peyton Jones, Satnam Singh, Lock Free Data Structures Using STM in Haskell., FLOPS 2006: 65-80
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset, Automatic phase detection for stochastic on-chip traffic generation., CODES+ISSS 2006: 88-93
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset, A Generic Multi-Phase On-Chip Traffic Generation Environment., ASAP 2006: 23-27
Antonio Núñez, Advances in video coding for hand-held device implementation in networked electronic media., J. Real-Time Image Processing 1(1): 9-23 (2006)
Antonio Robles-Gómez, Eva M. García, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, A Model for the Development of AS Fabric Management Protocols., Euro-Par 2006: 853-863
Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Integrated Verification Approach during ADL-Driven Processor Design., IEEE International Workshop on Rapid System Prototyping 2006: 110-118
Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Automatic ADL-based operand isolation for embedded processors., DATE 2006: 600-605
Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen, Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder., DDECS 2006: 59-64
Ari Kulmala, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen, Scalable MPEG-4 encoder on FPGA multiprocessor SOC, EURASIP Journal on Embedded Systems , Volume 2006 Issue 1, Hindawi Publishing Corp., January 2006
Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen, Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA., FPL 2006: 1-6
Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen, Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA., DSD 2006: 83-88
Ari Viinikainen, Jani Puttonen, Miska Sulander, Timo Hämäläinen, Timo Ylönen, Henri Suutarinen, Flow-based fast handover for mobile IPv6 environment - implementation and analysis., Computer Communications 29(16): 3051-3065 (2006)
Ariel N. Burton, Paul H. J. Kelly, Performance prediction of paging workloads using lightweight tracing., Future Generation Comp. Syst. 22(7): 784-793 (2006)
Arik Friedman, Assaf Schuster, Ran Wolff, k-Anonymous Decision Tree Induction., PKDD 2006: 151-162
Armando Sánchez-Peña, Pedro P. Carballo, Luz García, Antonio Núñez, VIPACES Verification Interface Primitives for the Development of AXI Compliant Elements and Systems., DSD 2006: 305-312
Arran Derbyshire, Tobias Becker, Wayne Luk, Incremental elaboration for run-time reconfigurable hardware designs., CASES 2006: 93-102
Artemis A. Christopoulou, Eleftherios D. Polychronopoulos, A Dynamic Lock Protocol for Scope-Consistency sDSM Systems, ICPADS '06: Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1 , Volume 1, IEEE Computer Society, July 2006
Arturo González-Escribano, Diego R. Llanos Ferraris, Speculative Parallelization., IEEE Computer 39(12): 126-128 (2006)
Asadollah Shahbahrami, Ben H. H. Juurlink, Demid Borodin, Stamatis Vassiliadis, Avoiding Conversion and Rearrangement Overhead in SIMD Architectures., International Journal of Parallel Programming 34(3): 237-260 (2006)
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis, Accelerating Color Space Conversion Using Extended Subwords and the Matrix Register File., ISM 2006: 37-46
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis, Improving the memory behavior of vertical filtering in the discrete wavelet transform., Conf. Computing Frontiers 2006: 253-260
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis, Limitations of special-purpose instructions for similarity measurements in media SIMD extensions., CASES 2006: 293-303
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Dynamic thermal clock skew compensation using tunable delay buffers., ISLPED 2006: 162-167
Athanasios Kakarountas, Nikolaos D. Zervas, George Theodoridis, Haralambos Michail, Dimitrios Soudris, Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers., J. Low Power Electronics 2(3): 356-364 (2006)
Austen McDonald, JaeWoong Chung, Brian D. Carlstrom, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun, Architectural Semantics for Practical Transactional Memory., ISCA 2006: 53-65
Avi Mendelson, Memory management challenges in the power-aware computing era., ISMM 2006: 1-2
Babak Falsafi, T. N. Vijaykumar, Power-Aware Computer Systems: 4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers (Lecture Notes in Computer Science), Power-Aware Computer Systems: 4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers (Lecture Notes in Computer Science), Springer-Verlag New York, Inc., January 2006
Baker Abdalhaq, Ana Cortés, Tomàs Margalef, Germán Bianchini, Emilio Luque, Between classical and ideal: enhancing wildland fire prediction using cluster computing., Cluster Computing 9(3): 329-343 (2006)
Bart de Ruijsscher, Georgi Gaydadjiev, Jeroen Lichtenauer, Emile A. Hendriks, FPGA accelerator for real-time skin segmentation., ESTImedia 2006: 93-97
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten, Dynamic-SIMD for lens distortion compensation., ASAP 2006: 261-264
Bartosz Balis, Hong Linh Truong, Marian Bubak, Thomas Fahringer, Krzysztof Guzy, Kuba Rozkwitalski, An Instrumentation Infrastructure for Grid Workflow Applications., OTM Conferences (2) 2006: 1305-1314
Behnaz Pourebrahimi, Koen Bertels, G. M. Kandru, Stamatis Vassiliadis, Market-Based Resource Allocation in Grids., e-Science 2006: 80
Ben Rudiak-Gould, Alan Mycroft, Simon L. Peyton Jones, Haskell Is Not Not ML., ESOP 2006: 38-53
Bertrand Anckaert, Matias Madou, Koen De Bosschere, A Model for Self-Modifying Code., Information Hiding 2006: 232-248
Bilha Mendelson, Shlomit S. Pinter, Ayal Zaks, Introduction., International Journal of Parallel Programming 34(2): 111-112 (2006)
Bill Lin, Isaac Keslassy, The Concurrent Matching Switch Architecture., INFOCOM 2006
Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Hardware and a Tool Chain for ADRES., ARC 2006: 425-430
Bjorn De Sutter, Bruno De Bus, Koen De Bosschere, Bidirectional liveness analysis or how less than half of the Alpha's registers are used., Journal of Systems Architecture 52(10): 535-548 (2006)
Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili, MMR: A MultiMedia Router architecture to support hybrid workloads., J. Parallel Distrib. Comput. 66(2): 307-321 (2006)
Brian D. Carlstrom, Austen McDonald, Hassan Chafi, JaeWoong Chung, Chi Cao Minh, Christoforos E. Kozyrakis, Kunle Olukotun, The Atomos transactional programming language., PLDI 2006: 1-13
Brian D. Carlstrom, JaeWoong Chung, Hassan Chafi, Austen McDonald, Chi Cao Minh, Lance Hammond, Christoforos E. Kozyrakis, Kunle Olukotun, Executing Java programs with transactional memory., Sci. Comput. Program. 63(2): 111-129 (2006)
Burkhard Monien, Guang Gao, Horst Simon, Paul G. Spirakis, Per Stenström, Introduction., J. Parallel Distrib. Comput. 66(5): 615-616 (2006)
Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau, Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems., SiPS 2006: 280-285
Cagkan Erbas, Selin Cerav-Erbas, Andy D. Pimentel, Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design., IEEE Trans. Evolutionary Computation 10(3): 358-374 (2006)
Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten, A Monitoring-Aware Network-on-Chip Design Flow., DSD 2006: 97-106
Calin Ciordas, Kees Goossens, Andrei Radulescu, Twan Basten, NoC monitoring: impact on the design flow., ISCAS 2006
Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto, SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture., ERSA 2006: 63-69
Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, Donatella Sciuto, Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC., IEEE Trans. Computers 55(5): 508-519 (2006)
Carlo Galuzzi, Elena Moscu Panainte, Yana Yankova, Koen Bertels, Stamatis Vassiliadis, Automatic selection of application-specific instruction-set extensions., CODES+ISSS 2006: 160-165
Carlos García, Manuel Prieto, Javier Setoain, Francisco Tirado, Enhancing the Performance of Multigrid Smoothers in Simultaneous Multithreading Architectures., VECPAR 2006: 439-451
Carmen Martínez, Enrique Vallejo, Ramón Beivide, Cruz Izu, Miquel Moretó, Dense Gaussian networks: suitable topologies for on-chip multiprocessors, International Journal of Parallel Programming , Volume 34 Issue 3, Kluwer Academic Publishers, June 2006
Carmen Martínez, Enrique Vallejo, Ramón Beivide, Cruz Izu, Miquel Moretó, Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors., International Journal of Parallel Programming 34(3): 193-211 (2006)
Catherine Dezan, Erwan Fabiani, Christophe Gouyen, Loïc Lagadec, Bernard Pottier, Caaliph Andriamisaina, Alix Poungou, Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques., Technique et Science Informatiques 25(7): 893-920 (2006)
Chaiyasit Manovit, Sudheendra Hangal, Hassan Chafi, Austen McDonald, Christos Kozyrakis, Kunle Olukotun, Testing implementations of transactional memory., PACT 2006: 134-143
Changhua Wu, Weihua Sheng, Wen-Zhan Song, A Dynamic MDS-Based Localization Algorithm for Mobile Sensor Networks., ROBIO 2006: 496-501
Chantal Ykman-Couvreur, Vincent Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal, Pareto-Based Application Specification for MP-SoC Customized Run-Time Management., ICSAMOS 2006: 78-84
Chengjun Zhu, Yuanxin Ouyang, Lei Gao, Zhenyong Chen, Zhang Xiong, An Automatic Video Text Detection Localization and Extraction Approach., SITIS 2006: 1-9
Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen, Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip., VLSI-SoC 2006: 80-85
Chris R. Jesshope, muTC - An Intermediate Language for Programming Chip Multiprocessors., Asia-Pacific Computer Systems Architecture Conference 2006: 147-160
Chris R. Jesshope, Microthreading a Model for Distributed Instruction-level Concurrency., Parallel Processing Letters 16(2): 209-228 (2006)
Chris R. Jesshope, Alexander V. Shafarenko, Guest Editor's Introduction (Part 2)., International Journal of Parallel Programming 34(4): 319-322 (2006)
Chris R. Jesshope, Alexander V. Shafarenko, Special issue on Micro-grids - Guest Editor Introduction., International Journal of Parallel Programming 34(3): 189-192 (2006)
Chris R. Jesshope, Colin Egan, Advances in Computer Systems Architecture 11th Asia-Pacific Conference ACSAC 2006 Shanghai China September 6-8 2006 Proceedings, Springer 2006
Christian Neeb, Norbert Wehn, Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip., DSD 2006: 665-672
Christine Nardini, Daniele Masotti, Sungroh Yoon, Enrico Macii, Michael D. Kuo, Giovanni De Micheli, Luca Benini, Mining Gene Sets for Measuring Similarities., ISCC 2006: 227-232
Christophe Poucet, David Atienza, Francky Catthoor, Template-Based Semi-Automatic Profiling of Multimedia Applications., ICME 2006: 1061-1064
Christos Koulamas, Aggeliki S. Prayati, Gauthier Lafruit, George Papadopoulos, Measurements and modeling of resource consumption in wireless video streaming: the decoder case., WMuNeP 2006: 67-72
Christos-Savvas Bouganis, Peter Y. K. Cheung, Li Zhaoping, FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex., FPL 2006: 1-6
Chuan Yue, Richard Tran Mills, Andreas Stathopoulos, Dimitrios S. Nikolopoulos, Runtime Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory., HPDC 2006: 183-194
Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk, Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation., ERSA 2006: 184-190
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo, Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs., FCCM 2006: 35-44
Claire Burguière, Christine Rochange, History-based Schemes and Implicit Path Enumeration., WCET 2006
Claudio Brunelli, Fabio Garzia, Jari Nurmi, A Coarse-Grain Reconfigurable Machine with Floating-Point Arithmetic Capabilities., ReCoSoC 2006: 1-7
Clemens Moser, Davide Brunelli, Lothar Thiele, Luca Benini, Lazy Scheduling for Energy Harvesting Sensor Nodes., DIPES 2006: 125-134
Clemens Moser, Lothar Thiele, Luca Benini, Davide Brunelli, Real-Time Scheduling with Regenerative Energy., ECRTS 2006: 261-270
Colin F. Snook, Michael Poppleton, Ian Johnson, Towards a Method for Rigorous Development of Generic Requirements Patterns., RODIN Book 2006: 326-342
Concepción Sanz, Manuel Prieto, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, System-level process variability compensation on memory organizations of dynamic applications: a case study., ISQED 2006: 376-382
Constantino G. Ribeiro, Marcelo Cintra, Quantifying Uncertainty in Points-To Relations., LCPC 2006: 190-204
Cor Meenderinck, Sorin Cotofana, High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology., SAMOS 2006: 447-456
Cor Meenderinck, Sorin Cotofana, Electron counting based high-radix multiplication in single electron tunneling technology., ISCAS 2006
Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Cacheflow: Cache Optimizations for Data Driven Multithreading., Parallel Processing Letters 16(2): 229-244 (2006)
Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Data-Driven Multithreading Using Conventional Microprocessors., IEEE Trans. Parallel Distrib. Syst. 17(10): 1176-1188 (2006)
Cristiana Bolchini, Carlo Curino, Fabio A. Schreiber, Letizia Tanca, Context Integration for Mobile Data Tailoring., MDM 2006: 5
Cristiana Bolchini, Carlo Curino, Fabio A. Schreiber, Letizia Tanca, Context integration for mobile data tailoring., SEBD 2006: 48-55
Cristiana Bolchini, Elisa Quintarelli, Context-Driven Data Filtering: A Methodology., OTM Workshops (2) 2006: 1986-1995
Cristiana Bolchini, Paolo Ferrandi, Pier Luca Lanzi, Fabio Salice, Evolving classifiers on field programmable gate arrays: Migrating XCS to FPGAs., Journal of Systems Architecture 52(8-9): 516-533 (2006)
Cruz Izu, José Miguel-Alonso, José A. Gregorio, Effects of Injection Pressure on Network Throughput., PDP 2006: 91-98
Cyril Banino-Rokkones, Olivier Beaumont, Lasse Natvig, Master-Slave Tasking on Asymmetric Networks., Euro-Par 2006: 167-176
Dan Tsafrir, Dror G. Feitelson, Instability in parallel job scheduling simulation: the role of workload flurries., IPDPS 2006
Dan Tsafrir, Dror G. Feitelson, The Dynamics of Backfilling: Solving the Mystery of Why Increased Inaccuracy May Help., IISWC 2006: 131-141
Dan Wallin, Henrik Löf, Erik Hagersten, Sverker Holmgren, Multigrid and Gauss-Seidel smoothers revisited: parallelization on chip multiprocessors., ICS 2006: 145-155
Daniel Gracia Pérez, Hugues Berry, Olivier Temam, A Sampling Method Focusing on Practicality., IEEE Micro 26(6): 14-28 (2006)
Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala, Software Implementation of WiMAX on the Sandbridge SandBlaster Platform., SAMOS 2006: 435-446
Daniel Ziener, Stefan Assmus, Jürgen Teich, Identifying FPGA IP-Cores Based on Lookup Table Content Analysis., FPL 2006: 1-6
Daniele Masotti, Elisa Ficarra, Enrico Macii, Luca Benini, Optimized Technique for Dna Structural Properties Discovering., International Journal on Artificial Intelligence Tools 15(5): 695-710 (2006)
Daniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor, Diederik Verkest, Software Simultaneous Multi-Threading a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism., PATMOS 2006: 12-23
David Atienza, Jose Manuel Mendias, Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor, Systematic dynamic memory management design methodology for reduced memory footprint., ACM Trans. Design Autom. Electr. Syst. 11(2): 465-489 (2006)
David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip., DAC 2006: 618-623
David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo, Compiler-Driven Leakage Energy Reduction in Banked Register Files., PATMOS 2006: 107-116
David Atienza, Stylianos Mamagkakis, Francesco Poletti, Jose Manuel Mendias, Francky Catthoor, Luca Benini, Dimitrios Soudris, Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems., Integration 39(2): 113-130 (2006)
David B. Thomas, Wayne Luk, Non-Uniform Random Number Generation Through Piecewise Linear Approximations., FPL 2006: 1-6
David B. Thomas, Wayne Luk, Efficient Hardware Generation of Random Variates with Arbitrary Distributions., FCCM 2006: 57-66
David F. Bacon, Perry Cheng, Daniel Frampton, David Grove, Matthias Hauswirth, V. T. Rajan, Demonstration: On-Line Visualization and Analysis of Real-Time Systems with TuningFork., CC 2006: 96-100
David Gregg, M. Anton Ertl, Optimizing code-copying JIT compilers for virtual stack machines., Concurrency and Computation: Practice and Experience 18(11): 1465-1484 (2006)
David J. Pearce, Paul H. J. Kelly, A dynamic topological sort algorithm for directed acyclic graphs., ACM Journal of Experimental Algorithmics 11: (2006)
David Montaner, Joaquín Tárraga, Jaime Huerta-Cepas, Jordi Burguet-Castell, Juan M. Vaquerizas, Lucía Conde, Pablo Minguez, Javier Vera, Sach Mukherjee, Joan Valls, Miguel A. G. P, Next station in microarray data analysis: GEPAS., Nucleic Acids Research 34(Web-Server-Issue): 486-491 (2006)
David Ródenas, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, George Almási, Călin Caşcaval, José Castaños, José Moreira, Exploiting multilevel parallelism using OpenMP on a massive multithreaded architecture, Journal of Embedded Computing , Volume 2 Issue 2, IOS Press, April 2006
David Verstraeten, Benjamin Schrauwen, Dirk Stroobandt, Reservoir-based techniques for speech recognition., IJCNN 2006: 1050-1053
Davide Brunelli, Elisabetta Farella, Laura Rocchi, Marco Dozza, Lorenzo Chiari, Luca Benini, Bio-feedback System for Rehabilitation Based on a Wireless Body Area Network., PerCom Workshops 2006: 527-531
Davy Genbrugge, Lieven Eeckhout, Koen De Bosschere, Accurate memory data flow modeling in statistical simulation., ICS 2006: 87-96
Derin Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici, A Predictable Communication Scheme for Embedded Multiprocessor Systems., VLSI-SoC 2006: 152-157
Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers, Offset assignment using simultaneous variable coalescing., ACM Trans. Embedded Comput. Syst. 5(4): 864-883 (2006)
Diana Göhringer, Mateusz Majer, Jürgen Teich, Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine., Dynamically Reconfigurable Architectures 2006
Diego Andrade, Basilio B. Fraguela, Ramon Doallo, Analytical modeling of codes with arbitrary data-dependent conditional structures., Journal of Systems Architecture 52(7): 394-410 (2006)
Diego Andrade, Basilio B. Fraguela, Ramon Doallo, Cache Behavior Modelling for Codes Involving Banded Matrices., LCPC 2006: 205-219
Diego R. Llanos Ferraris, TPCC-UVa: an open-source TPC-C implementation for global performance measurement of computer systems., SIGMOD Record 35(4): 6-15 (2006)
Diego R. Llanos Ferraris, Belén Palop, TPCC-UVa: an open-source TPC-C implementation for parallel and distributed systems., IPDPS 2006
Diego Sevilla, José M. García, Antonio Gómez, Automatic Code Generation for Non-Funtional Aspects in the CORBA-LC Component Model., ICUC 2006
Dionisios N. Pnevmatikatos, Aggelos Arelakis, Variable-Length Hashing for Exact Pattern Matching., FPL 2006: 1-6
Dirk Koch, Matthiaas Koerber, Jürgen Teich, Searching RC5-Keys with Distributed Reconfigurable Computing., ERSA 2006: 42-48
Dirk Koch, Thilo Streichert, Steffen Dittrich, Christian Strengert, Christian Haubelt, Jürgen Teich, An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks., ARCS 2006: 202-216
Djemai Kebbal, Pascal Sainrat, Combining Symbolic Execution and Path Enumeration in Worst-Case Execution Time Analysis., WCET 2006
Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich, A Generic Framework for Rapid Prototyping of System-on-Chip Designs., CDES 2006: 189-195
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template., ReCoSoC 2006: 31-37
Domenico Talia, Angelos Bilas, Marios D. Dikaiakos, Knowledge and Data Management in GRIDs, Knowledge and Data Management in GRIDs, Springer-Verlag New York, Inc., November 2006
Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque, Evaluation of the field-programmable cache: performance and energy consumption., Conf. Computing Frontiers 2006: 361-372
Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque, A Reconfigurable Data Cache for Adaptive Processors., ARC 2006: 230-242
Don M. Dini, Michael van Lent, Paul Carpenter, K. Iyer, Building Robust Planning and Exection Systems for Virtual Worlds., AIIDE 2006: 29-35
Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee, Reducing energy of virtual cache synonym lookup using bloom filters., CASES 2006: 179-189
Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides, Accuracy-Guaranteed Bit-Width Optimization., IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1990-2000 (2006)
Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong, A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis., IEEE Trans. Computers 55(6): 659-671 (2006)
Dorit Nuzman, Ira Rosen, Ayal Zaks, Auto-vectorization of interleaved data for SIMD., PLDI 2006: 132-143
Dorit Nuzman, Richard Henderson, Multi-platform Auto-vectorization., CGO 2006: 281-294
Dragan Stojanovic, Book Reviews: Web Service-Oriented Project Development from Different Perspectives, IEEE Distributed Systems Online , Volume 7 Issue 2, IEEE Educational Activities Department, February 2006
Dries Buytaert, Jonas Maebe, Lieven Eeckhout, Koen De Bosschere, Building Java program analysis tools using Javana., OOPSLA Companion 2006: 653-654
Dror Feitelson, Eitan Frachtenberg, Larry Rudolph, Uwe Schwiegelshohn, Job Scheduling Strategies for Parallel Processing: 11th International Workshop, JSSPP 2005, Cambridge, MA, USA, June 19, 2005, Revised Selected Papers (Lecture Notes in Computer Science), Job Scheduling Strategies for Parallel Processing: 11th International Workshop, JSSPP 2005, Cambridge, MA, USA, June 19, 2005, Revised Selected Papers (Lecture Notes in Computer Science), Springer-Verlag New York, Inc., January 2006
Dror G. Feitelson, Metrics for Mass-Count Disparity., MASCOTS 2006: 61-68
Dror G. Feitelson, Dan Tsafrir, Workload sanitation for performance evaluation., ISPASS 2006: 221-230
Dror G. Feitelson, Gillian Z. Heller, Stephen R. Schach, An Empirically-Based Criterion for Determining the Success of an Open-Source Project., ASWEC 2006: 363-368
Edi Shmueli, Dror G. Feitelson, Using Site-Level Modeling to Evaluate the Performance of Parallel System Schedulers., MASCOTS 2006: 167-178
Eduard Ayguadé, Gerald Baumgartner, J. Ramanujam, P. Sadayappan, Languages and Compilers for Parallel Computing 18th International Workshop LCPC 2005 Hawthorne NY USA October 20-22 2005 Revised Selected Papers, Springer 2006
Eduard Ayguadé, Marc González, Xavier Martorell, Gabriele Jost, Employing nested OpenMP for the parallelization of multi-zone computational fluid dynamics applications., J. Parallel Distrib. Comput. 66(5): 686-697 (2006)
Eduard Ayguadé, Wolfgang Karl, Koen De Bosschere, Jean-Francois Collard, Topic 7: Parallel Computer Architecture and Instruction Level Parallelism., Euro-Par 2006: 459
Eduardo Argollo, Adriana Gaudiani, Dolores Rexachs, Emilio Luque, Tuning Application in a Multi-cluster Environment., Euro-Par 2006: 78-88
Eduardo César, A. Moreno, Joan Sorribes, Emilio Luque, Modeling Master/Worker applications for automatic performance tuning., Parallel Computing 32(7-8): 568-589 (2006)
Edwin V. Bonilla, Christopher K. I. Williams, Felix V. Agakov, John Cavazos, John Thomson, Michael F. P. O'Boyle, Predictive search distributions., ICML 2006: 121-128
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Parallel Memory Implementation for Arbitrary Stride Accesses., ICSAMOS 2006: 1-6
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Parallel Memory Architecture for Arbitrary Stride Accesses., DDECS 2006: 65-70
Eero Wallenius, Timo Hämäläinen, Timo Nihtilä, Jani Puttonen, Jyrki Joutsensalo, Simulation Study on 3G and WLAN Inter-Working., IEICE Transactions 89-B(2): 446-459 (2006)
Eiko Yoneki, Pascal Felber, RDDS 2006 PC Co-chairs' Message., OTM Workshops (2) 2006: 1469
Electra Tamani, Paraskevas Evripidou, Applying Trust Mechanisms in an agent-based P2P Network of Service Providers and Requestors., CCGRID 2006: 13
Electra Tamani, Paraskevas Evripidou, A Pragmatic and Pervasive Methodology to Web Service Discovery., OTM Workshops (2) 2006: 1285-1294
Eleftheria Katsiri, Alan Mycroft, Applying Bayesian Networks to Sensor-Driven Systems., ISWC 2006: 149-150
Eleftherios Tiakas, Apostolos N. Papadopoulos, Alexandros Nanopoulos, Yannis Manolopoulos, Dragan Stojanovic, Slobodanka Djordjevic-Kajan, Trajectory Similarity Search in Spatial Networks, IDEAS '06: Proceedings of the 10th International Database Engineering and Applications Symposium, IEEE Computer Society, December 2006
Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis, Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration., VLSI Signal Processing 43(2-3): 161-172 (2006)
Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis, Compiler-driven FPGA-area allocation for reconfigurable computing., DATE 2006: 369-374
Elias Athanasopoulos, Kostas G. Anagnostakis, Evangelos P. Markatos, Misusing Unstructured P2P Systems to Perform DoS Attacks: The Network That Never Forgets., ACNS 2006: 130-145
Elisa Ficarra, Enrico Macii, Giovanni De Micheli, Luca Benini, Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images., CBMS 2006: 413-418
Elisabetta Farella, Augusto Pieracci, Luca Benini, Andrea Acquaviva, A Wireless Body Area Sensor Network for Posture Detection., ISCC 2006: 454-459
Elisabetta Farella, M. Sile O'Modhrain, Luca Benini, Bruno Riccò, Gesture Signature for Ambient Intelligence Applications: A Feasibility Study., Pervasive 2006: 288-304
Eric Petit, François Bodin, Guillaume Papaure, Florence Dru, Poster reception - ASTEX: a hot path based thread extractor for distributed memory system on a chip., SC 2006: 141
Erik Berg, Håkan Zeffer, Erik Hagersten, A statistical multiprocessor cache model., ISPASS 2006: 89-99
Erno Salminen, Tero Kangas, Timo D. Hämäläinen, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, HIBI Communication Network for System-on-Chip., VLSI Signal Processing 43(2-3): 185-205 (2006)
Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis, Nectarios Koziris, Exploring the Capacity of a Modern SMT Architecture to Deliver High Scientific Application Performance., HPCC 2006: 180-189
Evangelos Koukis, Nectarios Koziris, Memory and Network Bandwidth Aware Scheduling of Multiprogrammed Workloads on Clusters of SMPs., ICPADS (1) 2006: 345-354
Fátima Al-Shahrour, Pablo Minguez, Joaquín Tárraga, David Montaner, Eva Alloza, Juan M. Vaquerizas, Lucía Conde, Christian Blaschke, Javier Vera, Joaquín Dopazo, BABELOMICS: a systems biology perspective in the functional annotation of genome-scale experiments., Nucleic Acids Research 34(Web-Server-Issue): 472-476 (2006)
Félix Tobajas, Roberto Esper-Chaín, Raúl Regidor, O. Santana, Roberto Sarmiento, A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology., DDECS 2006: 21-26
F. Bagci, H. Schick, J. Petzold, W. Trumler, T. Ungerer, The reflective mobile agent paradigm implemented in a smart office environment, Personal and Ubiquitous Computing , Volume 11 Issue 1, Springer-Verlag, October 2006
F. Blachot, Benoît Dupont de Dinechin, Guillaume Huard, SCAN: A Heuristic for Near-Optimal Software Pipelining., Euro-Par 2006: 289-298
Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenzo Rana, Marco D. Santambrogio, VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow., IPDPS 2006
Fabrizio Petrini, Olav Lysne, Ron Brightwell, Guest Editors' Introduction: High-Performance Interconnects., IEEE Micro 26(3): 7-9 (2006)
Fadia Nemer, Hugues Cassé, Pascal Sainrat, Jean Paul Bahsoun, Marianne De Michiel, PapaBench: a Free Real-Time Benchmark., WCET 2006
Farrukh Nadeem, Muhammad Murtaza Yousaf, Radu Prodan, Thomas Fahringer, Soft Benchmarks-Based Application Performance Prediction Using a Minimum Training Set., e-Science 2006: 71
Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli, Reliability Support for On-Chip Memories Using Networks-on-Chip., ICCD 2006
Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini, An integrated open framework for heterogeneous MPSoC design space exploration., DATE 2006: 1145-1150
Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo, Contrasting a NoC and a traditional interconnect fabric with layout awareness., DATE 2006: 124-129
Felipe Cabarcas, Richard Demo Souza, Javier Garcia-Frias, Turbo coding of strongly nonuniform memoryless sources with unequal energy allocation and PAM signaling., IEEE Transactions on Signal Processing 54(5): 1942-1946 (2006)
Felix V. Agakov, Edwin V. Bonilla, John Cavazos, Björn Franke, Grigori Fursin, Michael F. P. O'Boyle, John Thomson, Marc Toussaint, Christopher K. I. Williams, Using Machine Learning to Focus Iterative Optimization., CGO 2006: 295-305
Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado, A Load-Store Queue Design Based on Predictive State Filtering., J. Low Power Electronics 2(1): 27-36 (2006)
Fernando Castro, Luis Piñuel, Daniel Chaver, Manuel Prieto, Michael C. Huang, Francisco Tirado, DMDC: Delayed Memory Dependence Checking through Age-Based Filtering., MICRO 2006: 297-308
Fernando Guirado, Ana Ripoll, Concepció Roig, Aura Hernandez, Emilio Luque, Exploiting Throughput for Pipeline Execution in Streaming Image Processing Applications., Euro-Par 2006: 1095-1105
Filipa Duarte, Stephan Wong, Profiling Bluetooth and Linux on the Xilinx Virtex II Pro., DSD 2006: 229-235
Florent Bouchez, Alain Darte, Christophe Guillon, Fabrice Rastello, Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How., LCPC 2006: 283-298
Florentin Picioroaga, Uwe Brinkschulte, Flexible QoS management and real-time in OSA+ middleware., PDPTA 2006: 984-990
Florin Isaila, David E. Singh, Jesús Carretero, Félix García, On Evaluating Decentralized Parallel I/O Scheduling Strategies for Parallel File Systems., VECPAR 2006: 120-130
Florin Isaila, David E. Singh, Jesús Carretero, Félix García, Gabor Szeder, Thomas Moschny, Integrating Logical and Physical File Models in the MPI-IO Implementation for "Clusterfile"., CCGRID 2006: 462
Francesc Guim, Ivan Rodero, Julita Corbalán, Jesús Labarta, Ariel Oleksiak, Tomasz Kuczynski, Dawid Szejnfeld, Jarek Nabrzyski, Uniform Job Monitoring using the HPC-Europa Single Point of Access., CCGRID 2006: 55
Francesc Guim, Ivan Rodero, M. Tomas, Julita Corbalán, Jesús Labarta, The Palantir Grid Meta-Information System., GRID 2006: 329-330
Francesco Belletti, Sebastiano Fabio Schifano, Raffaele Tripiccione, François Bodin, Philippe Boucaud, Jacques Micheli, Olivier Pène, Nicola Cabibbo, Sergio de Luca, Alessandro Lonardo, , Computing for LQCD: apeNEXT., Computing in Science and Engineering 8(1): 18-29 (2006)
Francesco Bruschi, Fabrizio Ferrandi, A SystemC-based Framework of Communication Architecture., FDL 2006: 319-327
Francesco Nerieri, Radu Prodan, Thomas Fahringer, Hong Linh Truong, Overhead Analysis of Grid Workflow Applications., GRID 2006: 17-24
Francesco Rossi, Massimo Rovini, Luca Fanucci, Design and Validation of Digital Channels for a Galileo Receiver Prototype., DSD 2006: 545-549
Francisco Almeida, Sergio Barrachina, Vicente Blanco Pérez, E. Quintana, Adrián Santos, An Open Source Web Service Based Platform for Heterogeneous Clusters., ISPA 2006: 760-771
Francisco Almeida, Sergio Barrachina, Vicente Blanco Pérez, Enrique S. Quintana-Ortí, Adrián Santos, An Open Source Web Service Based Platform for Heterogeneous Clusters., ISPA 2006: 760-771
Francisco Delicado, Pedro Cuenca, Luis Orozco-Barbosa, QoS mechanisms for multimedia communications over TDMA/TDD WLANs., Computer Communications 29(13-14): 2721-2735 (2006)
Francisco Delicado, Pedro Cuenca, Luis Orozco-Barbosa, QoS-Aware Video Communications over TDMA/TDD Wireless Networks., PWC 2006: 50-63
Francisco Gilabert, María Engracia Gómez, Pedro López, José Duato, On the Influence of the Selection Function on the Performance of Fat-Trees., Euro-Par 2006: 864-873
Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero, Predictable Performance in SMT Processors: Synergy between the OS and SMTs., IEEE Trans. Computers 55(7): 785-799 (2006)
Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata, Pipelined Range Reduction for Floating Point Numbers., ASAP 2006: 145-152
Francisco J. Villa, Manuel E. Acacio, José M. García, On the Evaluation of Dense Chip-Multiprocessor Architectures., ICSAMOS 2006: 21-27
Frank Hannig, Hritam Dutta, Jürgen Teich, Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology., IJES 2(1/2): 114-127 (2006)
Frank Kienle, Timo Lehnigk-Emden, Norbert Wehn, Fast convergence algorithm for LDPC Codes., VTC Spring 2006: 2393-2397
Frank Olaf Sem-Jacobsen, Olav Lysne, Tor Skeie, Combining Source Routing and Dynamic Fault Tolerance., SBAC-PAD 2006: 151-158
Frank Olaf Sem-Jacobsen, Tor Skeie, Olav Lysne, José Duato, Dynamic Fault Tolerance with Misrouting in Fat Trees., ICPP 2006: 33-44
Frederic Worm, Patrick Thiran, Paolo Ienne, Designing Robust Checkers in the Presence of Massive Timing Errors., IOLTS 2006: 281-286
Fredrik Dahlgren, Partial Continuous Functions and Admissible Domain Representations., CiE 2006: 94-104
Fredrik Warg, Per Stenström, Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush., SBAC-PAD 2006: 91-98
Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures., FPL 2006: 1-8
Friman Sánchez, Esther Salamí, Alex Ramírez, Mateo Valero, Performance Analysis of Sequence Alignment Applications., IISWC 2006: 51-60
Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis, Networks on chips for high-end consumer-electronics TV system architectures., DATE Designers' Forum 2006: 148-153
Gabriel Rodríguez, María J. Martín, Patricia González, Juan Touriño, Controller/Precompiler for Portable Checkpointing., IEICE Transactions 89-D(2): 408-417 (2006)
Gamal Atallah, Gabriel Rodríguez, Indirectpatent citations., Scientometrics 67(3): 437-465 (2006)
Ganesh Bikshandi, Jia Guo, Christoph von Praun, Gabriel Tanase, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Lawrence Rauchwerger, Design and Use of htalib - A Library for Hierarchically Tiled Arrays., LCPC 2006: 17-32
Ganesh Bikshandi, Jia Guo, Daniel Hoeflinger, Gheorghe Almási, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Christoph von Praun, Programming for parallelism and locality with hierarchically tiled arrays., PPOPP 2006: 48-57
Gary Wang, Zoran Salcic, Morteza Biglari-Abhari, Customizing multiprocessor implementation of an automated video surveillance system, EURASIP Journal on Embedded Systems , Volume 2006 Issue 1, Hindawi Publishing Corp., January 2006
Gaspar Mora, Jose Flich, José Duato, Pedro López, Elvira Baydal, Olav Lysne, Towards an efficient switch architecture for high-radix switches., ANCS 2006: 11-20
Genaro Costa, Anna Morajko, Tomàs Margalef, Emilio Luque, Automatic Tuning in Computational Grids., PARA 2006: 381-389
George A. Papadopoulos, Aristos Stavrou, Odysseas Papapetrou, An implementation framework for software architectures based on the coordination paradigm, Science of Computer Programming , Volume 60 Issue 1, Elsevier North-Holland, Inc., March 2006
George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis, Testability Analysis and Scalable Test Generation for High-Speed Floating Point Units, IEEE Transactions on Computers, vol. 55, no. 11, pp. 1449-1457, November 2006.
Georgi Gaydadjiev, C. John Glossner, Jarmo Takala, Stamatis Vassiliadis, Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (IC-SAMOS 2006) Samos Greece July 17-20 2006, IEEE 2006
Georgi Gaydadjiev, Stamatis Vassiliadis, SAD Prefetching for MPEG4 Using Flux Caches., SAMOS 2006: 248-258
Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis, Multimedia rectangularly addressable memory., IEEE Transactions on Multimedia 8(2): 315-322 (2006)
Georgios I. Goumas, Nikolaos Drosinos, Maria Athanasaki, Nectarios Koziris, Message-passing code generation for non-rectangular tiling transformations., Parallel Computing 32(10): 711-732 (2006)
Georgios Keramidas, Konstantinos Aisopos, Stefanos Kaxiras, Dynamic Dictionary-Based Data Compression for Level-1 Caches., ARCS 2006: 114-129
Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios N. Serpanos, Preventing Denial-of-Service Attacks in Shared CMP Caches., SAMOS 2006: 359-372
Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal, Paul M. Heysters, Efficient architectures for streaming applications., Dynamically Reconfigurable Architectures 2006
Gerard K. Rauwerda, Gerard J. M. Smit, Casper R. W. van Benthem, Paul M. Heysters, Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture., ERSA 2006: 110-116
Gerardo Fernández, Pedro Cuenca, Luis Orozco-Barbosa, Hari Kalva, Very low complexity MPEG-2 to H.264 transcoding using machine learning., ACM Multimedia 2006: 931-940
Gerardo Fernández-Escribano, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, RD-Optimization for MPEG-2 to H.264 Transcoding., ICME 2006: 309-312
Gerardo Fernández-Escribano, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, Speeding-Up the Macroblock Partition Mode Decision in MPEG-2/H.264 Transcoding., ICIP 2006: 869-872
Germán Bianchini, Ana Cortés, Tomàs Margalef, Emilio Luque, Improved Prediction Methods for Wildfires Using High Performance Computing: A Comparison., International Conference on Computational Science (1) 2006: 539-546
Giacomo Paci, Paul Marchal, Francesco Poletti, Luca Benini, Exploring "temperature-aware" design in low-power MPSoCs., DATE 2006: 838-843
Gianluca Casarosa, Michele Apuzzo, Luca Fanucci, Bruno Sarti, Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small Satellites., DSD 2006: 338-345
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos, Fast bit permutation unit for media enhanced microprocessors., ISCAS 2006
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos, An Energy-Delay Efficient Subword Permutation Unit., ASAP 2006: 245-252
Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto, Synthesis of Object Oriented Models on Reconfigurable Hardware., ERSA 2006: 249-250
Giovanni Agosta, Marco D. Santambrogio, Seda Ogrenci Memik, Adaptive Metrics for System-Level Functional Partitioning., FDL 2006: 153-155
Giovanni Agosta, Stefano Crespi Reghizzi, Dario Domizioli, Martino Sykora, Global instruction scheduling in dynamic compilation for embedded systems, JTRES '06: Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems, ACM, October 2006
Giovanni Agosta, Stefano Crespi Reghizzi, Gabriele Svelto, Jelatine: a virtual machine for small embedded systems, JTRES '06: Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems, ACM, October 2006
Giovanni Beltrame, Dario Bruschi, Donatella Sciuto, Cristina Silvano, Decision-theoretic exploration of multiProcessor platforms., CODES+ISSS 2006: 205-210
Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard, Chuck Pilkington, Exploiting TLM and object introspection for system-level simulation., DATE 2006: 100-105
Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane, An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures., VLSI-SoC 2006: 146-151
Giovanni Busonera, Salvatore Carta, Andrea Marongiu, Luigi Raffo, Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information., DSD 2006: 265-268
Giovanni De Micheli, Luca Benini, Networks on Chips: Technology and Tools (Systems on Silicon), Networks on Chips: Technology and Tools (Systems on Silicon), Morgan Kaufmann Publishers Inc., July 2006
Girma S. Tewolde, Weihua Sheng, Ant Colony Optimization for Tool Path Integration in Spray Forming Processes., IROS 2006: 2394-2399
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design., ICSAMOS 2006: 115-122
Giuseppe Ascia, Vincenzo Catania, Daniela Panno, An integrated fuzzy-GA approach for buffer management., IEEE T. Fuzzy Systems 14(4): 528-541 (2006)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip., J. UCS 12(4): 370-394 (2006)
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti, Neighbors-on-Path: A New Selection Strategy for On-Chip Networks., ESTImedia 2006: 79-84
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti, A new selection policy for adaptive routing in network on chip, EHAC'06: Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications, World Scientific and Engineering Academy and Society (WSEAS), February 2006
Grzegorz Danilewicz, Wojciech Kabacinski, Comments on "Wide-sense nonblocking multicast Log/sub 2/(N m p) Networks"., IEEE Transactions on Communications 54(6): 980-982 (2006)
Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Ozcan Ozturk, I. Demirkiran, Compiler-Directed Management of Leakage Power in Software-Managed Memories., ISVLSI 2006: 450-451
Guangyu Chen, Feihui Li, Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu, Leakage-Aware SPM Management., ISVLSI 2006: 393-398
Guido Bertoni, Luca Breveglieri, Farina Roberto, Francesco Regazzoni, Speeding Up AES By Extending a 32 bit Processor Instruction Set., ASAP 2006: 275-282
Guilin Chen, Ozcan Ozturk, Mahmut T. Kandemir, Mustafa Karaköy, Dynamic scratch-pad memory management for irregular array access patterns., DATE 2006: 931-936
Guillaume Chelius, Antoine Fraboulet, Eric Fleury, Demonstration of worldsens: a fast prototyping and performance evaluation of wireless sensor network applications & protocols, REALMAN '06: Proceedings of the 2nd international workshop on Multi-hop ad hoc networks: from theory to reality, ACM, May 2006
Guillermo L. Taboada, Juan Touriño, Ramon Doallo, Efficient Java Communication Protocols on High-speed Cluster Interconnects., LCN 2006: 264-271
Guillermo L. Taboada, Juan Touriño, Ramon Doallo, Non-blocking Java Communications Support on Clusters., PVM/MPI 2006: 256-265
Gustavo M. Callicó, Rafael Peset Llopis, Sebastian López, José Fco. López, Antonio Núñez, Ramanathan Sethuraman, Roberto Sarmiento, Low-cost super-resolution algorithms implementation over a HW/SW video compression platform, EURASIP Journal on Applied Signal Processing , Volume 2006 Issue 1, Hindawi Publishing Corp., January 2006
Håkan Zeffer, Zoran Radovic, Erik Hagersten, Exploiting locality: a flexible DSM approach., IPDPS 2006
Håkan Zeffer, Zoran Radovic, Martin Karlsson, Erik Hagersten, TMA: a trap-based memory architecture., ICS 2006: 259-268
Haakon Dybdahl, Marius Grannæs, Lasse Natvig, Cache Write-Back Schemes for Embedded Destructive-Read DRAM., ARCS 2006: 145-159
Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs, Lasse Natvig, Destructive-read in embedded DRAM, impact on power consumption, Journal of Embedded Computing , Volume 2 Issue 2, IOS Press, April 2006
Haakon Dybdahl, Per Stenström, Lasse Natvig, An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches, MEDEA '06: Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures, ACM, September 2006
Haakon Dybdahl, Per Stenström, Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination., Asia-Pacific Computer Systems Architecture Conference 2006: 52-66
Haakon Dybdahl, Per Stenström, Lasse Natvig, A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors., HiPC 2006: 22-34
Hadda Cherroun, Alain Darte, Paul Feautrier, Scheduling under resource constraints using dis-equations., DATE 2006: 1067-1072
Hagit Attiya, David Hay, Isaac Keslassy, Packet-mode emulation of output-queued switches., SPAA 2006: 138-147
Hagit Attiya, Faith Ellen, Panagiota Fatourou, The Complexity of Updating Multi-writer Snapshot Objects., ICDCN 2006: 319-330
Hakduran Koc, Ozcan Ozturk, Mahmut T. Kandemir, Sri Hari Krishna Narayanan, Ehat Ercanli, Minimizing energy consumption of banked memories using data recomputation., ISLPED 2006: 358-362
Hakduran Koc, Suleyman Tosun, Ozcan Ozturk, Mahmut T. Kandemir, Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems., ISVLSI 2006: 448-449
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Pieter P. Jonker, Run-time reconfiguration of communication in SIMD architectures., IPDPS 2006
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Richard Kleihorst, RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications, Journal of Embedded Computing , Volume 2 Issue 2, IOS Press, April 2006
Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, An interprocedural code optimization technique for network processors using hardware multi-threading support., DATE 2006: 919-924
Hans Peter Löb, Rainer Buchty, Wolfgang Karl, A network agent for diagnosis and analysis of real-time Ethernet networks., CASES 2006: 65-73
Hans Vandierendonck, Koen De Bosschere, On the Impact of OS and Linker Effects on Level-2 Cache Performance., MASCOTS 2006: 87-95
Hans Vandierendonck, Pedro Trancoso, Building and Validating a Reduced TPC-H Benchmark., MASCOTS 2006: 383-392
Hans Vandierendonck, Philippe Manet, Jean-Didier Legat, Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses., DATE 2006: 357-362
Haris Lekatsas, Jorg Henkel, Venkata Jakkula, Srimat Chakradhar, Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems, VLSID '06: Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design, IEEE Computer Society, January 2006
Hassan Ghasemzadeh, Sepideh Sepideh Mazrouee, Mohammad Reza Kakoee, Modified Pseudo LRU Replacement Algorithm., ECBS 2006: 368-376
Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout, Pattern-driven prefetching for multimedia applications on embedded processors., Journal of Systems Architecture 52(4): 199-212 (2006)
Hector Pettenghi, Maria Jose Avedillo, Jose Maria Quintana, Single Phase Clock Scheme for Mobile Based Circuits, XXI Conf. on Design of Circuits and Integrated Syst.
Hector Pettenghi, Maria Jose Avedillo, Jose Maria Quintana, Single phase clock scheme for mobile logic gates, Electronic Letters vol. 42 no. 24, pp. 1382-1383
Heikki Kariniemi, Jari Nurmi, On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips., FPL 2006: 1-6
Heikki Kariniemi, Jari Nurmi, Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip., DDECS 2006: 186-191
Heiner Giefers, Achim Rettberg, Energy aware multiple clock domain scheduling for a bit-serial self-timed architecture., SBCCI 2006: 113-118
Henan Zhao, Rizos Sakellariou, Advance Reservation Policies for Workflows., JSSPP 2006: 47-67
Henan Zhao, Rizos Sakellariou, Scheduling multiple DAGs onto heterogeneous systems., IPDPS 2006
Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert, Toward architecture-based test-vector generation for timing verification of fast parallel multipliers., IEEE Trans. VLSI Syst. 14(4): 370-379 (2006)
Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Själander, D. Johansson, M. Scholin, Multiplier reduction tree with logarithmic logic depth and regular connectivity., ISCAS 2006
Henrique João L. Domingos, Anne-Marie Kermarrec, Pascal Felber, Márk Jelasity, Topic 15: Peer-to-Peer and Web Computing., Euro-Par 2006: 993
Herbert Leitold, Evangelos P. Markatos, Communications and Multimedia Security 10th IFIP TC-6 TC-11 International Conference CMS 2006 Heraklion Crete Greece October 19-21 2006 Proceedings, Springer 2006
Hong Linh Truong, Peter Brunner, Thomas Fahringer, Francesco Nerieri, Robert Samborski, Bartosz Balis, Marian Bubak, Kuba Rozkwitalski, K-WfGrid Distributed Monitoring and Performance Analysis Services for Workflows in the Grid., e-Science 2006: 15
Hong Linh Truong, Robert Samborski, Thomas Fahringer, Towards a Framework for Monitoring and Analyzing QoS Metrics of Grid Services., e-Science 2006: 65
Hongyu Yang, Feng Xie, Yi Lu, Clustering and Classification Based Anomaly Detection., FSKD 2006: 1082-1091
Hongyu Yang, Feng Xie, Yi Lu, Network Anomalous Attack Detection Based on Clustering and Classifier., CIS 2006: 672-682
Hritam Dutta, Frank Hannig, Jürgen Teich, Hierarchical Partitioning for Piecewise Linear Algorithms., PARELEC 2006: 153-160
Hritam Dutta, Frank Hannig, Jürgen Teich, Controller Synthesis for Mapping Partitioned Programs on Array Architectures., ARCS 2006: 176-190
Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger, A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing., ASAP 2006: 331-340
I. Artundo, D. Manjarres, Wim Heirman, Christof Debaes, Joni Dambre, Jan M. Van Campenhout, Hugo Thienpont, Reconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior., ISPA Workshops 2006: 311-321
Ian Bell, Nabil Hasasneh, Chris R. Jesshope, Supporting Microthread Scheduling and Synchronisation in CMPs., International Journal of Parallel Programming 34(4): 343-381 (2006)
Ian Watson, Jens Trotzky, Self-organising Hierarchical Retrieval in a Case-Agent System., ECCBR 2006: 62-75
Idit Keidar, Assaf Schuster, Want scalable computing?: speculate!, SIGACT News 37(3): 59-66 (2006)
Ilya Obridko, Ran Ginosar, Minimal Energy Asynchronous Dynamic Adders., IEEE Trans. VLSI Syst. 14(9): 1043-1047 (2006)
Ingebjørg Theiss, Olav Lysne, FRoots: A Fault Tolerant and Topology-Flexible Routing Technique., IEEE Trans. Parallel Distrib. Syst. 17(10): 1136-1150 (2006)
Ioannis Sourdis, Vassilis Dimopoulos, Dionisios N. Pnevmatikatos, Stamatis Vassiliadis, Packet pre-filtering for network intrusion detection., ANCS 2006: 183-192
Iouliia Skliarova, Intelligent Systems Engineering with Reconfigurable Computing., IFIP PPAI 2006: 161-170
Isabelle Linden, Jean-Marie Jacquet, Koen De Bosschere, Antonio Brogi, On the expressiveness of timed coordination models., Sci. Comput. Program. 61(2): 152-187 (2006)
Ivan Rodero, Francesc Guim, Julita Corbalán, Jesús Labarta, How the JSDL can Exploit the Parallelism?, CCGRID 2006: 275-282
Ivona Brandic, Sabri Pllana, Siegfried Benkner, An approach for the high-level specification of QoS-aware grid workflows considering location affinity., Scientific Programming 14(3-4): 231-250 (2006)
Ivona Brandic, Sabri Pllana, Siegfried Benkner, Amadeus: A Holistic Service-oriented Environment for Grid Workflows., GCC Workshops 2006: 259-266
Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson, MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis., Conf. Computing Frontiers 2006: 21-28
Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev, A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration., DAC 2006: 125-130
Izchak Sharfman, Assaf Schuster, Daniel Keren, A geometric approach to monitoring threshold functions over distributed data streams., SIGMOD Conference 2006: 301-312
Júlio C. B. de Mattos, Stephan Wong, Luigi Carro, The Molen FemtoJava Engine., ASAP 2006: 19-22
Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas, 06141 Executive Summary -- Dynamically Reconfigurable Architectures., Dynamically Reconfigurable Architectures 2006
Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas, 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures., Dynamically Reconfigurable Architectures 2006
Jürgen Becker, Kurt Brändle, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl, Thorsten Köster, Michael Wenz, Heinz Wörn, Digital On-Demand Computing Organism for Real-Time Systems., ARCS Workshops 2006: 230-245
Jürgen Hofer, Thomas Fahringer, Presenting Scientific Legacy Programs as Grid Services via Program Synthesis., e-Science 2006: 34
Jürgen Hofer, Thomas Fahringer, Specification-based Synthesis of Tailor-made Grid Service Wrappers for Scientific Legacy Codes., GRID 2006: 305-306
Jürgen Teich, Are current ESL tools meeting the requirements of advanced embedded systems?, CODES+ISSS 2006: 166
Jürgen Teich, Shuvra S. Bhattacharyya, Analysis of Dataflow Programs with Interval-limited Data-rates., VLSI Signal Processing 43(2-3): 247-258 (2006)
Jürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner, Topic 18: Embedded Parallel Systems., Euro-Par 2006: 1179
J. Chamorro-Martinez, D. Sanchez, B. Prados-Suarez, E. Galan-Perales, Fuzzy homogeneity measures for path-based colour image segmentation, International Journal of Intelligent Systems Technologies and Applications , Volume 1 Issue 3/4, Inderscience Publishers, June 2006
J. J. Costa, Toni Cortes, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Running OpenMP applications efficiently on an everything-shared SDSM., J. Parallel Distrib. Comput. 66(5): 647-658 (2006)
Jacob A. Bower, Wayne Luk, Oskar Mencer, Michael J. Flynn, Martin Morf, Dynamic clock-frequencies for FPGAs., Microprocessors and Microsystems 30(6): 388-397 (2006)
Jacqueline Chame, Chun Chen, Pedro C. Diniz, Mary W. Hall, Yoon-Ju Lee, Robert F. Lucas, An overview of the ECO project., IPDPS 2006
Jaeheon Jeong, Per Stenström, Michel Dubois, Simple penalty-sensitive replacement policies for caches., Conf. Computing Frontiers 2006: 341-352
JaeWoong Chung, Chi Cao Minh, Austen McDonald, Travis Skare, Hassan Chafi, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun, Tradeoffs in transactional memory virtualization., ASPLOS 2006: 371-381
JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun, The common case transactional behavior of multithreaded programs., HPCA 2006: 266-277
Jairo Balart, Marc González, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Runtime Address Space Computation for SDSM Systems., LCPC 2006: 330-344
Jamel Tayeb, Smaïl Niar, Adapting EPIC Architecture's Register Stack for Virtual Stack Machines., DSD 2006: 204-210
Jan Petzold, Faruk Bagci, Wolfgang Trumler, Theo Ungerer, Hybrid Predictors for Next Location Prediction., UIC 2006: 125-134
Jan Petzold, Faruk Bagci, Wolfgang Trumler, Theo Ungerer, Comparison of Different Methods for Next Location Prediction., Euro-Par 2006: 909-918
Jan-David Mol, Dick H. J. Epema, Henk J. Sips, The Orchard Algorithm: P2P Multicasting without Free-Riding., Peer-to-Peer Computing 2006: 275-282
Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe, Reunion: Complexity-Effective Multicore Redundancy., MICRO 2006: 223-234
Jari Heikkinen, Jarmo Takala, Effects of Program Compression., SAMOS 2006: 259-268
Jari K. Juntunen, Mauri Kuorilehto, Mikko Kohvakka, Ville Kaseva, Marko Hännikäinen, Timo D. Hämäläinen, WSN API: Application Programming Interface for Wireless Sensor Networks., PIMRC 2006: 1-5
Jari Nikara, Jarmo Takala, Jaakko Astola, Discrete cosine and sine transforms - regular algorithms and pipeline architectures., Signal Processing 86(2): 230-249 (2006)
Jarmo Takala, Konsta Punkka, Scalable FFT Processors and Pipelined Butterfly Units., VLSI Signal Processing 43(2-3): 113-123 (2006)
Jarno Vanne, Eero Aho, Timo Hämäläinen, Kimmo Kuusilinna, A High-Performance Sum of Absolute Difference Implementation for Motion Estimation., IEEE Trans. Circuits Syst. Video Techn. 16(7): 876-883 (2006)
Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, Babak Falsafi, Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays., IEEE Micro 26(1): 70-79 (2006)
Javier D. Bruguera, Roberto R. Osorio, A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization, DSD '06: Proceedings of the 9th EUROMICRO Conference on Digital System Design, IEEE Computer Society, August 2006
Javier D. Bruguera, Roberto R. Osorio, A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization., DSD 2006: 407-414
Javier Fernández, Félix García Carballeira, Jesús Carretero, Alejandro Calderón, José Daniel García, Disk Scheduling Proposal for an In-Band Bandwidth Virtualization Schema., PDPTA 2006: 669-675
Javier Garcia-Frias, Felipe Cabarcas, Approaching the Slepian-Wolf boundary using practical channel codes., Signal Processing 86(11): 3096-3101 (2006)
Javier Setoain, Christian Tenllado, Manuel Prieto, David Valencia, Antonio Plaza, Javier Plaza, Parallel Hyperspectral Image Processing on Commodity Graphics Hardware., ICPP Workshops 2006: 465-472
Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero, The impact of traffic aggregation on the memory performance of networking applications, Journal of Embedded Computing , Volume 2 Issue 1, IOS Press, January 2006
Jay L. T. Cornwall, Olav Beckmann, Paul H. J. Kelly, Automatically translating a general purpose C++ image processing library for GPUs., IPDPS 2006
Jehangir Khan, Yassin Elhillali, Smaïl Niar, Atika Rivenq, A Low Speed Digital Correlator Architecture Optimized For Resource Savings., ReCoSoC 2006: 207-213
Jeremy Gibbons, David Lester, Richard S. Bird, Functional Pearl: Enumerating the rationals., J. Funct. Program. 16(3): 281-291 (2006)
Jesús Alastruey, José Luis Briz, Pablo Ibáñez, Víctor Viñals, Software Demand Hardware Supply., IEEE Micro 26(4): 72-82 (2006)
Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero, Speculative early register release., Conf. Computing Frontiers 2006: 291-302
Jesús Delicado, Luis Orozco-Barbosa, Francisco Delicado, Pedro Cuenca, A QoS-aware protocol architecture for WiMAX., CCECE 2006: 1779-1782
Jesús Labarta, Bernd Mohr, Allan Snavely, Jeffrey S. Vetter, Topic 2: Performance Prediction and Evaluation., Euro-Par 2006: 63
Jesus Alastruey, Jose Luis Briz, Pablo Ibanez, Victor Cinals, Software Demand, Hardware Supply, IEEE Micro , Volume 26 Issue 4, IEEE Computer Society Press, July 2006
Jeyarajan Thiyagalingam, Olav Beckmann, Paul H. J. Kelly, Is Morton layout competitive for large two-dimensional arrays yet?, Concurrency and Computation: Practice and Experience 18(11): 1509-1539 (2006)
Jia Guo, Ganesh Bikshandi, Daniel Hoeflinger, Gheorghe Almási, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Christoph von Praun, Hierarchically tiled arrays for parallelism and locality., IPDPS 2006
Jiang Xu, Wayne Wolf, Joerg Henkel, Srimat Chakradhar, A design methodology for application-specific networks-on-chip, Transactions on Embedded Computing Systems (TECS) , Volume 5 Issue 2, ACM, May 2006
Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting., VLSI Signal Processing 43(2-3): 235-246 (2006)
Jie Tao, Siegfried Schloissnig, Wolfgang Karl, Analysis of the Spatial and Temporal Locality in Data Accesses., International Conference on Computational Science (2) 2006: 502-509
Jie Tao, Wolfgang Karl, Detailed cache simulation for detecting bottleneck miss reason and optimization potentialities., VALUETOOLS 2006: 62
Jie Tao, Wolfgang Karl, Supporting Cache Locality Optimization with a Toolset., Euro-Par 2006: 25-34
Jie Tao, Wolfgang Karl, Performance Evaluation of Adaptive Caching Schemes., ARCS Workshops 2006: 351-364
Jinfeng Huang, Jeroen Voeten, Henk Corporaal, Correctness-preserving synthesis for real-time control software., QSIC 2006: 65-73
Jinfeng Huang, Marc Geilen, Jeroen Voeten, Henk Corporaal, Branching-Time Property Preservation Between Real-Time Systems., ATVA 2006: 260-275
Jingling Xue, Jens Knoop, A Fresh Look at PRE as a Maximum Flow Problem., CC 2006: 139-154
Joachim Falk, Christian Haubelt, Jürgen Teich, Efficient Representation and Simulation of Model-Based Designs., FDL 2006: 129-135
Joaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata, Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA., FPL 2006: 1-4
Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides, Emilio L. Zapata, SAD computation based on online arithmetic for motion estimation., Microprocessors and Microsystems 30(5): 250-258 (2006)
Johan Jeuring, Alexey Rodriguez, Gideon Smeding, Generating generic functions., ICFP-WGP 2006: 23-32
Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma, Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography., DATE 2006: 218-223
John Cavazos, Christophe Dubach, Felix V. Agakov, Edwin V. Bonilla, Michael F. P. O'Boyle, Grigori Fursin, Olivier Temam, Automatic performance model construction for the fast software exploration of new hardware designs., CASES 2006: 24-34
John Cavazos, J. Eliot B. Moss, Michael F. P. O'Boyle, Hybrid Optimizations: Which Optimization Algorithm to Use?., CC 2006: 124-138
John Cavazos, Michael F. P. O'Boyle, Method-specific dynamic compilation using logistic regression., OOPSLA 2006: 229-240
Jonas Maebe, Dries Buytaert, Lieven Eeckhout, Koen De Bosschere, Javana: a system for building customized Java program analysis tools., OOPSLA 2006: 153-168
Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung, Fast word-level power models for synthesis of FPGA-based arithmetic., ISCAS 2006
Jonathan Barre, Cédric Landet, Christine Rochange, Pascal Sainrat, Modeling Instruction-Level Parallelism for WCET Evaluation., RTCSA 2006: 61-67
Jorge García-Vidal, Maribel March, Llorenç Cerdà, Jesús Corbal, Mateo Valero, A DRAM/SRAM Memory Scheme for Fast Packet Buffers., IEEE Trans. Computers 55(5): 588-602 (2006)
José A. Gregorio, Bettina Schnor, Angelos Bilas, Olav Lysne, Topic 13: Routing and Communication in Interconnection Networks., Euro-Par 2006: 851
José Carlos Mouriño, María J. Martín, Patricia González, Ramon Doallo, High Performance Air Quality Simulation in the European CrossGrid Project., Computers and Artificial Intelligence 25(4): (2006)
José Carlos Mouriño, María J. Martín, Patricia González, Ramon Doallo, Dynamic Load-Balancing for the STEM-II Air Quality Model., ICCSA (1) 2006: 701-710
José Daniel García, Jesús Carretero, Félix García Carballeira, Javier Fernández, David E. Singh, Alejandro Calderón, Reliable Partial Replication of Contents in Web Clusters: Getting Storage without losing Reliability., JCP 1(7): 81-88 (2006)
José Daniel García, Jesús Carretero, Félix García, Javier Fernández, Alejandro Calderón, David E. Singh, A Quantitative Justification to Partial Replication of Web Contents., ICCSA (4) 2006: 1136-1145
José Daniel García, Jesús Carretero, Javier Fernández, Félix García, David E. Singh, Alejandro Calderón, On the Reliability of Web Clusters with Partial Replication of Contents., ARES 2006: 617-624
José Ignacio Aliaga, José M. Badía, Sergio Barrachina, Maribel Castillo, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Francisco Almeida, Vicente Bl, Parallelization of GSL: The Web Service Interface., PDP 2006: 301-307
José Luis Imaña, Juan Manuel Sánchez, Francisco Tirado, Bit-Parallel Finite Field Multipliers for Irreducible Trinomials., IEEE Trans. Computers 55(5): 520-533 (2006)
José Luis Imaña, Román Hermida, Francisco Tirado, Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials., IEEE Trans. VLSI Syst. 14(12): 1388-1393 (2006)
José Luis Martínez, Pedro Cuenca, Francisco Delicado, Luis Orozco-Barbosa, On the Capabilities of Quality Measures in Video Compresion Standards., CCECE 2006: 527-532
José M. Badía, Peter Benner, Rafael Mayo, Enrique S. Quintana-Ortí, Parallel Solution of Large-Scale and Sparse Generalized Algebraic Riccati Equations., Euro-Par 2006: 710-719
José Manuel Claver, Manel Canseco, P. Agustí, G. León, A Hardware NIC Scheduler to Guarantee QoS on High Performance Servers., ISPA 2006: 86-97
José Miguel Montañana, Jose Flich, Antonio Robles, José Duato, Reachability-Based Fault-Tolerant Routing., ICPADS (1) 2006: 515-524
José Villalón, Pedro Cuenca, Luis Orozco-Barbosa, A Novel IEEE 802.11e-Based QoS Protocol for Voice Communications over WLANs., WWIC 2006: 224-235
José Villalón, Pedro Cuenca, Luis Orozco-Barbosa, B-EDCA: A New IEEE 802.11e-Based QoS Protocol for Multimedia Wireless Communications., Networking 2006: 148-159
José Villalón, Yongho Seok, Thierry Turletti, Pedro Cuenca, Luis Orozco-Barbosa, ARSM: Auto Rate Selection Multicast Mechanism for Multi-rate Wireless LANs., PWC 2006: 239-250
Jose Gonzalez-Mora, Nicolas Guil, Emilio L. Zapata, Tracking of Linear Appearance Models Using Second Order Minimization., ACIVS 2006: 1002-1013
Jose L. Ayala, David Atienza, Praveen Raghavan, Marisa Lopez-Vallejo, Francky Catthoor, Compilation for Delay Impact Minimization in VLIW Embedded Systems, IWIA '06: Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IEEE Computer Society, January 2006
Jose Maria Quintana, Maria Jose Avedillo, Hector Pettenghi, Implementación de lógica umbral y multiumbral con RTDs, 12th IBERCHIP, no. 12
Jose Maria Quintana, Maria Jose Avedillo, Hector Pettenghi, Self-Latching Operation Limits for MOBILE Circuits, Proc. Int. Symp. on Circuits and Syst., pp. 4579-4582
Josep Aguilar-Saborit, Pedro Trancoso, Victor Muntés-Mulero, Josep-Lluis Larriba-Pey, Dynamic count filters., SIGMOD Record 35(1): 26-32 (2006)
Josep Domènech, Ana Pont, Julio Sahuquillo, José A. Gil, Cost-Benefit Analysis of Web Prefetching Algorithms from the User's Point of View., Networking 2006: 1113-1118
Josep Domènech, José A. Gil, Julio Sahuquillo, Ana Pont, Web prefetching performance metrics: A survey., Perform. Eval. 63(9-10): 988-1004 (2006)
Josep Domènech, Julio Sahuquillo, Ana Pont, José A. Gil, Design keys to adapt web prefetching algorithms to environment conditions., COMSWARE 2006
Josep Domènech, Julio Sahuquillo, José A. Gil, Ana Pont, The Impact of the Web Prefetching Architecture on the Limits of Reducing User's Perceived Latency., Web Intelligence 2006: 740-744
Josep Jorba, Tomàs Margalef, Emilio Luque, Search of Performance Inefficiencies in Message Passing Applications with KappaPI 2 Tool., PARA 2006: 409-419
Josep L. Lérida, Francesc Solsona, Francesc Giné, Mauricio Hanzich, Porfidio Hernández, Emilio Luque, MetaLoRaS: A Predictable MetaScheduler for Non-dedicated Multiclusters., ISPA 2006: 630-641
Josep M. Pérez, Rosa M. Badia, Jesús Labarta, Including SMP in Grids as Execution Platform and Other Extensions in GRID Superscalar., e-Science 2006: 60
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin, Instruction packing: Toward fast and energy-efficient instruction scheduling., TACO 3(2): 156-181 (2006)
Joshua J. Yi, Hans Vandierendonck, Lieven Eeckhout, David J. Lilja, The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools., ICS 2006: 75-86
Joshua J. Yi, Lieven Eeckhout, David J. Lilja, Brad Calder, Lizy Kurian John, James E. Smith, The Future of Simulation: A Field of Dreams., IEEE Computer 39(11): 22-29 (2006)
Joshua J. Yi, Resit Sendag, Lieven Eeckhout, Ajay Joshi, David J. Lilja, Lizy Kurian John, Evaluating Benchmark Subsetting Approaches., IISWC 2006: 93-104
Juan C. Moure, Domingo Benitez, Dolores Rexachs, Emilio Luque, Wide and efficient trace prediction using the local trace predictor., ICS 2006: 55-65
Juan Carlos Pichel, David E. Singh, Francisco F. Rivera, Image segmentation based on merging of sub-optimal segmentations., Pattern Recognition Letters 27(10): 1105-1116 (2006)
Juan L. Aragón, José M. González, Antonio González, Control Speculation for Energy-Efficient Next-Generation Superscalar Processors., IEEE Trans. Computers 55(3): 281-291 (2006)
Juanjo Noguera, Rosa M. Badia, System-level power-performance tradeoffs for reconfigurable computing., IEEE Trans. VLSI Syst. 14(7): 730-739 (2006)
Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen, Design Implementation and Experiments on Outdoor Deployment of Wireless Sensor Network for Environmental Monitoring., SAMOS 2006: 109-121
Julián Ramos Cózar, Nicolás Guil Mata, J. M. González-Linares, Emilio L. Zapata, Video Cataloging Based on Robust Logotype Detection., ICIP 2006: 3217-3220
Juraj Polakovic, Ali Erdem Özcan, Jean-Bernard Stefani, Building Reconfigurable Component-Based OS with THINK., EUROMICRO-SEAA 2006: 178-185
Jyrki Joutsensalo, Ari Viinikainen, Mika Wikström, Timo Hämäläinen, Bandwidth allocation and pricing in multimode network., AINA (1) 2006: 573-578
K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, A novel methodology for designing high-performance and low-energy FPGA routing architecture., FPGA 2006: 224
Karine Heydemann, François Bodin, Peter M. W. Knijnenburg, Laurent Morin, UFS: a global trade-off strategy for loop unrolling for VLIW architectures., Concurrency and Computation: Practice and Experience 18(11): 1413-1434 (2006)
Kenneth Hoste, Aashish Phansalkar, Lieven Eeckhout, Andy Georges, Lizy Kurian John, Koen De Bosschere, Performance prediction based on inherent program similarity., PACT 2006: 114-122
Kenneth Hoste, Lieven Eeckhout, Comparing Benchmarks Using Key Microarchitecture-Independent Characteristics., IISWC 2006: 83-92
Kimish Patel, Enrico Macii, Massimo Poncino, Luca Benini, Energy-Efficient Value Based Selective Refresh for Embedded DRAMS., J. Low Power Electronics 2(1): 70-79 (2006)
Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino, STV-Cache: a leakage energy-efficient architecture for data caches., ACM Great Lakes Symposium on VLSI 2006: 404-409
Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino, Reducing Conflict Misses by Application-Specific Reconfigurable Indexing., IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2626-2637 (2006)
Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Memory Access Micro-Profiling for ASIP Design., DELTA 2006: 255-262
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia, Design and implementation of a modular and portable IEEE 754 compliant floating-point unit., DATE Designers' Forum 2006: 221-226
Klaus Danne, Marco Platzner, An EDF schedulability test for periodic tasks on reconfigurable hardware devices., LCTES 2006: 93-102
Klaus Danne, Marco Platzner, Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware., IPDPS 2006
Klaus Danne, Roland Muhlenbernd, Marco Platzner, Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions., FPL 2006: 1-6
Koen Bertels, João M. P. Cardoso, Stamatis Vassiliadis, Reconfigurable Computing: Architectures and Applications Second International Workshop ARC 2006 Delft The Netherlands March 1-3 2006 Revised Selected Papers, Springer 2006
Konstantinos Xinidis, Ioannis Charitakis, Spyros Antonatos, Kostas G. Anagnostakis, Evangelos P. Markatos, An Active Splitter Architecture for Intrusion Detection and Prevention., IEEE Trans. Dependable Sec. Comput. 3(1): 31-44 (2006)
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope, Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors., Comput. J. 49(2): 211-233 (2006)
Kostas Siozios, Dimitrios Soudris, Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures., FPL 2006: 1-4
Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis, A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications., ISCAS 2006
Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis, Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique., VLSI-SoC 2006: 204-209
Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis, Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources., PATMOS 2006: 403-414
Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis, Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications., IPDPS 2006
Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Koen De Bosschere, Wilfried Philips, Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture., ARC 2006: 52-58
Kris Venstermans, Lieven Eeckhout, Koen De Bosschere, 64-bit versus 32-bit Virtual Machines for Java., Softw. Pract. Exper. 36(1): 1-26 (2006)
Kris Venstermans, Lieven Eeckhout, Koen De Bosschere, Space-Efficient 64-bit Java Objects through Selective Typed Virtual Addressing., CGO 2006: 76-86
Krisztián Flautner, Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systems., CODES+ISSS 2006: 265
Kyriakos Stavrou, Pedro Trancoso, Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems., DSD 2006: 123-126
Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou, Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor., Asia-Pacific Computer Systems Architecture Conference 2006: 244-259
L. M. Sánchez García, Florin Isaila, Félix García Carballeira, Jesús Carretero Pérez, Rolf Rabenseifner, Panagiotis A. Adamidis, A New I/O Architecture for Improving the Performance in Large Scale Clusters., ICCSA (5) 2006: 108-117
Laila Sakkila, P. Deloof, Yassin Elhillali, Atika Rivenq, Smaïl Niar, A Real Time Signal Processing for an Anticollision Road Radar System., VTC Fall 2006: 1-5
Lari Kannisto, Ari Viinikainen, Jyrki Joutsensalo, Timo Hämäläinen, Adaptive Algorithm for Revenue Maximization in WFQ Scheduler., AINA (1) 2006: 339-346
Lars Wehmeyer, Peter Marwedel, Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation, Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation, Springer-Verlag New York, Inc., August 2006
Laura Pozzi, Kubilay Atasu, Paolo Ienne, Exact and approximate algorithms for the extension of embedded processor instruction sets., IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1209-1229 (2006)
Laurence Tianruo Yang, Hai Jin, Jianhua Ma, Theo Ungerer, Autonomic and Trusted Computing Third International Conference ATC 2006 Wuhan China September 3-6 2006 Proceedings, Springer 2006
Leandro Souza, Ana Ripoll, Xiaoyuan Yang, Emilio Luque, Fernando Cores, On the Relevance of Network Topologies in Distributed Video-on-Demand Servers., PDP 2006: 396-404
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann, FPGAs GPUs and the PS2 - A Single Programming Methodology., FCCM 2006: 313-314
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann, Oliver Pell, Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description., FPL 2006: 1-6
Lei Gao, Yongsheng Ding, Hao Ying, Economics-inspired decentralized control approach for adaptive grid services and applications., Int. J. Intell. Syst. 21(12): 1269-1288 (2006)
Lieven Eeckhout, Koen De Bosschere, Yet shorter warmup by combining no-state-loss and MRRL for sampled LRU cache simulation., Journal of Systems and Software 79(5): 645-652 (2006)
Liliana Cucu, Joël Goossens, Feasibility Intervals for Fixed-Priority Real-Time Scheduling on Uniform Multiprocessors., ETFA 2006: 397-404
Lily R. Liang, Shiyong Lu, Yi Lu, Puneet Dhawan, Deepak Kumar, CM-test: An Innovative Divergence Measurement and Its Application in Diabetes Gene Expression Data Analysis., GrC 2006: 262-268
Liping Xue, Ozcan Ozturk, Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu, Dynamic partitioning of processing and memory resources in embedded MPSoC architectures., DATE 2006: 690-695
Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis, A reconfigurable hardware based embedded scheduler for buffered crossbar switches., FPGA 2006: 143-149
Lotfi Mhamdi, Mounir Hamdi, Christopher Kachris, Stephan Wong, Stamatis Vassiliadis, High-performance switching based on buffered crossbar fabrics., Computer Networks 50(13): 2271-2285 (2006)
Luca Benini, Application specific NoC design., DATE 2006: 491-495
Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano, Allocation Scheduling and Voltage Scaling on Energy Aware MPSoCs., CPAIOR 2006: 44-58
Luca Benini, Elisabetta Farella, Carlotta Guiducci, Wireless sensor networks: Enabling technology for ambient intelligence., Microelectronics Journal 37(12): 1639-1649 (2006)
Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, ASIP design and synthesis for non linear filtering in image processing., DATE Designers' Forum 2006: 233-238
Luca Fanucci, Pasquale Ciao, Giulio Colavolpe, VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes., IEICE Transactions 89-A(7): 1976-1986 (2006)
Ludo Van Put, Bjorn De Sutter, Matias Madou, Bruno De Bus, Dominique Chanet, Kristof Smits, Koen De Bosschere, LANCET: a nifty code editing tool, PASTE '05: Proceedings of the 6th ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering, ACM, January 2006
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Victor Viñals, Data prefetching in a cache hierarchy with high bandwidth and capacity, MEDEA '06: Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures, ACM, September 2006
Luis Miguel Sánchez, Florin Isaila, Alejandro Calderón, David E. Singh, José Daniel García, Improving the Performance of Cluster Applications through I/O Proxy Architecture., CLUSTER 2006
Luk Van Ertvelde, Filip Hellebaut, Lieven Eeckhout, Koen De Bosschere, NSL-BLRL: Efficient CacheWarmup for Sampled Processor Simulation., Annual Simulation Symposium 2006: 168-177
M. Aldea, Guillem Bernat, Ian Broster, Alan Burns, Radu Dobrin, José M. Drake, Gerhard Fohler, Paolo Gai, Michael González Harbour, Giacomo Guidi, J. Javier Gutiérrez, Tomas Lennv, FSF: A Real-Time Scheduling Architecture Framework., IEEE Real Time Technology and Applications Symposium 2006: 113-124
M. Anton Ertl, Kevin Casey, David Gregg, Fast and flexible instruction selection with on-demand tree-parsing automata., PLDI 2006: 52-60
M. Goyeneche, Jesús E. Villadangos, José Javier Astrain, Manuel Prieto, Alberto Córdoba, A distributed data gathering algorithm for wireless sensor networks with uniform architecture., PE-WASUN 2006: 162-166
M.E.Castro, Roberto R. Osorio, Javier D. Bruguera, Optimizing CABAC for VLIW architectures, Proc. XXI Conference on Design of Circuits and Integrated Systems (DCIS2006)
Manish Verma, Lars Wehmeyer, Peter Marwedel, Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems., IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2035-2051 (2006)
Manish Verma, Lars Wehmeyer, Robert Pyka, Peter Marwedel, Luca Benini, Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations ., SAMOS 2006: 279-288
Manish Verma, Peter Marwedel, Overlay techniques for scratchpad memories in low power embedded processors., IEEE Trans. VLSI Syst. 14(8): 802-815 (2006)
Manolis Marazakis, Konstantinos Xinidis, Vassilis Papaefstathiou, Angelos Bilas, Efficient remote block-level I/O over an RDMA-capable NIC., ICS 2006: 97-106
Manolis Marazakis, Vassilis Papaefstathiou, Giorgos Kalokairinos, Angelos Bilas, Experiences from Debugging a PCIX-based RDMA-capable NIC., CLUSTER 2006
Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren, Retargetable code optimization with SIMD instructions., CODES+ISSS 2006: 148-153
Manuel Prieto, Jesús E. Villadangos, Federico Fariña, Alberto Córdoba, An O(n) Distributed Deadlock Resolution Algorithm., PDP 2006: 48-55
María Blanca Ibáñez, Félix García, Jesús Carretero, A Profiling Approach for the Management of Writing in Irregular Applications., ISPA Workshops 2006: 251-259
María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida, Bitwise scheduling to balance the computational cost of behavioral specifications., IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 31-46 (2006)
María Cruz Valiente, Gonzalo Génova, Jesús Carretero, UML 2.0 Notation for Modeling Real Time Task Scheduling., Journal of Object Technology 5(4): 91-105 (2006)
María Engracia Gómez, Nils Agne Nordbotten, Jose Flich, Pedro López, Antonio Robles, José Duato, Tor Skeie, Olav Lysne, A Routing Methodology for Achieving Fault Tolerance in Direct Networks., IEEE Trans. Computers 55(4): 400-415 (2006)
María Engracia Gómez, Pedro López, José Duato, FIR: An efficient routing strategy for tori and meshes., J. Parallel Distrib. Comput. 66(7): 907-921 (2006)
María S. Pérez, Jesús Carretero, Félix García Carballeira, José Manuel Peña, Víctor Robles, MAPFS: A flexible multiagent parallel file system for clusters., Future Generation Comp. Syst. 22(5): 620-632 (2006)
Marc Duranton, The Challenges for High Performance Embedded Systems., DSD 2006: 3-7
Marcel D. van de Burgwal, Gerard J. M. Smit, Gerard K. Rauwerda, Paul M. Heysters, Hydra: An Energy-efficient and Reconfigurable Network Interface., ERSA 2006: 171-177
Marco Aldinucci, Marco Danelutto, Marco Vanneschi, Autonomic QoS in ASSIST Grid-Aware Components., PDP 2006: 221-230
Marco D. Santambrogio, Donatella Sciuto, Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign., FPL 2006: 1-2
Marco Danelutto, Marco Aldinucci, Algorithmic skeletons meeting grids., Parallel Computing 32(7-8): 449-462 (2006)
Marco Giorgetta, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini, A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures., VLSI-SoC 2006: 24-29
Marek Wieczorek, Mumtaz Siddiqui, Alex Villazón, Radu Prodan, Thomas Fahringer, Applying Advance Reservation to Increase Predictability of Workflow Execution on the Grid., e-Science 2006: 82
Marek Wieczorek, Radu Prodan, Thomas Fahringer, Dynamic Programming Based Approach for Bi-criteria Workflow Scheduling on the Grid., HPDC 2006: 381-382
Margarita Amor, Montserrat Bóo, Emilio J. Padrón, Dirk Bartz, Hardware Oriented Algorithms for Rendering Order-Independent Transparency., Comput. J. 49(2): 201-210 (2006)
Maria Jose Avedillo, Jose Maria Quintana, Hector Pettenghi, Increased Logic Functionality of Clocked Series-Connected RTDs, IEEE Trans. on Nanotechnology, vol. 5, no. 5, pp. 606- 611
Maria Jose Avedillo, Jose Maria Quintana, Hector Pettenghi, Self-Latching Operation of MOBILE Circuits using Series-Connection of RTDs and Transistors, EEE Trans. on Circuits and Systems II, vol. 53, no. 5, pp. 334-338
Marina Alonso, Salvador Coll, Juan Miguel Martínez, Vicente Santonja, Pedro López, José Duato, Dynamic power saving in fat-tree interconnection networks using on/off links., IPDPS 2006
Marius Mikalsen, Jacqueline Floch, Nearchos Paspallis, George A. Papadopoulos, Pedro Antonio Ruiz, Putting Context in Context: The Role and Design of Context Management in a Mobility and Adaptation Enabling Middleware, MDM '06: Proceedings of the 7th International Conference on Mobile Data Management (MDM'06) - Volume 00 , Volume 00, IEEE Computer Society, May 2006
Marius Mikalsen, Nearchos Paspallis, Jacqueline Floch, Erlend Stav, George A. Papadopoulos, Akis Chimaris, Distributed context management in a mobility and adaptation enabling middleware (MADAM), SAC '06: Proceedings of the 2006 ACM symposium on Applied computing, ACM, April 2006
Mark Silberstein, Dan Geiger, Assaf Schuster, A Distributed System for Genetic Linkage Analysis., GCCB 2006: 110-123
Mark Silberstein, Dan Geiger, Assaf Schuster, Miron Livny, Scheduling Mixed Workloads in Multi-grids: The Grid Execution Hierarchy., HPDC 2006: 291-302
Mark Silberstein, Gabriel Kliot, Artyom Sharov, Assaf Schuster, Miron Livny, Materializing Highly Available Grids., HPDC 2006: 321-323
Mark Thompson, Andy D. Pimentel, Simon Polstra, Cagkan Erbas, A Mixed-level Co-simulation Method for System-level Design Space Exploration., ESTImedia 2006: 27-32
Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli, A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control., CODES+ISSS 2006: 130-135
Martin Brain, Tom Crick, Marina De Vos, John Fitch, TOAST: Applying Answer Set Programming to Superoptimisation., ICLP 2006: 270-284
Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Symbolic Archive Representation for a Fast Nondominance Test., EMO 2006: 111-125
Martin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor, Systematic Preprocessing of Data Dependent Constructs for Embedded Systems., J. Low Power Electronics 2(1): 9-1 (2006)
Martin Streubühr, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf, Task-accurate performance modeling in SystemC for real-time multi-processor architectures., DATE 2006: 480-481
Martin Thuresson, Per Stenström, Scalable Value-Cache Based Compression Schemes for Multiprocessors., SBAC-PAD 2006: 117-124
Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Francesco Poletti, Michela Milano, Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip., DATE 2006: 3-8
Mary Jane Irwin, Koen De Bosschere, Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages Compilers and Tools for Embedded Systems (LCTES'06) Ottawa Ontario Canada June 14-16 2006, ACM 2006
Massimo Rovini, Francesco Rossi, Pasquale Ciao, Nicola L'Insalat, Luca Fanucci, Layered Decoding of Non-Layered LDPC Codes., DSD 2006: 537-544
Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich, A Flexible Reconfiguration Manager for the Erlangen Slot Machine., ARCS Workshops 2006: 183-194
Mathias Pacher, Alexander von Renteln, Uwe Brinkschulte, Towards an Organic Middleware for Real-Time Applications., ISORC 2006: 400-407
Matias Madou, Bertrand Anckaert, Bruno De Bus, Koen De Bosschere, Jan Cappaert, Bart Preneel, On the Effectiveness of Source Code Transformations for Binary Obfuscation., Software Engineering Research and Practice 2006: 527-533
Matias Madou, Ludo Van Put, Koen De Bosschere, LOCO: an interactive code (De)obfuscation tool., PEPM 2006: 140-144
Matias Madou, Ludo Van Put, Koen De Bosschere, Understanding Obfuscated Code., ICPC 2006: 268-274
Mats Brorsson, Mikael Collin, Adaptive and flexible dictionary code compression for embedded applications, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Mats Brorsson, Mikael Collin, Adaptive and flexible dictionary code compression for embedded applications., CASES 2006: 113-124
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, An efficient synchronization technique for multiprocessor systems on-chip, MEDEA '05: Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture, ACM, March 2006
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, Efficient Synchronization for Embedded On-Chip Multiprocessors., IEEE Trans. VLSI Syst. 14(10): 1049-1062 (2006)
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors., ICSAMOS 2006: 144-151
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, Power/performance hardware optimization for synchronization intensive applications in MPSoCs., DATE 2006: 606-611
Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow., VLSI-SoC 2006: 74-79
Matthew Curtis-Maury, Dimitrios S. Nikolopoulos, Christos D. Antonopoulos, PACMAN: A PerformAnce Counters MANager for Intel Hyperthreaded Processors., QEST 2006: 141-144
Matthew Curtis-Maury, James Dzierwa, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Online strategies for high-performance power-aware thread execution on emerging multiprocessors., IPDPS 2006
Matthew Curtis-Maury, James Dzierwa, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Online power-performance adaptation of multithreaded programs using hardware event-based prediction., ICS 2006: 157-166
Mauricio Alvarez, Ricardo Henao, Probabilistic Kernel Principal Component Analysis Through Time., ICONIP (1) 2006: 747-754
Mauricio Hanzich, Josep L. Lérida, Matías Torchinsky, Francesc Giné, Porfidio Hernández, Emilio Luque, Using On-the-Fly Simulation for Estimating the Turnaround Time on Non-dedicated Clusters., Euro-Par 2006: 177-187
Mauricio Hanzich, Porfidio Hernández, Emilio Luque, Francesc Giné, Francesc Solsona, Josep L. Lérida, Using Simulation Historical and Hybrid Estimation Systems for Enhacing Job Scheduling on NOWs., CLUSTER 2006
Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania, A methodology for design of application specific deadlock-free routing algorithms for NoC systems., CODES+ISSS 2006: 142-147
Maurizio Palesi, Shashi Kumar, Rickard Holsmark, A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures., SAMOS 2006: 373-384
Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto, Combined software and hardware techniques for the design of reliable IP processors., DFT 2006: 265-273
Md. Mafijul Islam, Per Stenström, Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations., ICSAMOS 2006: 28-34
Melanie R. Rieback, Georgi Gaydadjiev, Bruno Crispo, Rutger F. H. Hofman, Andrew S. Tanenbaum, A Platform for RFID Security and Privacy Administration (Awarded Best Paper!)., LISA 2006: 89-102
Mercedes Marqués, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Specialized Spectral Division Algorithms for Generalized Eigenproblems Via the Inverse-Free Iteration., PARA 2006: 157-166
Michael Bender, Dror G. Feitelson, Allan Gottlieb, Uwe Schwiegelshohn, Topic 3: Scheduling and Load Balancing., Euro-Par 2006: 155
Michael Factor, Assaf Schuster, Konstantin Shagin, A Platform-Independent Distributed Runtime for Standard Multithreaded Java., International Journal of Parallel Programming 34(2): 113-142 (2006)
Michael Van Biesbrouck, Brad Calder, Lieven Eeckhout, Efficient Sampling Startup for SimPoint., IEEE Micro 26(4): 32-42 (2006)
Michael Van Biesbrouck, Lieven Eeckhout, Brad Calder, Considering all starting points for simultaneous multithreading simulation., ISPASS 2006: 143-153
Michail Flouris, Renaud Lachaize, Angelos Bilas, Using Lightweight Transactions and Snapshots for Fault-Tolerant Services Based on Shared Storage Bricks., CLUSTER 2006
Michail Papamichail, Dimitris Karadimas, Kostas Efstathiou, George Papadopoulos, Linear range extension of a phase-frequency-detector with saturated output., ISCAS 2006
Michalis Polychronakis, Kostas G. Anagnostakis, Evangelos P. Markatos, Network-Level Polymorphic Shellcode Detection Using Emulation., DIMVA 2006: 54-73
Michele Sama, Vincenzo Pacella, Elisabetta Farella, Luca Benini, Bruno Riccò, 3dID: a low-power low-cost hand motion capture device., DATE Designers' Forum 2006: 136-141
Michiel D'Haene, Benjamin Schrauwen, Dirk Stroobandt, Accelerating Event Based Simulation for Multi-synapse Spiking Neural Networks., ICANN (1) 2006: 760-769
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis Paschalis, Anand Raghunathan, Srivaths Ravi, Systematic Software-Based Self-Test for Pipelined Processors, ACM/IEEE Design Automation Conference (DAC 2006), San Fransisco, CA, USA, July 2006
Mikko Kohvakka, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen, Transmission Power Based Path Loss Metering for Wireless Sensor Networks., PIMRC 2006: 1-5
Mikko Kohvakka, Mauri Kuorilehto, Marko Hännikäinen, Timo D. Hämäläinen, Performance analysis of IEEE 802.15.4 and ZigBee for large-scale wireless sensor network applications., PE-WASUN 2006: 48-57
Mikko Kohvakka, Tero Arpinen, Marko Hännikäinen, Timo D. Hämäläinen, High-performance multi-radio WSN platform, REALMAN '06: Proceedings of the 2nd international workshop on Multi-hop ad hoc networks: from theory to reality, ACM, May 2006
Mikko Setälä, Petri Kukkala, Tero Arpinen, Marko Hännikäinen, Timo D. Hämäläinen, Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform., SAMOS 2006: 27-38
Mila Dalla Preda, Matias Madou, Koen De Bosschere, Roberto Giacobazzi, Opaque Predicates Detection by Abstract Interpretation., AMAST 2006: 81-95
Milan Tichý, Andy Nisbet, David Gregg, GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems., FPGA 2006: 236
Milan Tichý, Jan Schier, David Gregg, Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA., ARC 2006: 311-316
Miljan Vuletic, Laura Pozzi, Paolo Ienne, Virtual memory window for application-specific reconfigurable coprocessors., IEEE Trans. VLSI Syst. 14(8): 910-915 (2006)
Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis, A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck., IEEE Trans. VLSI Syst. 14(3): 279-291 (2006)
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson, Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration., ISQED 2006: 557-563
Miquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero, A decoupled KILO-instruction processor., HPCA 2006: 53-64
Mirko Loghi, Massimo Poncino, Luca Benini, Cache coherence tradeoffs in shared-memory MPSoCs., ACM Trans. Embedded Comput. Syst. 5(2): 383-407 (2006)
Mirko Loghi, Massimo Poncino, Luca Benini, Synchronization-driven dynamic speed scaling for MPSoCs., ISLPED 2006: 346-349
Mladen Berekovic, Tim Niggemeier, A Scalable Multi-thread Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme., SAMOS 2006: 289-298
Mohammad Abdullah Al Faruque, Gereon Weiss, Joerg Henkel, Bounded arbitration algorithm for QoS-supported on-chip communication, CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, ACM, October 2006
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto, Single-Event Upset Analysis and Protection in High Speed Circuits., European Test Symposium 2006: 29-34
Mojtaba Sabeghi, Mahmoud Naghibzadeh, Performance assessment of a distributed real-time control system utilizing RDM and RDM+ protocols for communication., CoNEXT 2006: 25
Mojtaba Sabeghi, Mahmoud Naghibzadeh, Toktam Taghavi, Scheduling Non-Preemptive Periodic Tasks in Soft Real-Time Systems Using Fuzzy Inference., ISORC 2006: 27-32
Montse Farreras, Toni Cortes, Jesús Labarta, George Almási, Scaling MPI to short-memory MPPs such as BG/L., ICS 2006: 209-218
Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee, Efficient System-on-Chip Energy Management with a Segmented Bloom Filter., ARCS 2006: 283-297
Mumtaz Siddiqui, Alex Villazón, Thomas Fahringer, Grid allocation and reservation - Grid capacity planning with negotiation-based advance reservation for optimized QoS., SC 2006: 103
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, On-Chip Communication in Run-Time Assembled Reconfigurable Systems., ICSAMOS 2006: 168-176
Nabil Hasasneh, Ian Bell, Chris R. Jesshope, Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors., ARCS 2006: 252-267
Nalini Moti Belaramani, Michael Dahlin, Lei Gao, Amol Nayate, Arun Venkataramani, Praveen Yalagandula, Jiandan Zheng, PRACTI Replication., NSDI 2006
Nastaran Baradaran, Pedro C. Diniz, Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures., FPL 2006: 1-6
Nathan Clark, Amir Hormati, Scott A. Mahlke, Sami Yehia, Scalable subgraph mapping for acyclic computation accelerators., CASES 2006: 147-157
Nearchos Paspallis, George A. Papadopoulos, An Approach for Developing Adaptive, Mobile Applications with Separation of Concerns, COMPSAC '06: Proceedings of the 30th Annual International Computer Software and Applications Conference (COMPSAC'06) - Volume 01 , Volume 01, IEEE Computer Society, September 2006
Nektarios Kranitis, Andreas Merentitis, Nikos Laoutaris, George Theodorou, Antonis Paschalis, Dimitris Gizopoulos, Costas Halatsis, Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications, ACM/IEEE Design Automation and Test in Europe Conference (DATE 2006), Munich, Germany, March 2006.
Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko, Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs., FPL 2006: 1-6
Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko, Yield enhancements of design-specific FPGAs., FPGA 2006: 93-100
Nicolas Vasilache, Cédric Bastoul, Albert Cohen, Polyhedral Code Generation in the Real World., CC 2006: 185-201
Nicolas Vasilache, Cédric Bastoul, Albert Cohen, Sylvain Girbal, Violated dependence analysis., ICS 2006: 335-344
Nikolaos Chrysos, Manolis Katevenis, Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics., INFOCOM 2006
Nikolaos Drosinos, Georgios I. Goumas, Nectarios Koziris, Selecting the tile shape to reduce the total communication volume., IPDPS 2006
Nikolaos Drosinos, Nectarios Koziris, The Effect of Process Topology and Load Balancing on Parallel Programming Models for SMP Clusters and Iterative Algorithms., The Journal of Supercomputing 35(1): 65-91 (2006)
Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis, Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors., VLSI Signal Processing 44(1-2): 153-171 (2006)
Nikolas Kroupis, Stylianos Mamagkakis, Dimitrios Soudris, An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems., ESTImedia 2006: 21-26
Noam Palatin, Arie Leizarowitz, Assaf Schuster, Ran Wolff, Mining for misconfigured machines in grid systems., KDD 2006: 687-692
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh, High-level power analysis for multi-core chips., CASES 2006: 389-400
Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod, Dynamic Voltage Scaling Aware Delay Fault Testing., European Test Symposium 2006: 15-20
Norbert Wehn, Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems., ISVLSI 2006: 3
Norbert Wehn, Timo Vogt, Christian Neeb, A Reconfigurable Outer Modem Platform for Future Communications Systems., Dynamically Reconfigurable Architectures 2006
Oana Florescu, Jeroen Voeten, Marcel Verhoef, Henk Corporaal, Reusing Real-Time Systems Design Experience., FDL 2006: 375-381
Oana Florescu, Jinfeng Huang, Jeroen Voeten, Henk Corporaal, Strengthening Property Preservation in Concurrent Real-Time Systems., RTCSA 2006: 106-109
Oana Florescu, Menno de Hoon, Jeroen Voeten, Henk Corporaal, Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems., SAMOS 2006: 206-215
Oguz Ergin, Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors., PATMOS 2006: 477-485
Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose, Early Register Deallocation Mechanisms Using Checkpointed Register Files., IEEE Trans. Computers 55(9): 1153-1166 (2006)
Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González, Exploiting Narrow Values for Soft Error Tolerance., Computer Architecture Letters 5(2): (2006)
Olav Lysne, Tor Skeie, Sven-Arne Reinemo, Ingebjørg Theiss, Layered Routing in Irregular Networks., IEEE Trans. Parallel Distrib. Syst. 17(1): 51-65 (2006)
Oliver Pell, Wayne Luk, Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information., FPL 2006: 1-6
Oliver Pell, Wayne Luk, Generating Parametrised Hardware Libraries from Higher-Order Descriptions., FCCM 2006: 297-298
Oliver Sinnen, Leonel Augusto Sousa, Frode Eika Sandnes, Toward a Realistic Task Scheduling Model., IEEE Trans. Parallel Distrib. Syst. 17(3): 263-275 (2006)
Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero, Branch predictor guided instruction decoding., PACT 2006: 202-211
Olivier Rochecouste, Gilles Pokam, André Seznec, A case for a complexity-effective width-partitioned microarchitecture., TACO 3(3): 295-326 (2006)
Olli Alanen, Timo Hämäläinen, Eero Wallenius, Network and System Performance Management for Next Generation Networks., AINA (1) 2006: 689-692
Orna Grumberg, Tamir Heyman, Assaf Schuster, A work-efficient distributed algorithm for reachability analysis., Formal Methods in System Design 29(2): 157-175 (2006)
Osman S. Unsal, James Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin, Impact of Parameter Variations on Circuits and Microarchitecture., IEEE Micro 26(6): 30-39 (2006)
Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio González, Empowering a helper cluster through data-width aware instruction selection policies., IPDPS 2006
Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser, Safe Design Methodology for an Intelligent Cruise Control System with GPS., VTC Fall 2006: 1-5
Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser, Pierre Boulet, UML2 Profile for Modeling Controlled Data Parallel Applications., FDL 2006: 359-367
Owen Callanan, David Gregg, Andy Nisbet, Mike Peardon, High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD., FPL 2006: 1-6
Ozcan Ozturk, Feng Wang, Mahmut T. Kandemir, Yuan Xie, Optimal topology exploration for application-specific 3D architectures., ASP-DAC 2006: 390-395
Ozcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy, An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors., ISVLSI 2006: 50-58
Ozcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy, Cache miss clustering for banked memory systems., ICCAD 2006: 244-250
Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Multi-compilation: capturing interactions among concurrently-executing applications., Conf. Computing Frontiers 2006: 157-170
Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu, Compiler-Guided data compression for reducing memory consumption of embedded applications., ASP-DAC 2006: 814-819
Ozcan Ozturk, Guilin Chen, Mahmut T. Kandemir, Optimizing code parallelization through a constraint network based approach., DAC 2006: 863-688
Ozcan Ozturk, Mahmut T. Kandemir, Data Replication in Banked DRAMs for Reducing Energy Consumption., ISQED 2006: 551-556
Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu, Shared Scratch-Pad Memory Space Management., ISQED 2006: 576-584
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun, Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors., ICPADS (1) 2006: 383-390
Ozcan Ozturk, Mahmut T. Kandemir, Seung Woo Son, Mustafa Karaköy, Selective code/data migration for reducing communication energy in embedded MpSoC architectures., ACM Great Lakes Symposium on VLSI 2006: 386-391
Ozcan Ozturk, Mahmut T. Kandemir, Suleyman Tosun, An ILP based approach to address code generation for digital signal processors., ACM Great Lakes Symposium on VLSI 2006: 37-42
P. Marwedel, Embedded System Design, Embedded System Design, Springer-Verlag New York, Inc., March 2006
Pablo Garcia Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli, A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework., VLSI-SoC 2006: 140-145
Panagiota Fatourou, Faith Ellen Fich, Eric Ruppert, Time-space tradeoffs for implementations of snapshots., STOC 2006: 169-178
Panagiota Fatourou, Nikolaos D. Kallimanis, Single-scanner multi-writer snapshot implementations are fast!, PODC 2006: 228-237
Panagiotis Kenterlis, Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs, IEEE International On-Line Testing Symposium 2006 (IOLTS 2006), Como, Italy, pp. 235-241, July 2006.
Panos Trimintzios, Michalis Polychronakis, Antonis Papadogiannakis, Michalis Foukarakis, Evangelos P. Markatos, Arne Øslebø, DiMAPI: An Application Programming Interface for Distributed Network Monitoring., NOMS 2006: 382-393
Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen, Riku Soininen, Risto Rautee, Design and implementation of real-time betting system with offline terminals., Electronic Commerce Research and Applications 5(2): 170-188 (2006)
Panu Hämäläinen, Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen, Security in Wireless Sensor Networks: Considerations and Experiments., SAMOS 2006: 167-177
Panu Hämäläinen, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen, Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core., DSD 2006: 577-583
Paolo Ienne, Rainer Leupers, Customizable Embedded Processors: Design Technologies and Applications (Systems on Silicon), CustomizableEmbedded Processors: Design Technologies and Applications (Systems on Silicon), Morgan Kaufmann Publishers Inc., July 2006
Paraskevas Evripidou, George Samaras, Metacomputing with Mobile Agents., International Journal of Parallel Programming 34(5): 429-458 (2006)
Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi, Automatic identification of application-specific functional units with architecturally visible storage., DATE 2006: 212-217
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne, ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors., IEEE Trans. VLSI Syst. 14(7): 754-762 (2006)
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi, Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core., VLSI Design 2006: 651-656
Paul Feautrier, Scalable and Structured Scheduling., International Journal of Parallel Programming 34(5): 459-487 (2006)
Paul M. Heysters, Coarse-Grained Reconfigurable Computing for Power Aware Applications., ERSA 2006: 272-
Paul M. Heysters, The Era of Reconfigurable Computing., ERSA 2006: 257-264
Paula Cecilia Fritzsche, Concepció Roig, Ana Ripoll, Emilio Luque, Aura Hernandez, A Performance Prediction Methodology for Data-dependent Parallel Applications., CLUSTER 2006
Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten, Modeling Cache Sharing on Chip Multiprocessor Architectures., IISWC 2006: 160-171
Pedro C. Diniz, Gokul Govindu, Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit., FPL 2006: 1-4
Pedro Carmona-Saez, Roberto D. Pascual-Marqui, Francisco Tirado, José María Carazo, Alberto D. Pascual-Montano, Biclustering of gene expression data by non-smooth non-negative matrix factorization., BMC Bioinformatics 7: 78 (2006)
Pedro Cuenca, Luis Orozco-Barbosa, Personal Wireless Communications IFIP TC6 11th International Conference PWC 2006 Albacete Spain September 20-22 2006 Proceedings, Springer 2006
Pedro Javier García, Francisco J. Quiles, Jose Flich, José Duato, Ian Johnson, Finbar Naven, Efficient Scalable Congestion Management for Interconnection Networks., IEEE Micro 26(5): 52-66 (2006)
Pedro Javier García, Francisco J. Quiles, Jose Flich, José Duato, Ian Johnson, Finbar Naven, RECN-DD: A Memory-Efficient Congestion Management Technique for Advanced Switching., ICPP 2006: 23-32
Pedro Morillo, Juan M. Orduña, José Duato, A Scalable Synchronization Technique for Distributed Virtual Environments Based on Networked-Server Architectures., ICPP Workshops 2006: 74-81
Pedro Morillo, Juan M. Orduña, Marcos Fernández, Workload Characterization in Multiplayer Online Games., ICCSA (1) 2006: 490-499
Pedro Morillo, W. Moncho, Juan M. Orduña, José Duato, Providing Full Awareness to Distributed Virtual Environments Based on Peer-to-Peer Architectures., Computer Graphics International 2006: 336-347
Pedro Trancoso, Adaptive High-End Microprocessor for Power-Performance Efficiency., DSD 2006: 221-228
Pedro Trancoso, Paraskevas Evripidou, Kyriakos Stavrou, Costas Kyriacou, A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model., International Journal of Parallel Programming 34(3): 213-235 (2006)
Pepijn J. de Langen, Ben H. H. Juurlink, Leakage-aware multiprocessor scheduling for low power., IPDPS 2006
Per Stenström, Chip-multiprocessing and beyond., HPCA 2006: 109
Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala, Software Pipelining Support for Transport Triggered Architecture Processors., SAMOS 2006: 237-247
Peter Benner, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Solving Stable Sylvester Equations via Rational Iterative Schemes., J. Sci. Comput. 28(1): 51-83 (2006)
Peter Brunner, Hong Linh Truong, Thomas Fahringer, Performance Monitoring and Visualization of Grid Scientific Workflows in ASKALON., HPCC 2006: 170-179
Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich, Dynamically Reconfigurable Architectures 02.04. - 07.04.2006, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI) Schloss Dagstuhl Germany 2006
Petra Povalej, Mateja Verlic, Peter Kokol, José L. Sánchez, Jose F. Sigut, Identifying Lymphoma in Microscopy Images with Classificational Cellular Automata., CBMS 2006: 309-314
Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen, Configurable Protocol Engine for Runtime-Configurable Communication Subsystems on Multiprocessor SoC., PIMRC 2006: 1-5
Petros Oikonomakos, Mark Zwolinski, An Integrated High-Level On-Line Test Synthesis Tool., IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2479-2491 (2006)
Petros Oikonomakos, Mark Zwolinski, On the Design of Self-Checking Controllers with Datapath Interactions., IEEE Trans. Computers 55(11): 1423-1434 (2006)
Philippe Clauss, Bénédicte Kenmei, Polyhedral Modeling and Analysis of Memory Access Profiles., ASAP 2006: 191-198
Philippe Faes, Bram Minnaert, Mark Christiaens, Eric Bonnet, Yvan Saeys, Dirk Stroobandt, Yves Van de Peer, Scalable hardware accelerator for comparing DNA and protein sequences., Infoscale 2006: 33
Philippe Grosse, Yves Durand, Paul Feautrier, Power Modeling of a NoC Based Design for High Speed Telecommunication Systems., PATMOS 2006: 157-168
Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini, SHAPES: : a tiled scalable software hardware architecture platform for embedded systems., CODES+ISSS 2006: 167-172
Pierre Amiranoff, Albert Cohen, Paul Feautrier, Beyond Iteration Vectors: Instancewise Relational Abstract Domains., SAS 2006: 161-180
Pierre Palatin, Yves Lhuillier, Olivier Temam, CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs., MICRO 2006: 247-258
Pieter Bellens, Josep M. Pérez, Rosa M. Badia, Jesús Labarta, Memory - CellSs: a programming model for the cell BE architecture., SC 2006: 86
Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii, Enabling fine-grain leakage management by voltage anchor insertion., DATE 2006: 868-873
Piotr Dziurzanski, W. Bielecki, Konrad Trifunovic, M. Kleszczonek, A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description., DDECS 2006: 153-154
Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors., DATE 2006: 339-344
Quan Shi, Ning Xi, Weihua Sheng, Yifan Chen, Development of Dynamic Inspection Methods for Dimensional Measurement of Automotive Body Parts., ICRA 2006: 315-320
Quan Shi, Ning Xi, Yifan Chen, Weihua Sheng, Registration of Point Clouds for 3D Shape Inspection., IROS 2006: 235-240
R. Castillo, Adrian Tineo, Francisco Corbera, Angeles G. Navarro, Rafael Asenjo, Emilio L. Zapata, Towards a Versatile Pointer Analysis Framework., Euro-Par 2006: 323-333
R. R. Osorio, J. D. Bruguera, High-Throughput Architecture for H.264/AVC CABAC Compression System, IEEE Trans. Circuits and Systems for Video Technology
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Implementing the Advanced Switching Minimum Bandwidth Egress Link Scheduler., NCA 2006: 118-125
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Studying Several Proposals for the Adaptation of the DTable Scheduler to Advanced Switching., ISPA 2006: 98-112
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Decoupling the Bandwidth and Latency Bounding for Table-based Schedulers., ICPP 2006: 155-163
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Providing Quality of Service over Advanced Switching., ICPADS (1) 2006: 223-234
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Improving the Flexibility of the Deficit Table Scheduler., HiPC 2006: 84-97
Raúl Sirvent, Josep M. Pérez, Rosa M. Badia, Jesús Labarta, Automatic Grid workflow based on imperative programming languages., Concurrency and Computation: Practice and Experience 18(10): 1169-1186 (2006)
Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser, Estimating Energy Consumption for an MPSoC Architectural Exploration., ARCS 2006: 298-310
Rachid Seghir, Vincent Loechner, Memory optimization by counting points in integer transformations of parametric polytopes., CASES 2006: 74-82
Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida, Pre-synthesis optimization of multiplications to improve circuit performance., DATE 2006: 1306-1311
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, Applying the zeros switch-off technique to reduce static energy in data caches., SBAC-PAD 2006: 133-140
Rainer Buchty, A Monitoring Infrastructure for the Digital on-demand Computing Organism (DodOrg)., IWSOS/EuroNGI 2006: 258
Rainer Buchty, Reconfigurable Architectures and Instruction Sets: Programmability Code Generation and Program Execution., Dynamically Reconfigurable Architectures 2006
Rainer Buchty, Jie Tao, Wolfgang Karl, Automatic Data Locality Optimization Through Self-optimization., IWSOS/EuroNGI 2006: 187-201
Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, M. Pandey, A design flow for configurable embedded processors based on optimized instruction set extension synthesis., DATE 2006: 581-586
Ramon Bertran, Marisa Gil, Javier Cabezas, Lluis Vilanova, Enric Morancho, Nacho Navarro, An Experimental Framework for Whole System Optimization., ACACES 2006
Ramon Bertran, Marisa Gil, Javier Cabezas, Victor Jimenez, Lluis Vilanova, Nacho Navarro, Building a Global System View for Optimization Purposes., WIOSCA 2006
Ramon Bertran, Marisa Gil, Victor Jimenez, Javier Cabezas, Lluis Vilanova, Nacho Navarro, Opportunities for Global Optimization: Breaking the Boundaries Across System Components. Poster Session. , Eurosys 2006
Ramon Nou, Ferran Julià, David Carrera, Kevin Hogan, Jordi Caubet, Jesús Labarta, Jordi Torres, Monitoring and analysing a Grid Middleware Node., GRID 2006: 309-310
Ramon Nou, Jordi Guitart, David Carrera, Jordi Torres, Experiences with Simulations - A Light and Fast Model for Secure Web Applications., ICPADS (1) 2006: 177-186
Raphaël Kummer, Peter Kropf, Pascal Felber, Distributed Lookup in Structured Peer-to-Peer Ad-Hoc Networks., OTM Conferences (2) 2006: 1541-1554
Raymond S. Wagner, Richard G. Baraniuk, Shu Du, David B. Johnson, Albert Cohen, An architecture for distributed wavelet analysis and processing in sensor networks., IPSN 2006: 243-250
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis, Rescheduling for Optimized SHA-1 Calculation., SAMOS 2006: 425-434
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis, Improving SHA-2 Hardware Implementations., CHES 2006: 298-310
Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, Leonel Sousa, Reconfigurable memory based AES co-processor., IPDPS 2006
Rickard Holsmark, Maurizio Palesi, Shashi Kumar, Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions., DSD 2006: 696-703
Robert D. Mullins, Andrew West, Simon W. Moore, The design and implementation of a low-latency on-chip network., ASP-DAC 2006: 164-169
Robert G. Dimond, Oskar Mencer, Wayne Luk, Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA., FCCM 2006: 175-184
Robert G. Dimond, Oskar Mencer, Wayne Luk, Automating processor customisation: optimised memory access and resource sharing., DATE 2006: 206-211
Robert van Engelen, Madhusudhan Govindaraju, Nectarios Koziris, Kleanthis Psarris, Editorial message: special track on distributed systems and grid computing., SAC 2006: 739-740
Roberto Cordone, Fabrizio Ferrandi, Marco D. Santambrogio, Gianluca Palermo, Donatella Sciuto, Using speculative computation and parallelizing techniques to improve scheduling of control based designs., ASP-DAC 2006: 898-904
Roberto R. Osorio, Javier D. Bruguera, High-Throughput Architecture for H.264/AVC CABAC Compression System, IEEE Trans. Circuits and Systems for Video Technology
Roberto R. Osorio, Javier D. Bruguera, A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems, DSD '06: Proceedings of the 9th EUROMICRO Conference on Digital System Design, IEEE Computer Society, August 2006
Roberto R. Osorio, Javier D. Bruguera, High-Throughput Architecture for H.264/AVC CABAC Compression System., IEEE Trans. Circuits Syst. Video Techn. 16(11): 1376-1384 (2006)
Roberto R. Osorio, Javier D. Bruguera, A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems., DSD 2006: 269-274
Rodrigo Piedade, Leonel Sousa, Configurable Embedded Core for Controlling Electro-Mechanical Systems., ARC 2006: 18-23
Roland Ducournau, Etienne Gagnon, Chandra Krintz, Philippe Mulet, Jan Vitek, Olivier Zendra, Implementation Compilation Optimization of Object-Oriented Languages Programs and Systems., ECOOP Workshops 2006: 1-14
Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe, Statistical sampling of microarchitecture simulation., ACM Trans. Model. Comput. Simul. 16(3): 197-224 (2006)
Ron Gabor, Shlomo Weiss, Avi Mendelson, Fairness and Throughput in Switch on Event Multithreading., MICRO 2006: 149-160
Rosa Castillo, Adrian Tineo, Francisco Corbera, Angeles G. Navarro, Rafael Asenjo, Emilio L. Zapata, Towards a Versatile Pointer Analysis Framework., Euro-Par 2006: 323-333
Rosalia Christodoulopoulou, Kaloian Manassiev, Angelos Bilas, Cristiana Amza, Fast and transparent recovery for continuous availability of cluster-based servers., PPOPP 2006: 221-229
Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny, Fast Asynchronous Shift Register for Bit-Serial Communication., ASYNC 2006: 117-127
Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou, High Rate Data Synchronization in GALS SoCs., IEEE Trans. VLSI Syst. 14(10): 1063-1074 (2006)
Rubén Gran Tejero, Enric Morancho, Angel Olive, José María Llabería, An Enhancement for a Scheduling Logic Pipelined over two Cycles, 24º International Conference on Computer Design
Ruben Gran, Enric Morancho, Àngel Olivé, José María Llabería, An Enhancement for a Scheduling Logic Pipelined over two Cycles ., ICCD 2006
Rubing Duan, Radu Prodan, Thomas Fahringer, Data Mining-based Fault Prediction and Detection on the Grid., HPDC 2006: 305-308
Rubing Duan, Radu Prodan, Thomas Fahringer, Run-time Optimisation of Grid Workflow Applications., GRID 2006: 33-40
Rubino Geiß, Gernot Veit Batz, Daniel Grund, Sebastian Hack, Adam Szalkowski, GrGen: A Fast SPO-Based Graph Rewriting Tool., ICGT 2006: 383-397
Rudy Sicard, Thierry Artières, Eric Petit, Patch Learning for Incremental Classifier Design., ECAI 2006: 807-808
Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich, Higher-Dimensional Packing with Order Constraints., SIAM J. Discrete Math. 20(4): 1056-1078 (2006)
Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich, Minimizing Communication Cost for Reconfigurable Slot Modules., FPL 2006: 1-6
Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser, FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar., DSD 2006: 280-287
S. Bartolini, P. Foglia, C. A. Prete, Embedded processors and systems: Architectural issues and solutions for emerging applications, Journal of Embedded Computing , Volume 2 Issue 1, IOS Press, January 2006
S. Bartolini, P. Foglia, R. Giorgi, C. A. Prete, Memory performance: dealing with applications, systems and architecture, MEDEA '05: Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture, ACM, March 2006
S. Momcilovic, Tiago Dias, Nuno Roma, Leonel Sousa, Application Specific Instruction Set Processor for Adaptive Video Motion Estimation., DSD 2006: 160-167
Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Opens and Delay Faults in CMOS RAM Address Decoders., IEEE Trans. Computers 55(12): 1630-1639 (2006)
Salvador Petit, Julio Sahuquillo, Ana Pont, David R. Kaeli, Addressing a workload characterization study to the design of consistency protocols., The Journal of Supercomputing 38(1): 49-72 (2006)
Salvador Petit, Noel Tomás, Julio Sahuquillo, Ana Pont, An execution-driven simulation tool for teaching cache memories in introductory computer organization courses., WCAE 2006: 4
Sami Yehia, Jean-Francois Collard, Olivier Temam, Load squared: Adding logic close to memory to reduce the latency of indirect loads in embedded and general systems, Journal of Embedded Computing , Volume 2 Issue 1, IOS Press, January 2006
Sandrine Boumard, Matti Weissenfelt, Huageng Chi, Jari Nurmi, A Wireless MIMO STC OFDM System Implementation., PIMRC 2006: 1-5
Sandro Bartolini, Roberto Giorgi, Issues in Embedded Single-Chip Multicore Architectures, Journal of Embedded Computing , Volume 2 Issue 2, IOS Press, April 2006
Sarah Thompson, Alan Mycroft, Bit-level partial evaluation of synchronous circuits., PEPM 2006: 29-37
Sascha Uhrig, S. Maier, Georgi Kuzmanov, Theo Ungerer, Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling., IPDPS 2006
Sathish Chandra, Francesco Regazzoni, Marcello Lajolo, Hardware/software partitioning of operating systems: a behavioral synthesis approach., ACM Great Lakes Symposium on VLSI 2006: 324-329
Satish Narayanasamy, Gilles Pokam, Brad Calder, BugNet: Recording Application-Level Execution for Deterministic Replay Debugging., IEEE Micro 26(1): 100-109 (2006)
Scott Schneider, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Scalable locality-conscious multithreaded memory allocation., ISMM 2006: 84-94
Sebastian Hack, Daniel Grund, Gerhard Goos, Register Allocation for Programs in SSA-Form., CC 2006: 247-262
Seon Wook Kim, Chong-liang Ooi, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar, Exploiting reference idempotency to reduce speculative storage overflow., ACM Trans. Program. Lang. Syst. 28(5): 942-965 (2006)
Seongsoo Hong, Wayne Wolf, Krisztián Flautner, Taewhan Kim, Proceedings of the 2006 International Conference on Compilers Architecture and Synthesis for Embedded Systems CASES 2006 Seoul Korea October 22-25 2006, ACM 2006
Sergio Saponara, Pierangelo Terreni, Mixed-signal design of a digital input power amplifier for automotive audio applications., DATE Designers' Forum 2006: 212-216
Sherif Yusuf, Wayne Luk, M. K. N. Szeto, W. G. Osborne, UNITE: Uniform Hardware-Based Network Intrusion deTection Engine., ARC 2006: 389-400
Shimin Chen, Babak Falsafi, Phillip B. Gibbons, Michael Kozuch, Todd C. Mowry, Radu Teodorescu, Anastassia Ailamaki, Limor Fix, Gregory R. Ganger, Bin Lin, Steven W. Schlosser, Log-based architectures for general-purpose monitoring of deployed code., ASID 2006: 63-65
Shinichi Yamagiwa, Leonel Sousa, Kevin Ferreira, Keiichi Aoki, Masaaki Ono, Koichi Wada, Maestro2: Experimental Evaluation of Communication Performance Improvement Techniques in the Link Layer., Journal of Interconnection Networks 7(2): 295-318 (2006)
Shiyong Lu, Feng Cao, Yi Lu, Pama: a Fast String Matching Algorithm., Int. J. Found. Comput. Sci. 17(2): 357-378 (2006)
Sid Ahmed Ali Touati, Denis Barthou, On the decidability of phase ordering problem in optimizing compilation., Conf. Computing Frontiers 2006: 147-156
Silvia Alayón, J. I. Estévez, Jose F. Sigut, José L. Sánchez, P. Toledo, An evolutionary Michigan recurrent fuzzy system for nuclei classification in cytological images using nuclear chromatin distribution., Journal of Biomedical Informatics: 573-588 (2006)
Simon Künzli, Francesco Poletti, Luca Benini, Lothar Thiele, Combining simulation and formal methods for system-level performance analysis., DATE 2006: 236-241
Simona Rossi, Daniele Masotti, Christine Nardini, Elena Bonora, Giovanni Romeo, Enrico Macii, Luca Benini, Stefano Volinia, TOM: a web-based integrated approach for identification of candidate disease genes., Nucleic Acids Research 34(Web-Server-Issue): 285-292 (2006)
Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo, Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA., ICSAMOS 2006: 107-114
Smaïl Niar, Nicolas Inglart, Rapid Performance and Power Consumption Estimation Methods for Embedded System Design., IEEE International Workshop on Rapid System Prototyping 2006: 47-53
Sonia González, Angeles G. Navarro, Juan López, Emilio L. Zapata, A Case Study of Load Sharing Based on Popularity in Distributed VoD Systems., IEEE Transactions on Multimedia 8(6): 1299-1304 (2006)
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk, Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs., ISQED 2006: 570-575
Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli, A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip., DAC 2006: 845-848
Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli, A methodology for mapping multiple use-cases onto networks on chips., DATE 2006: 118-123
Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli, Mapping and configuration methods for multi-use-case networks on chips., ASP-DAC 2006: 146-151
Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo, Designing application-specific networks on chips with floorplan information., ICCAD 2006: 355-362
Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo, Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips., VLSI-SoC 2006: 158-163
Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz, PISC: Polymorphic Instruction Set Computers., ARC 2006: 274-286
Stamatis Vassiliadis, Ioannis Sourdis, FLUX Networks: Interconnects on Demand., ICSAMOS 2006: 160-167
Stamatis Vassiliadis, Stephan Wong, Timo Hämäläinen, Embedded Computer Systems: Architectures Modeling and Simulation 6th International Workshop SAMOS 2006 Samos Greece July 17-20 2006 Proceedings, Springer 2006
Stavros Papastavrou, George Samaras, Paraskevas Evripidou, Panos K. Chrysanthis, A decade of dynamic web content: A structured survey on past and present practices and future trends., IEEE Communications Surveys and Tutorials 8(1-4): 52-60 (2006)
Stavros Polyviou, George Samaras, Paraskevas Evripidou, Active Folders: A Metaphor for Developing and Interacting with Context-Aware Applications., MDM 2006: 146
Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner, Effective compiler generation by architecture description., LCTES 2006: 145-152
Stefan Holdermans, Johan Jeuring, Andres Löh, Alexey Rodriguez, Generic Views on Data Types., MPC 2006: 209-234
Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal, Profiling Driven Scenarion Detection and Prediction for Multimedia Applications., ICSAMOS 2006: 63-70
Stefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, Antonio Poggiali, Supporting task migration in multi-processor systems-on-chip: a feasibility study., DATE 2006: 15-20
Stephane Piskorski, Lionel Lacassagne, Efficient 16-bit Floating-Point Interval Processor for Embedded Systems and Applications, SCAN '06: Proceedings of the 12th GAMM - IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics (SCAN 2006) - Volume 00 , Volume 00, IEEE Computer Society, September 2006
Stephen Childs, Brian A. Coghlan, Jason McCandless, GridBuilder: A Tool for Creating Virtual Grid Testbeds., e-Science 2006: 77
Stephen Childs, Brian A. Coghlan, Jason McCandless, Dynamic Virtual Worker Nodes in a Production Grid., ISPA Workshops 2006: 417-426
Stephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos, Spatial Memory Streaming., ISCA 2006: 252-263
Steve Furber, Living with Failure: Lessons from Nature?, ETS '06: Proceedings of the Eleventh IEEE European Test Symposium (ETS'06) - Volume 00 , Volume 00, IEEE Computer Society, May 2006
Steve McKeever, Wayne Luk, Provably-correct hardware compilation tools based on pass separation techniques., Formal Asp. Comput. 18(2): 120-142 (2006)
Stijn Eyerman, James E. Smith, Lieven Eeckhout, Characterizing the branch misprediction penalty., ISPASS 2006: 48-58
Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere, Efficient design space exploration of high performance embedded out-of-order processors., DATE 2006: 351-356
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith, A performance counter architecture for computing accurate CPI components., ASPLOS 2006: 175-184
Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis, Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance., Computer Communications 29(13-14): 2612-2620 (2006)
Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Energy-efficient dynamic memory allocators at the middleware level of embedded systems., EMSOFT 2006: 215-222
Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems., DATE 2006: 874-875
Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk, A Flexible Multi-port Caching Scheme for Reconfigurable Platforms., ARC 2006: 205-216
Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk, Efficient Realtime FPGA Implementation of the Trace Transform., FPL 2006: 1-6
Suleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Ozcan Ozturk, An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors., ISCIS 2006: 267-276
Sungroh Yoon, Luca Benini, Giovanni De Micheli, A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis., IEEE Trans. on CAD of Integrated Circuits and Systems 25(2): 358-377 (2006)
Sutjipto Arifin, Peter Y. K. Cheung, User Attention Based Arousal Content Modeling., ICIP 2006: 433-436
Sutjipto Arifin, Peter Y. K. Cheung, Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System., FPL 2006: 1-4
Sutjipto Arifin, Peter Y. K. Cheung, A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation., DATE Designers' Forum 2006: 227-232
Suzanne Rivoire, Rebecca Schultz, Tomofumi Okuda, Christos Kozyrakis, Vector Lane Threading., ICPP 2006: 55-64
Svetislav Momcilovic, Tiago Dias, Nuno Roma, Leonel Sousa, Application Specific Instruction Set Processor for Adaptive Video Motion Estimation., DSD 2006: 160-167
Sylvain Girbal, Nicolas Vasilache, Cédric Bastoul, Albert Cohen, David Parello, Marc Sigler, Olivier Temam, Semi-Automatic Composition of Loop Transformations for Deep Parallelism and Memory Hierarchies., International Journal of Parallel Programming 34(3): 261-317 (2006)
T. Nachiondo, Jose Flich, José Duato, Destination-Based HoL Blocking Elimination., ICPADS (1) 2006: 213-222
T. Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé, Performance power efficiency and scalability of asymmetric cluster chip multiprocessors., Computer Architecture Letters 5(1): 14-17 (2006)
Taeho Kgil, Shaun D'Souza, Ali G. Saidi, Nathan L. Binkert, Ronald G. Dreslinski, Trevor N. Mudge, Steven K. Reinhardt, Krisztián Flautner, PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor., ASPLOS 2006: 117-128
Talal Bonny, Joerg Henkel, Using Lin-Kernighan algorithm for look-up table compression to improve code density, GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI, ACM, April 2006
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero, A simple speculative load control mechanism for energy saving, MEDEA '06: Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures, ACM, September 2006
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero, Kilo-instruction processors runahead and prefetching., Conf. Computing Frontiers 2006: 269-278
Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala, Low-Power High-Performance TTA Processor for 1024-Point Fast Fourier Transform., SAMOS 2006: 227-236
Teresa Olivares, P. J. Tirado, Luis Orozco-Barbosa, Vicente López, P. Pedrón, Simulation of power-aware wireless sensor network architectures., PM2HW2N 2006: 32-39
Tero Arpinen, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications., DATE 2006: 1324-1329
Tero Kangas, Petri Kukkala, Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Jouni Riihimäki, Kimmo Kuusilinna, UML-based multiprocessor SoC design framework., ACM Trans. Embedded Comput. Syst. 5(2): 281-320 (2006)
Tero Kangas, Timo D. Hämäläinen, Kimmo Kuusilinna, Scalable Architecture for SoC Video Encoders., VLSI Signal Processing 44(1-2): 79-95 (2006)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, On-FPGA Communication Architectures and Design Factors., FPL 2006: 1-8
Tewolde Ghebregziabher, Jani Puttonen, Timo Hämäläinen, Ari Viinikainen, Security Analysis of Flow-based Fast Handover Method for Mobile IPv6 Networks., AINA (2) 2006: 849-853
Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, A Parallel Architecture for Hardware Face Detection., ISVLSI 2006: 452-453
Theocharis Theocharides / Vijay Narayanan, Embedded hardware face detection for digital surveillance systems, Embedded hardware face detection for digital surveillance systems, Pennsylvania State University, January 2006
Thierry Joffrain, Tze Meng Low, Enrique S. Quintana-Ortí, Robert A. van de Geijn, Field G. Van Zee, Accumulating Householder transformations revisited., ACM Trans. Math. Softw. 32(2): 169-179 (2006)
Thilo Streichert, Christian Haubelt, Jürgen Teich, Multi-Objective Topology Optimization for Networked Embedded Systems., ICSAMOS 2006: 93-98
Thilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich, Dynamic task binding for hardware/software reconfigurable networks., SBCCI 2006: 38-43
Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich, Modeling and design of fault-tolerant and self-adaptive reconfigurable networked embedded systems, EURASIP Journal on Embedded Systems , Volume 2006 Issue 1, Hindawi Publishing Corp., January 2006
Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe, Statistical sampling of microarchitecture simulation., IPDPS 2006
Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe, Simulation sampling with live-points., ISPASS 2006: 2-12
Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe, SimFlex: Statistical Sampling of Computer System Simulation., IEEE Micro 26(4): 18-31 (2006)
Thomas Fahringer, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks as part of the 24th IASTED International Multi-Conference on Applied Informatics February 14-16 2006 Innsbruck Austria, IASTED/ACTA Press 2006
Thomas Fahringer, Towards a sophisticated grid workflow development and computing environment., IPDPS 2006
Thomas J. Ashby, Anthony D. Kennedy, Stephen M. Watt, Coxeter Lattice Paths., Challenges in Symbolic Computation Software 2006
Thomas J. Ashby, Michael F. P. O'Boyle, Iterative Collective Loop Fusion., CC 2006: 202-216
Thomas Sødring, Raúl Martínez, Geir Horn, A Statistical Approach to Traffic Management in Source Routed Loss-Less Networks., HPCC 2006: 190-199
Thomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich, Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms., ISVLSI 2006: 309-316
Tiago Dias, Nuno Roma, Leonel Sousa, Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators., PATMOS 2006: 247-255
Tim Kogel, Rainer Leupers, Heinrich Meyr, Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms, Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms, Springer-Verlag New York, Inc., July 2006
Timo Vanhatupa, Marko Hännikäinen, Timo D. Hämäläinen, Evaluation of throughput estimation models and algorithms for WLAN frequency planning, QShine '06: Proceedings of the 3rd international conference on Quality of service in heterogeneous wired/wireless networks, ACM, August 2006
Timo Vogt, Christian Neeb, Norbert Wehn, A Reconfigurable Multi-Processor Platform for Convolutional and Turbo Decoding., ReCoSoC 2006: 16-23
Tiziana Gravagnoli, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, Automatic Test Pattern Generation with BOA., PPSN 2006: 423-432
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney, Aligning traces for performance evaluation., IPDPS 2006
Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng, Off-Line Testing of Delay Faults in NoC Interconnects., DSD 2006: 677-680
Tor Skeie, Svein Johannessen, Øyvind Holmeide, Timeliness of real-time IP communication in switched industrial Ethernet networks., IEEE Trans. Industrial Informatics 2(1): 25-39 (2006)
Torben Brack, Frank Kienle, Norbert Wehn, Disclosing the LDPC code decoder design space., DATE 2006: 200-205
Torben Brack, Matthias Alles, Frank Kienle, Norbert Wehn, A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding., PIMRC 2006: 1-5
Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, A SW performance estimation framework for early system-level-design using fine-grained instrumentation., DATE 2006: 468-473
Torvald Riegel, Pascal Felber, Christof Fetzer, A Lazy Snapshot Algorithm with Eager Validation., DISC 2006: 284-298
Tudor Niculiu, Cristian Lupu, Sorin Cotofana, Consciousness for modeling intelligence - simulating the evolution by closure to the inverse., ICINCO-ICSO 2006: 187-190
Tuomas Järvinen, Perttu Salmela, Konsta Punkka, Jarmo Takala, Evaluation of stride permutation networks., ISCAS 2006
Uri Frank, Tsachy Kapschitz, Ran Ginosar, A predictive synchronizer for periodic clock domains., Formal Methods in System Design 28(2): 171-186 (2006)
Uwe Brinkschulte, Scalable Online Feasibility Tests for Admission Control in a Java Real-Time System., Real-Time Systems 32(3): 175-195 (2006)
Uwe Brinkschulte, Alexander von Renteln, Mathias Pacher, A Scheduling Strategy for a Real-Time Dependable Organic Middleware., SAMOS 2006: 339-348
Uwe Brinkschulte, Mathias Pacher, Florentin Picioroaga, Stefan Gaa, Evaluation of the Komodo Microcontroller and the OSA+ Middleware Using an Autonomous Guided Vehicle., ISORC 2006: 550-557
Víctor Reyes, Wido Kruijtzer, Tomás Bautista, Ghiath Alkadi, Antonio Núñez, A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study., DATE 2006: 474-479
Valentin Kravtsov, Thomas Niessen, Vlado Stankovski, Assaf Schuster, Service-based Resource Brokering for Grid-Based Data Mining., GCA 2006: 163-169
Valentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide, Cruz Izu, High-performance adaptive routing for networks with arbitrary topology., Journal of Systems Architecture 52(6): 345-358 (2006)
Valery Sklyarov, Iouliia Skliarova, Reconfigurable Systems and their Influence on Mobile and Multimedia Applications., MoMM 2006: 7-8
Valery Sklyarov, Iouliia Skliarova, Multimedia Tools for Teaching Reconfigurable Systems., MoMM 2006: 211-220
Valery Sklyarov, Iouliia Skliarova, Recursive and Iterative Algorithms for N-ary Search Problems., IFIP PPAI 2006: 81-90
Valery Sklyarov, Iouliia Skliarova, Evolutionary Algorithm for State Encoding., IFIP AI 2006: 227-236
Valery Sklyarov, Iouliia Skliarova, E-learning Tools and Web-resources for Teaching Reconfigurable Systems., Education for the 21st Century 2006: 215-224
Vanco B. Litovski, Miona Andrejevic, Mark Zwolinski, Analogue electronic circuit diagnosis based on ANNs., Microelectronics Reliability 46(8): 1382-1391 (2006)
Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson, Parallel depth first vs. work stealing schedulers on CMP architectures., SPAA 2006: 330
Vasilis F. Pavlidis, Eby G. Friedman, Via placement for minimum interconnect delay in three-dimensional (3D) circuits., ISCAS 2006
Vassilis Papaefstathiou, Ioannis Papaefstathiou, A hardware-engine for layer-2 classification in low-storage ultra-high bandwidth environments., DATE Designers' Forum 2006: 112-117
Vassos S. Soteriou / Li-Shiuan Peh, Run-time and design-time techniques towards power-efficient interconnection networks, Run-time and design-time techniques towards power-efficient interconnection networks, Princeton University, January 2006
Vassos Soteriou, Hangsheng Wang, Li-Shiuan Peh, A Statistical Traffic Model for On-Chip Interconnection Networks., MASCOTS 2006: 104-116
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh, Polaris: A System-Level Roadmap for On-Chip Interconnection Networks., ICCD 2006
Veerle Desmet, Lieven Eeckhout, Koen De Bosschere, Improved composite confidence mechanisms for a perceptron branch predictor., Journal of Systems Architecture 52(3): 143-151 (2006)
Veljko M. Milutinovic, Our Profession Needs a Reminder., IEEE Computer 39(5): 102-104 (2006)
Viay Holimath, Javier D. Bruguera, A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table., DSD 2006: 236-239
Viktor Yarmolenko, Rizos Sakellariou, An evaluation of heuristics for SLA based parallel job scheduling., IPDPS 2006
Vincent Nollet, Prabhat Avasare, Diederik Verkest, Henk Corporaal, Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment., ERSA 2006: 49-55
Wei Xing, Marios D. Dikaiakos, Rizos Sakellariou, A Core Grid Ontology for the Semantic Grid., CCGRID 2006: 178-184
Weichao Wang, Bharat K. Bhargava, Yi Lu, Xiaoxin Wu, Defending against wormhole attacks in mobile ad hoc networks., Wireless Communications and Mobile Computing 6: 483-503 (2006)
Weihaw Chuang, Satish Narayanasamy, Ganesh Venkatesh, Jack Sampson, Michael Van Biesbrouck, Gilles Pokam, Brad Calder, Osvaldo Colavin, Unbounded page-based transactional memory., ASPLOS 2006: 347-358
Weihua Sheng, Girma S. Tewolde, Developing Active Sensor Networks with Micro Mobile Robots: Distributed Node Localization., FLAIRS Conference 2006: 478-483
Weihua Sheng, Girma S. Tewolde, Song Ci, Micro Mobile Robots in Active Sensor Networks: Closing the Loop., IROS 2006: 1440-1445
Weihua Sheng, Qingyan Yang, Jindong Tan, Ning Xi, Distributed multi-robot coordination in area exploration., Robotics and Autonomous Systems 54(12): 945-955 (2006)
Weihua Sheng, Qingyan Yang, Yi Guo, Cooperative Driving based on Inter-vehicle Communications: Experimental Platform and Algorithm., IROS 2006: 5073-5078
Weihua Sheng, Yantao Shen, Ning Xi, Mobile Sensor Navigation with Miniature Active Camera for Structure Inspection., IROS 2006: 1177-1182
Weizhe Zhang, Binxing Fang, Mingzeng Hu, Xinran Liu, Hongli Zhang, Lei Gao, Multisite co-allocation scheduling algorithms for parallel jobs in computing grid environments., Science in China Series F: Information Sciences 49(6): 906-926 (2006)
William Jalby, Christophe Lemuet, Sid Ahmed Ali Touati, An efficient memory operations optimization technique for vector loops on Itanium 2 processors., Concurrency and Computation: Practice and Experience 18(11): 1485-1508 (2006)
William Jalby, Oscar G. Plata, Barbara M. Chapman, Paul Kelly, Topic 4: Compilers for High Performance., Euro-Par 2006: 277
Wim Heirman, Joni Dambre, Jan M. Van Campenhout, Congestion modeling for reconfigurable inter-processor networks., SLIP 2006: 59-66
Wojciech Kabacinski, Marek Michalski, The Routing Algorithm and Wide-Sense Nonblocking Conditions for Multiplane Baseline Switching Networks., IEEE Journal on Selected Areas in Communications 24(S-12): 35-44 (2006)
Wolfgang Karl, Jürgen Becker, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle, ARCS 2006 - 19th International Conference on Architecture of Computing Systems Workshops Proceedings March 16 2006 Frankfurt am Main Germany, GI 2006
Wolfgang Trumler, Jan Petzold, Faruk Bagci, Theo Ungerer, AMUN: an autonomic middleware for the Smart Doorplate Project., Personal and Ubiquitous Computing 10(1): 7-11 (2006)
Wolfgang Trumler, Robert Klaus, Theo Ungerer, Self-configuration Via Cooperative Social Behavior., ATC 2006: 90-99
Wolfgang Trumler, Tobias Thiemann, Theo Ungerer, An Artificial Hormone System for Self-organization of Networked Nodes., BICC 2006: 85-94
Wouter Caarls, Pieter P. Jonker, Henk Corporaal, Skeletons and Asynchronous RPC for Embedded Data and Task Parallel Image Processing., IEICE Transactions 89-D(7): 2036-2043 (2006)
Wouter Caarls, Pieter P. Jonker, Henk Corporaal, Algorithmic skeletons for stream programming in embedded heterogeneous parallel image processing applications., IPDPS 2006
Xavier Martorell, Marc González, Alejandro Duran, Jairo Balart, Roger Ferrer, Eduard Ayguadé, Jesús Labarta, Techniques supporting threadprivate in OpenMP., IPDPS 2006
Xiaoning Ding, Dimitrios S. Nikolopoulos, Song Jiang, Xiaodong Zhang, MESA: reducing cache conflicts by integrating static and run-time methods., ISPASS 2006: 189-198
Xiaoyuan Yang, Porfidio Hernández, Fernando Cores, Ana Ripoll, Remo Suppi, Emilio Luque, Providing VCR in a Distributed Client Collaborative Multicast Video Delivery Scheme., Euro-Par 2006: 777-787
Xiaoyuan Yang, Porfidio Hernández, Fernando Cores, Leandro Souza, Ana Ripoll, Remo Suppi, Emilio Luque, DVoDP/sup 2/P: distributed P2P assisted multicast VoD architecture., IPDPS 2006
Xin Wang, Tapani Ahonen, Jari Nurmi, Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools., FPL 2006: 1-6
Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, A Spatiotemporal Saliency Framework., ICIP 2006: 437-440
Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley, Hardware efficient architectures for Eigenvalue computation., DATE 2006: 953-958
Yang Qu, Juha-Pekka Soininen, Jari Nurmi, A parallel configuration model for reducing the run-time reconfiguration overhead., DATE 2006: 965-969
Yehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz, Michael Vinov, Eitan Marcus, Gil Shurek, Constraint-Based Random Stimuli Generation for Hardware Verification., AAAI 2006
Yehuda Sadeh Weinraub, Shlomo Weiss, Power-aware out-of-order issue logic in high-performance microprocessors., Microprocessors and Microsystems 30(7): 457-467 (2006)
Yi Lu / Shiyong Lu, Advanced data mining techniques for identifying correlation between gene expression and promoters, Advanced data mining techniques for identifying correlation between gene expression and promoters, Wayne State University, January 2006
Yi Lu, Adrian E. Platts, G. Charles Ostermeier, Stephen A. Krawetz, K-SPMM: a database of murine spermatogenic promoters modules & motifs., BMC Bioinformatics 7: 238 (2006)
Yi Lu, Shiyong Lu, Adrian E. Platts, Stephen A. Krawetz, Mining Correlation between Motifs and Gene Expression., ICDM 2006: 986-990
Yi Lu, Shiyong Lu, Farshad Fotouhi, Yan Sun, Zijiang Yang, Lily R. Liang, PDC: Pattern discovery with confidence in DNA sequences., ACST 2006: 345-350
Yi Lu, Shiyong Lu, Jeffrey L. Ram, Fast search in DNA sequence databases using punctuation and indexing., ACST 2006: 351-356
Yi Lu, Shiyong Lu, Lily R. Liang, Deepak Kumar, FM-test: A Fuzzy Set Theory Based Approach for Discovering Diabetes Genes., IMSCCS (1) 2006: 48-55
Yi Lu, Weichao Wang, Bharat K. Bhargava, Dongyan Xu, Trust-based privacy preservation for peer-to-peer data sharing., IEEE Transactions on Systems Man and Cybernetics Part A 36(3): 498-502 (2006)
Yitzhak Birk, Idit Keidar, Liran Liss, Assaf Schuster, Efficient Dynamic Aggregation., DISC 2006: 90-104
Yitzhak Birk, Idit Keidar, Liran Liss, Assaf Schuster, Ran Wolff, Veracity radius: capturing the locality of distributed computations., PODC 2006: 102-111
Yoav Etsion, Dan Tsafrir, Dror G. Feitelson, Process prioritization using output production: Scheduling for multimedia., TOMCCAP 2(4): 318-342 (2006)
Yolanda Becerra, Jordi Garcia, Toni Cortes, Nacho Navarro, Java Virtual Machine: the key for accurated memory prefetching., Software Engineering Research and Practice 2006: 933-939
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner, SODA: A Low-power Architecture For Software Radio., ISCA 2006: 89-101
Yunhe Shi, Emre Özer, David Gregg, Low-Cost Microarchitectural Techniques for Enhancing the Prediction of Return Addresses on High-Performance Trace Cache Processors., ISCIS 2006: 248-257
Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Space of DRAM fault models and corresponding testing., DATE 2006: 1252-1257
Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Sultan M. Al-Harbi, Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs., IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2989-2996 (2006)
Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari, HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems., Microprocessors and Microsystems 30(2): 72-85 (2006)
Zsolt Németh, Michail Flouris, Renaud Lachaize, Angelos Bilas, Support for Automatic Diagnosis and Dynamic Configuration of Scalable Storage Systems., Euro-Par Workshops 2006: 15-21
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny, Efficient link capacity and QoS design for network-on-chip., DATE 2006: 9-14

2007

Ahmed Abdel-Hafez, Ali Miri, Luis Orozco-Barbosa, Authenticated Group Key Agreement Protocols for Ad hoc Wireless Networks., I. J. Network Security 4(1): 90-98 (2007)
Alessio Bechini, Andrea Tomasi, Jacopo Viotto, Document Management for Collaborative e-Business: Integrating EBXML Environment and Legacy DMS., ICE-B 2007: 78-83
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere, Classifying interprocess communication in process network representation of nested-loop programs., ACM Trans. Embedded Comput. Syst. 6(2): (2007)
Christoph W. Kessler, Andrzej Bednarski, Mattias V. Eriksson, Classification and generation of schedules for VLIW processors., Concurrency and Computation: Practice and Experience 19(18): 2369-2389 (2007)
Christoph W. Kessler, Welf Löwe, A Framework for Performance-Aware Composition of Explicitly Parallel Components., PARCO 2007: 227-234
Giovanni Agosta, Gerardo Pelosi, A Domain Specific Language for Cryptography., FDL 2007: 159-164
Giovanni Agosta, Luca Breveglieri, Gerardo Pelosi, Israel Koren, Countermeasures against Branch Target Buffer Attacks., FDTC 2007: 75-79
Giovanni Agosta, Luca Breveglieri, Gerardo Pelosi, Martino Sykora, Programming Highly Parallel Reconfigurable Architectures for Public-Key Cryptographic Applications., ITNG 2007: 3-10
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere, Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips., FPL 2007: 580-584
José M. Badía, Peter Benner, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Alfredo Remón, Parallel Implementation of LQG Balanced Truncation for Large-Scale Systems., LSSC 2007: 227-234
Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran, , RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks., DAC 2007: 489-492
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Cristina Silvano, , A data protection unit for NoC-based architectures., CODES+ISSS 2007: 167-172
M. Danish, Arees Qamareen, Shashi Kumar, Surendra Kumar, Letter to the Editor., Computers & Chemical Engineering 31(10): 1364-1365 (2007)
Mikel Luján, Phyllis Gustafson, Michael Paleczny, Christopher A. Vick, Speculative Parallelization - Eliminating the Overhead of Failure., HPCC 2007: 460-471
Mikhail Chalabine, Christoph W. Keßler, A Survey of Reasoning in Parallelization., SNPD (3) 2007: 629-634
Mikhail Chalabine, Christoph W. Kessler, A Formal Framework for Automated Round-Trip Software Engineering in Static Aspect Weaving and Transformations., ICSE 2007: 137-146
Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. Deprettere, Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation., IEEE Transactions on Signal Processing 55(6-2): 3126-3138 (2007)
Mohamed Hussein, Kenneth R. Mayes, Mikel Luján, John R. Gurd, Adaptive performance control for distributed scientific coupled models., ICS 2007: 274-283
N. Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Arvind M, Prem Kumar Ramesh, Karthik Ganesan, Viswanath Krish, Future generation supercomputers II: a paradigm for cluster architecture., SIGARCH Computer Architecture News 35(5): 61-70 (2007)
Pablo Ituero, José L. Ayala, Marisa López-Vallejo, Leakage-based On-Chip Thermal Sensor for CMOS Technology., ISCAS 2007: 3327-3330
Perttu Salmela, Chung-Ching Shen, Shuvra S. Bhattacharyya, Jarmo Takala, Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations., SiPS 2007: 475-480
Perttu Salmela, Juho Antikainen, Olli Silvén, Jarmo Takala, Memory-Based List Updating for List Sphere Decoders., SiPS 2007: 633-638
Reiner Hartenstein, , The Neumann Syndrome calls for a revolution., HPRCTA 2007
Saeed Samet, Ali Miri, Luis Orozco-Barbosa, Privacy Preserving k-Means Clustering in Multi-Party Environment., SECRYPT 2007: 381-385
Stéphanie Lanche, Tron A. Darvann, Hildur Ólafsdóttir, Nuno V. Hermann, Andrea E. Van Pelt, Daniel Govier, Marissa J. Tenenbaum, Sybill Naidoo, Per Larsen, Sven Kreiborg, Rasmus , A Statistical Model of Head Asymmetry in Infants with Deformational Plagiocephaly., SCIA 2007: 898-907
Vanderlei Bonato, Eduardo Marques, George A. Constantinides, A floating-point Extended Kalman Filter implementation for autonomous mobile robots., FPL 2007: 576-579
Zoran Babovic, Darko Jovic, Veljko M. Milutinovic, Survey of eGovernment Services in Serbia., Informatica (Slovenia) 31(4): 379-396 (2007)
Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi, A New Family of High.Performance Parallel Decimal Multipliers., IEEE Symposium on Computer Arithmetic 2007: 195-204
Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi, A radix-10 SRT divider based on alternative BCD codings., ICCD 2007: 280-287
Åshild Grønstad Solheim, Olav Lysne, Thomas Sødring, Tor Skeie, Jakob Aleksander Libak, Routing-Contained Virtualization Based on Up*/Down* Forwarding., HiPC 2007: 500-513
Éric Piel, Philippe Marquet, Jean-Luc Dekeyser, Model Transformations for the Compilation of Multi-processor Systems-on-Chip., GTTSE 2007: 459-473
A. Bai, Tor Skeie, Paal E. Engelstad, A Model-Based Admission Control for 802.11e EDCA using Delay Predictions., IPCCC 2007: 226-235
A. Bardine, P. Foglia, G. Gabrielli, C. A. Prete, P. Stenström, Improving power efficiency of D-NUCA caches, SIGARCH Computer Architecture News , Volume 35 Issue 4, ACM, September 2007
A. Mejia, Jose Flich, José Duato, Sven-Arne Reinemo, Tor Skeie, Boosting Ethernet Performance by Segment-Based Routing., PDP 2007: 55-62
Abbas Bigdeli, Colin Sim, Morteza Biglari-Abhari, Brian C. Lovell, Face Detection on Embedded Systems., ICESS 2007: 295-308
Abou El Hassan Benyamina, Pierre Boulet, Multi-objective Mapping for NoC Architectures., JDIM 5(6): 378-384 (2007)
Afrin Naz, Krishna M. Kavi, Jung-Hwan Oh, Pierfrancesco Foglia, Reconfigurable split data caches: a novel scheme for embedded systems., SAC 2007: 707-712
Aggelos Ioannou, Manolis Katevenis, Pipelined heap (priority queue) management for advanced scheduling in high-speed networks., IEEE/ACM Trans. Netw. 15(2): 450-461 (2007)
Ahmad Zmily, Christos Kozyrakis, A low power front-end for embedded processors using a block-aware instruction set., CASES 2007: 267-276
Ajay K. Verma, Paolo Ienne, Automatic synthesis of compressor trees: reevaluating large counters., DATE 2007: 443-448
Ajay K. Verma, Paolo Ienne, Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands., ASP-DAC 2007: 601-608
Ajay K. Verma, Philip Brisk, Paolo Ienne, Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits., DAC 2007: 404-409
Ajay K. Verma, Philip Brisk, Paolo Ienne, Rethinking custom ISE identification: a new processor-agnostic method., CASES 2007: 125-134
Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John, Exploring the Application Behavior Space Using Parameterized Synthetic Benchmarks., PACT 2007: 412
Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal, Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip., DATE 2007: 117-122
Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha, A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices., DAC 2007: 726-731
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal, Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA., FPL 2007: 92-97
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal, Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA, IEEE Circuit and Systems Society
Alain Darte, C. Quinson, Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis., ASAP 2007: 140-147
Alan Mycroft, Programming Language Design and Analysis Motivated by Hardware Evolution., SAS 2007: 18-33
Alastair F. Donaldson, Alice Miller, Extending Symmetry Reduction Techniques to a Realistic Model of Computation., Electr. Notes Theor. Comput. Sci. 185: 63-76 (2007)
Alastair F. Donaldson, Alice Miller, David Parker, GRIP: Generic Representatives in PRISM., QEST 2007: 115-116
Alastair F. Donaldson, Colin Riley, Anton Lokhmotov, Andrew Cook, Auto-parallelisation of Sieve C++ Programs., Euro-Par Workshops 2007: 18-27
Alberto Ros, Manuel E. Acacio, José M. García, Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors., HiPC 2007: 147-160
Alejandro Calderón, Félix García Carballeira, Florin Isaila, Rainer Keller, Alexander Schulz, Fault Tolerant File Models for MPI-IO Parallel File Systems., PVM/MPI 2007: 153-160
Alejandro Calderón, Félix García Carballeira, Luis Miguel Sánchez, José Daniel García, Javier Fernández, Fault tolerant file models for parallel file systems: distribution pattern flexibility and its reliability., PDPTA 2007: 676-682
Alejandro Duran, Roger Ferrer, Juan José Costa, Marc González, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, A Proposal for Error Handling in OpenMP., International Journal of Parallel Programming 35(4): 393-416 (2007)
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, Francisco J. Quiles, José Duato, A New Cost-Effective Technique for QoS Support in Clusters., IEEE Trans. Parallel Distrib. Syst. 18(12): 1714-1726 (2007)
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato, Efficient Switches with QoS Support for Clusters., IPDPS 2007: 1-6
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato, Providing Full QoS with 2 VCs in High-Speed Switches., ICOIN 2007: 345-354
Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato, Deadline-based QoS Algorithms for High-performance Networks., IPDPS 2007: 1-9
Alejandro Martínez, Raúl Martínez, Francisco José Alfaro, José L. Sánchez, A low-cost strategy to provide full QoS support in Advanced Switching networks., Journal of Systems Architecture 53(7): 355-368 (2007)
Alejandro Martínez-Vicente, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, Jose Flich, Francisco J. Quiles, José Duato, Integrated QoS Provision and Congestion Management for Interconnection Networks., Euro-Par 2007: 837-847
Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Analysis of static and dynamic energy consumption in NUCA caches: initial results, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Alessandro Dalla Torre, Martino Ruggiero, Luca Benini, MP-Queue: an Efficient Communication Library for Embedded Streaming Multimedia Platforms., ESTImedia 2007: 105-110
Alessandro G. Di Nuovo, Maurizio Palesi, Vincenzo Catania, Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems., FUZZ-IEEE 2007: 1-6
Alessandro G. Di Nuovo, Vincenzo Catania, On External Measures for Validation of Fuzzy Partitions., IFSA (1) 2007: 491-501
Alex E. Susu, Michele Magno, Andrea Acquaviva, David Atienza, Giovanni De Micheli, Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation., T. HiPEAC 1: 341-360 (2007)
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Using fine grain multithreading for energy efficient computing., PPOPP 2007: 259-269
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gregory Shklover, Code Compilation for an Explicitly Parallel Register-Sharing Architecture., ICPP 2007: 58
Alex Villazón, Malik Junaid, Mumtaz Siddiqui, Thomas Fahringer, Applying patterns for porting complex workflows onto the Grid., CoreGRID 2007: 265-275
Alexander Sayenko, Olli Alanen, Timo Hämäläinen, Adaptive Contention Resolution for VoIP Services in the IEEE 802.16 Networks., WOWMOM 2007: 1-7
Alexander Sayenko, Olli Alanen, Timo Hämäläinen, On Contention Resolution Parameters for the IEEE 802.16 Base Station., GLOBECOM 2007: 4957-4962
Alexandros Stamatakis, Filip Blagojevic, Dimitrios S. Nikolopoulos, Christos D. Antonopoulos, Exploring New Search Algorithms and Hardware for Phylogenetics: RAxML Meets the IBM Cell., VLSI Signal Processing 48(3): 271-286 (2007)
Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich, Efficient event-driven simulation of parallel processor architectures., SCOPES 2007: 71-80
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement, Modeling of Interconnection Networks in Massively Parallel Processor Architectures., ARCS 2007: 268-282
Alfredo Remón, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Parallel Solution of Band Linear Systems in Model Reduction., PPAM 2007: 678-687
Alfredo Remón, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, The Implementation of BLAS for Band Matrices., PPAM 2007: 668-677
Ali Ahmadinia, Christophe Bobda, Sandor P. Fekete, Jurgen Teich, Jan C. van der Veen, Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices, IEEE Transactions on Computers , Volume 56 Issue 5, IEEE Computer Society, May 2007
Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha, Transactional programming in a multi-core environment., PPOPP 2007: 272
Ali-Reza Adl-Tabatabai, David Dice, Maurice Herlihy, Nir Shavit, Christos Kozyrakis, Christoph von Praun, Michael Scott, Potential show-stoppers for transactional synchronization., PPOPP 2007: 55
Aliaksei Kerhet, Francesco Leonardi, Andrea Boni, Paolo Lombardo, Michele Magno, Luca Benini, Distributed video surveillance using hardware-friendly sparse large margin classifiers., AVSS 2007: 87-92
Aliaksei Kerhet, Michele Magno, Francesco Leonardi, Andrea Boni, Luca Benini, A low-power wireless video sensor node for distributed object detection., J. Real-Time Image Processing 2(4): 331-342 (2007)
Alice Miller, Muffy Calder, Alastair F. Donaldson, A template-based approach for the generation of abstractable and reducible models of featured networks., Computer Networks 51(2): 439-455 (2007)
Alicia Asín Pérez, Darío Suárez Gracia, Victor Viñals Yúfera, A proposal to introduce power and energy notions in computer architecture laboratories, WCAE '07: Proceedings of the 2007 workshop on Computer architecture education, ACM, June 2007
Amedeo Cesta, Gabriella Cortellessa, Michel Denis, Alessandro Donati, Simone Fratini, Angelo Oddi, Nicola Policella, Erhard Rabenau, Jonathan Schulster, Mexar2: AI Solves Mission Planner Problems., IEEE Intelligent Systems 22(4): 12-19 (2007)
Amit D. Lakhani, Erica Y. Yang, Brian Matthews, Ian Johnson, Syed Naqvi, Gheorghe Cosmin Silaghi, Threat Analysis and Attacks on XtreemOS: a Grid-enabled Operating System., CoreGRID 2007: 53-62
Amund Kvalbein, Olav Lysne, How can multi-topology routing be used for intradomain traffic engineering?, INM '07: Proceedings of the 2007 SIGCOMM workshop on Internet network management, ACM, August 2007
Ana Bosque, Pablo Ibañez, Víctor Viñals, Per Stenström, Jose M. Llabería, Characterization of Apache web server with Specweb2005, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Ana Lucia Varbanescu, Henk J. Sips, Kenneth A. Ross, Qiang Liu, Lurng-Kuo Liu, Apostol Natsev, John R. Smith, An Effective Strategy for Porting C++ Applications on Cell., ICPP 2007: 59
Anastasios Gounaris, Carmela Comito, Rizos Sakellariou, Domenico Talia, A Service-Oriented System to Support Data Integration on Data Grids., CCGRID 2007: 627-635
Anastasios Gounaris, Christos Yfoulis, Rizos Sakellariou, Marios D. Dikaiakos, Self-optimizing block transfer in web service grids., WIDM 2007: 49-56
Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven, Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors., T. HiPEAC 1: 279-297 (2007)
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Joerg Henkel, Instruction trace compression for rapid instruction cache simulation, DATE '07: Proceedings of the conference on Design, automation and test in Europe, EDA Consortium, April 2007
Andrés Marín López, Daniel Díaz Sánchez, Florina Almenárez, Carlos García Rubio, Celeste Campo, Smart card-based agents for fair non-repudiation, Computer Networks: The International Journal of Computer and Telecommunications Networking , Volume 51 Issue 9, Elsevier North-Holland, Inc., June 2007
André C. Nácul, Francesco Regazzoni, Marcello Lajolo, Hardware scheduling support in SMP architectures., DATE 2007: 642-647
Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology., ACM Great Lakes Symposium on VLSI 2007: 501-504
Andrea Marongiu, Luca Benini, Mahmut T. Kandemir, Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms., CASES 2007: 145-149
Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis, Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip, IEEE Transactions on Very Large Scale Integration Systems, vol. 15, no. 8, pp. 971-975, August 2007.
Andreas Hansson, Kees Goossens, Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases., NOCS 2007: 233-242
Andreas Hansson, Martijn Coenen, Kees Goossens, Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip., DATE 2007: 954-959
Andreas Hansson, Martijn Coenen, Kees Goossens, Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip., CODES+ISSS 2007: 149-154
Andreas Merentitis, Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, Selecting Power-Optimal SBST Routines for On-Line Processor Testing, IEEE European Test Symposium (ETS 2007), Freiburg, Germany, May 2007.
Andrei Terechko, Henk Corporaal, Inter-cluster communication in VLIW architectures., TACO 4(2): (2007)
Andres Mejia, Jose Flich, José Duato, Sven-Arne Reinemo, Tor Skeie, Boosting Ethernet Performance by Segment-Based Routing., PDP 2007: 55-62
Andy Georges, Dries Buytaert, Lieven Eeckhout, Adding rigorous statistics to the Java benchmarker's toolbox., OOPSLA Companion 2007: 793-794
Andy Georges, Dries Buytaert, Lieven Eeckhout, Statistically rigorous java performance evaluation., OOPSLA 2007: 57-76
Angeles G. Navarro, Francisco Corbera, Adrian Tineo, Rafael Asenjo, Emilio L. Zapata, Detecting loop-carried dependences in programs with dynamic data structures., J. Parallel Distrib. Comput. 67(1): 47-62 (2007)
Angelo Duarte, Dolores Rexachs, Emilio Luque, Functional Tests of the RADIC Fault Tolerance Architecture., PDP 2007: 278-287
Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto, A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis., ISVLSI 2007: 92-97
Ani Anciaux-Sedrakian, Rosa M. Badia, Raúl Sirvent, Josep M. Pérez, Thilo Kielmann, André Merzky, GRID superscalar and job mapping on the reliable grid resources., CoreGRID Workshop - Making Grids Work 2007: 77-88
Ani Nahapetian, Paolo Lombardo, Andrea Acquaviva, Luca Benini, Majid Sarrafzadeh, Dynamic reconfiguration in sensor networks with regenerative energy sources., DATE 2007: 1054-1059
Anna Antola, Marco Castagna, Pamela Gotti, Marco D. Santambrogio, Evolvable Hardware: A Functional Level Evolution Framework Based on ImpulseC., ERSA 2007: 216-219
Anna Morajko, Paola Caymes-Scutari, Tomàs Margalef, Emilio Luque, MATE: Monitoring Analysis and Tuning Environment for parallel/distributed applications., Concurrency and Computation: Practice and Experience 19(11): 1517-1531 (2007)
Anna Morajko, Tomàs Margalef, Emilio Luque, Design and implementation of a dynamic tuning environment., J. Parallel Distrib. Comput. 67(4): 474-490 (2007)
Antoine Fraboulet, Guillaume Chelius, Eric Fleury, Worldsens: development and prototyping tools for application specific wireless sensors networks., IPSN 2007: 176-185
Antoine Fraboulet, Tanguy Risset, Master Interface for On-chip Hardware Accelerator Burst Communications., VLSI Signal Processing 49(1): 73-85 (2007)
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset, Long-Range Dependence and On-chip Processor Traffic., ReCoSoC 2007: 111-120
Anton Lokhmotov, Alan Mycroft, Optimal bit-reversal using vector permutations., SPAA 2007: 198-199
Anton Lokhmotov, Alan Mycroft, Andrew Richards, Delayed Side-Effects Ease Multi-core Programming., Euro-Par 2007: 641-650
Anton Lokhmotov, Benedict R. Gaster, Alan Mycroft, Neil Hickey, David Stuttard, Revisiting SIMD Programming., LCPC 2007: 32-46
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, An Interrupt Controller for FPGA-based Multiprocessors., ICSAMOS 2007: 82-87
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb., ISVLSI 2007: 449-450
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs., ISVLSI 2007: 331-336
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, A Self-Reconfigurable Implementation of the JPEG Encoder., ASAP 2007: 24-29
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, A design kit for a fully working shared memory multiprocessor on FPGA., ACM Great Lakes Symposium on VLSI 2007: 219-222
Antonio Flores, Juan L. Aragón, Manuel E. Acacio, Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network., HiPC 2007: 133-146
Antonio Flores, Juan L. Aragón, Manuel E. Acacio, Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures., AINA Workshops (1) 2007: 752-757
Antonio J. Dorta, José M. Badía, Enrique S. Quintana-Ortí, Francisco de Sande, Parallelizing Dense Linear Algebra Operations with Task Queues in., PVM/MPI 2007: 89-96
Antonio Ortiz, Teresa Olivares, Luis Orozco-Barbosa, A heterogeneous role-based sensor network., PM2HW2N 2007: 61-67
Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini, NoC Design and Implementation in 65nm Technology., NOCS 2007: 273-282
Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini, Bringing NoCs to 65 nm., IEEE Micro 27(5): 75-85 (2007)
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, A Complete Topology Management Mechanism for the Advanced Switching Interconnect Technology., ISCC 2007: 893-899
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, Implementing the Advanced Switching Fabric Discovery Process., IPDPS 2007: 1-8
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, Tor Skeie, A distributed approach to handle topological changes in advanced switching., PM2HW2N 2007: 37-44
Antonis Papadogiannakis, Demetres Antoniades, Michalis Polychronakis, Evangelos P. Markatos, Improving the Performance of Passive Network Monitoring Applications using Locality Buffering., MASCOTS 2007: 151-157
Antony Chazapis, Georgios Tsoukalas, Georgios Verigakis, Kornilios Kourtis, Aristidis Sotiropoulos, Nectarios Koziris, Global-scale peer-to-peer file services with DFS., GRID 2007: 251-258
Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen, IP Integration Overhead Analysis in System-on-Chip Video Encoder., DDECS 2007: 333-336
Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Design space exploration of partially re-configurable embedded processors., DATE 2007: 319-324
Anupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors., IEEE International Workshop on Rapid System Prototyping 2007: 189-194
Arash Ahmadi, Mark Zwolinski, Multiple-Width Bus Partitioning Approach to Datapath Synthesis., ISCAS 2007: 2994-2997
Ari Kulmala, Erno Salminen, Timo D. Hämäläinen, Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder., DDECS 2007: 105-110
Ari Kulmala, Erno Salminen, Timo D. Hämäläinen, Evaluating Large System-on-Chip on Multi-FPGA Platform., SAMOS 2007: 179-189
Arnab Banerjee, Robert D. Mullins, Simon W. Moore, A Power and Energy Exploration of Network-on-Chip Architectures., NOCS 2007: 163-172
Arnaud Verdant, Antoine Dupret, Hervé Mathias, Patrick Villard, Lionel Lacassagne, Adaptive Multiresolution for Low Power CMOS Image Sensor., ICIP (5) 2007: 185-188
Arun Ramakrishnan, Gurmeet Singh, Henan Zhao, Ewa Deelman, Rizos Sakellariou, Karan Vahi, Kent Blackburn, David Meyers, Michael Samidi, Scheduling Data-IntensiveWorkflows onto Storage-Constrained Distributed Resources., CCGRID 2007: 401-409
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis, SIMD Vectorization of Histogram Functions., ASAP 2007: 174-179
Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing., DATE 2007: 1544-1549
Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Timing-driven row-based power gating., ISLPED 2007: 104-109
Audun Fosselie Hansen, Olav Lysne, Tarik Cicic, Stein Gjessing, Fast Proactive Recovery from Concurrent Failures., ICC 2007: 115-122
Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, José Duato, Handling Topology Changes in InfiniBand., IEEE Trans. Parallel Distrib. Syst. 18(2): 172-185 (2007)
Austen McDonald, Brian D. Carlstrom, JaeWoong Chung, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun, Transactional Memory: The Hardware-Software Interface., IEEE Micro 27(1): 67-76 (2007)
Avi Mendelson, Current trends in computer architectures: multi-cores many-cores and special-cores., ICS 2007: 1
Avi Nissimov, Dror G. Feitelson, Probabilistic Backfilling., JSSPP 2007: 102-115
Avraam N. Chimaris, George A. Papadopoulos, Implementing a generic component-based framework for telecontrol applications, Software—Practice & Experience , Volume 37 Issue 10, John Wiley & Sons, Inc., August 2007
Ayelet Israeli, Dror G. Feitelson, Success of Open Source Projects: Patterns of Downloads and Releases with Time., SwSTE 2007: 87-94
Ayose Falcón, Paolo Faraboschi, Daniel Ortega, Combining Simulation and Virtualization through Dynamic Sampling., ISPASS 2007: 72-83
B. de la Ossa, J. A. Gil, J. Sahuquillo, A. Pont, Web prefetch performance evaluation in a real environment, LANC '07: Proceedings of the 4th international IFIP/ACM Latin American conference on Networking, ACM, October 2007
B. de la Ossa, José A. Gil, Julio Sahuquillo, Ana Pont, Delfos: the Oracle to Predict NextWeb User's Accesses., AINA 2007: 679-686
B. Prados-Suárez, J. Chamorro-Martínez, D. Sánchez, J. Abad, Region-based fit of color homogeneity measures for fuzzy image segmentation, Fuzzy Sets and Systems , Volume 158 Issue 3, Elsevier North-Holland, Inc., February 2007
Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek, Communication-Centric SoC Debug Using Transactions., European Test Symposium 2007: 69-76
Bas Breijer, Filipa Duarte, Stephan Wong, An OCM based shared Memory controller for Virtex 4., FPL 2007: 692-696
Beatriz Otero, José M. Cela, A Workload Distribution Pattern for Grid Environments., GCA 2007: 56-62
Behnaz Pourebrahimi, Koen Bertels, Fair access to scarce resources in ad-hoc grids using an economic-based approach., MGC 2007: 8
Behnaz Pourebrahimi, Koen Bertels, Stamatis Vassiliadis, Luc Onana Alima, A Dynamic Pricing and Bidding Strategy for Autonomous Agents in Grids., AP2PC 2007: 55-71
Behnaz Pourebrahimi, S. Arash Ostadzadeh, Koen Bertels, Resource Allocation in Market-based Grids Using a History-based Pricing Mechanism., SCSS (1) 2007: 97-100
Ben Cope, Peter Y. K. Cheung, Wayne Luk, Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective., ASAP 2007: 308-313
Benjamin Satzger, Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer, A new adaptive accrual failure detector for dependable distributed systems., SAC 2007: 551-555
Benjamin Satzger, Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer, A new adaptive accrual failure detector for dependable distributed systems, SAC '07: Proceedings of the 2007 ACM symposium on Applied computing, ACM, March 2007
Benjamin Satzger, Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer, Variations and Evaluations of an Adaptive Accrual Failure Detector to Enable Self-healing Properties in Distributed Systems., ARCS 2007: 171-184
Benny Akesson, Kees Goossens, Markus Ringhofer, Predator: a predictable SDRAM memory controller., CODES+ISSS 2007: 251-256
Bertrand Anckaert, Mariusz H. Jakubowski, Ramarathnam Venkatesan, Koen De Bosschere, Run-Time Randomization to Mitigate Tampering., IWSEC 2007: 153-168
Bertrand Anckaert, Matias Madou, Bjorn De Sutter, Bruno De Bus, Koen De Bosschere, Bart Preneel, Program obfuscation: a quantitative approach., QoP 2007: 15-20
Bhuvaneswari Arunachalan, Janet Light, Ian Watson, Mobile Agent Based Messaging Mechanism for Emergency Medical Data Transmission Over Cellular Networks., COMSWARE 2007
Bill Lin, Isaac Keslassy, Frame-aggregated concurrent matching switch., ANCS 2007: 107-116
Biplav Srivastava, Tuan A. Nguyen, Alfonso Gerevini, Subbarao Kambhampati, Minh Binh Do, Ivan Serina, Domain independent approaches for finding diverse plans, IJCAI'07: Proceedings of the 20th international joint conference on Artifical intelligence, Morgan Kaufmann Publishers Inc., January 2007
Björn Nilsson, Lars Bengtsson, Per-Arne Wiberg, Bertil Svensson, Protocols for Active RFID - The Energy Consumption Aspect., SIES 2007: 41-48
Bjorn De Sutter, Ludo Van Put, Dominique Chanet, Bruno De Bus, Koen De Bosschere, Link-time compaction and optimization of ARM executables., ACM Trans. Embedded Comput. Syst. 6(1): (2007)
Bjorn De Sutter, Ludo Van Put, Koen De Bosschere, A practical interprocedural dominance algorithm., ACM Trans. Program. Lang. Syst. 29(4): (2007)
Blas Cuesta, Antonio Robles, José Duato, An Effective Starvation Avoidance Mechanism to Enhance the Token Coherence Protocol., PDP 2007: 47-54
Bratislav Predic, Dejan Rančic, Dragan Stojanovic, Aleksandar Milosavljevic, Automatic vehicle location in public bus transportation system, ICCOMP'07: Proceedings of the 11th WSEAS International Conference on Computers, World Scientific and Engineering Academy and Society (WSEAS), July 2007
Brian D. Carlstrom, Austen McDonald, Michael Carbin, Christos Kozyrakis, Kunle Olukotun, Transactional collection classes., PPOPP 2007: 56-67
C. Arbelo, Andreas Kanstein, Sebastián López, José Francisco López, Mladen Berekovic, Roberto Sarmiento, Jean-Yves Mignolet, Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter., DATE 2007: 177-182
C. P. Ravikumar, Jari Nurmi, Conference Reports., IEEE Design & Test of Computers 24(2): 202-203 (2007)
Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy, Synthesis of Multimode digital signal processing systems., AHS 2007: 318-325
Cagkan Erbas, Andy D. Pimentel, Mark Thompson, Simon Polstra, A framework for system-level modeling and simulation of embedded systems architectures, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Cagkan Erbas, Andy D. Pimentel, Selin Cerav-Erbas, Static priority scheduling of event-triggered real-time embedded systems., Formal Methods in System Design 30(1): 29-47 (2007)
Carles Pairot Gavalda, Pedro Garcia Lopez, Ruben Mondejar Andreu, Deploying Wide-Area Applications Is a Snap, IEEE Internet Computing , Volume 11 Issue 2, IEEE Educational Activities Department, March 2007
Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis, A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size., SAMOS 2007: 283-293
Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis, A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions., ARC 2007: 130-141
Carlos Dominguez, Houcine Hassan, Alfons Crespo, Real-Time Embedded Architecture for Pervasive Robots, IPC '07: Proceedings of the The 2007 International Conference on Intelligent Pervasive Computing, IEEE Computer Society, October 2007
Carlos García, Manuel Prieto, Francisco Tirado, Multigrid Smoothers on Multicore Architectures., PARCO 2007: 279-286
Carlos Morra, João M. P. Cardoso, Jürgen Becker, Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements., IPDPS 2007: 1-8
Carmen Martínez, Ramón Beivide, Ernst M. Gabidulin, Perfect Codes for Metrics Induced by Circulant Graphs., IEEE Transactions on Information Theory 53(9): 3042-3052 (2007)
Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy, A hardware/software framework for supporting transactional memory in a MPSoC environment, SIGARCH Computer Architecture News , Volume 35 Issue 1, ACM, March 2007
Chang-Hua Wu, Weihua Sheng, Ying Zhang, Mobile Sensor Networks Self Localization based on Multi-dimensional Scaling., ICRA 2007: 4038-4043
Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Grasso Bronson, Jared Casper, Christos Kozyrakis, Kunle Olukotun, An effective hybrid transactional memory system with strong isolation guarantees., ISCA 2007: 69-80
Chris Bleakley, Tom Clerckx, Harald Devos, Matthias Grumer, Alex Janek, Ulrich Kremer, Christian W. Probst, Phillip Stanley-Marbell, Christian Steger, Vasanth Venkatachalam, Manuel Wendt, 07041 Working Group - Towards Interfaces for Integrated Performance and Power Analysis and Simulation., Power-aware Computing Systems 2007
Christian Haubelt, Joachim Falk, Joachim Keinert, Thomas Schlichter, Martin Streubühr, Andreas Deyhle, Andreas Hadert, Jürgen Teich, A SystemC-based design methodology for digital signal processing systems, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Christian Pilato, Gianluca Palermo, Antonino Tumeo, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi, Fitness inheritance in evolutionary and multi-objective high-level synthesis., IEEE Congress on Evolutionary Computation 2007: 3459-3466
Christian W. Probst, Ulrich Kremer, Luca Benini, Peter Schelkens, Power-aware computing systems., IJES 3(1/2): 3-7 (2007)
Christine Rochange, WCET 2007 Abstracts Collection - 7th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis., WCET 2007
Christine Rochange, 7th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis Pisa Italy July 3 2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI) Schloss Dagstuhl Germany 2007
Christof Fetzer, Pascal Felber, Improving Program Correctness with Atomic Exception Handling., J. UCS 13(8): 1047-1072 (2007)
Christophe Alias, Fabrice Baray, Alain Darte, Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose., LCTES 2007: 73-82
Christophe Dubach, John Cavazos, Björn Franke, Grigori Fursin, Michael F. P. O'Boyle, Olivier Temam, Fast compiler optimisation evaluation using code-feature based performance prediction., Conf. Computing Frontiers 2007: 131-142
Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle, Microarchitectural Design Space Exploration Using an Architecture-Centric Approach., MICRO 2007: 262-271
Christophe Poucet, Stylianos Mamagkakis, David Atienza, Francky Catthoor, Systematic intermediate sequence removal for reduced memory accesses., SCOPES 2007: 51-60
Christos Baloukas, Lazaros Papadopoulos, Stylianos Mamagkakis, Dimitrios Soudris, Component Based Library Implementation of Abstract Data Types for Resource Management Customization of Embedded Systems., ESTImedia 2007: 99-104
Christos Koulamas, Aggeliki S. Prayati, George Papadopoulos, A framework for the implementation of adaptive streaming systems., WMuNeP 2007: 23-26
Christos-S Bouganis, Iosifina Pournara, Peter Y. K. Cheung, Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications., FPL 2007: 196-201
Clemens Moser, Davide Brunelli, Lothar Thiele, Luca Benini, Real-time scheduling for energy harvesting sensor nodes., Real-Time Systems 37(3): 233-260 (2007)
Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini, Adaptive power management in energy harvesting systems., DATE 2007: 773-778
Colby Ranger, Ramanan Raghuraman, Arun Penmetsa, Gary R. Bradski, Christos Kozyrakis, Evaluating MapReduce for Multi-core and Multiprocessor Systems., HPCA 2007: 13-24
Cosmin E. Oancea, Alan Mycroft, A Lightweight Model for Software Thread-Level Speculation (TLS)., PACT 2007: 419
Crispín Gómez Requena, Francisco Gilabert, María Engracia Gómez, Pedro López, José Duato, Deterministic versus Adaptive Routing in Fat-Trees., IPDPS 2007: 1-8
Crispín Gómez Requena, María Engracia Gómez, Pedro López, José Duato, An Efficient Fault-Tolerant Routing Methodology for Fat-Tree Interconnection Networks., ISPA 2007: 509-522
Cristiana Bolchini, Antonio Miele, Marco D. Santambrogio, TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs., DFT 2007: 87-95
Cristiana Bolchini, Carlo Curino, Elisa Quintarelli, Fabio A. Schreiber, Letizia Tanca, A data-oriented survey of context models., SIGMOD Record 36(4): 19-26 (2007)
Cristiana Bolchini, Carlo Curino, Giorgio Orsi, Elisa Quintarelli, Fabio A. Schreiber, Letizia Tanca, CADD: A Tool for Context Modeling and Data Tailoring., MDM 2007: 221-223
Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio, SEU mitigation for sram-based fpgas through dynamic partial reconfiguration., ACM Great Lakes Symposium on VLSI 2007: 55-60
Cristiana Bolchini, Elisa Quintarelli, Rosalba Rossato, Relational Data Tailoring Through View Composition., ER 2007: 149-164
Cristiana Bolchini, Elisa Quintarelli, Rosalba Rossato, Letizia Tanca, Using Context for the Extraction of Relational Views., CONTEXT 2007: 108-121
Cristiana Bolchini, Fabio A. Schreiber, Letizia Tanca, A methodology for a Very Small Data Base design., Inf. Syst. 32(1): 61-82 (2007)
Cristiana Bolchini, Fabio Salice, Marco D. Santambrogio, Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs., ERSA 2007: 199-202
Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) 26-28 September 2007 Rome Italy., IEEE Computer Society 2007
Cyprian Grassmann, Mathias Richter, Mirko Sauermann, Mapping the physical layer of radio standards to multiprocessor architectures., DATE 2007: 1412-1417
Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin, A design flow dedicated to multi-mode architectures for DSP applications., ICCAD 2007: 604-611
D. Gao, Y. Wang, H. Hindi, M. Do, Decompose Document Image Using Integer Linear Programming, ICDAR '07: Proceedings of the Ninth International Conference on Document Analysis and Recognition - Volume 01 , Volume 01, IEEE Computer Society, September 2007
Damien Sauveron, Constantinos Markantonakis, Angelos Bilas, Jean-Jacques Quisquater, Information Security Theory and Practices. Smart Cards Mobile and Ubiquitous Computing Systems First IFIP TC6 / WG 8.8 / WG 11.2 International Workshop WISTP 2007 Heraklion Crete Greece May 9-11 2007 Proceedings, Springer 2007
Dan Tsafrir, Keren Ouaknine, Dror G. Feitelson, Reducing Performance Evaluation Sensitivity and Variability by Input Shaking., MASCOTS 2007: 231-237
Dan Tsafrir, Yoav Etsion, Dror G. Feitelson, Backfilling Using System-Generated Predictions Rather than User Runtime Estimates., IEEE Trans. Parallel Distrib. Syst. 18(6): 789-803 (2007)
Dan Tsafrir, Yoav Etsion, Dror G. Feitelson, Secretly monopolizing the CPU without superuser privileges, SS'07: Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium, USENIX Association, August 2007
Daniel Díaz, Xoán C. Pardo, María J. Martín, Patricia González, Gabriel Rodríguez, CPPC-G: Fault-Tolerant Applications on the Grid., PPAM 2007: 852-859
Daniel Grund, Sebastian Hack, A Fast Cutting-Plane Algorithm for Optimal Coalescing., CC 2007: 111-125
Daniel Jiménez-González, Xavier Martorell, Alex Ramírez, Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications., ISPASS 2007: 210-219
Daniel Sanchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam, Implementing Signatures for Transactional Memory, MICRO '07: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, IEEE Computer Society, December 2007
David Atienza, Christos Baloukas, Lazaros Papadopoulos, Christophe Poucet, Stylianos Mamagkakis, José Ignacio Hidalgo, Francky Catthoor, Dimitrios Soudris, Juan Lanchares, Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation., SCOPES 2007: 31-40
David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, HW-SW emulation framework for temperature-aware design in MPSoCs., ACM Trans. Design Autom. Electr. Syst. 12(3): (2007)
David B. Thomas, Jacob A. Bower, Wayne Luk, Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations., ASAP 2007: 168-173
David B. Thomas, Wayne Luk, High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices., VLSI Signal Processing 47(1): 77-92 (2007)
David B. Thomas, Wayne Luk, Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
David B. Thomas, Wayne Luk, Michael Stumpf, Reconfigurable Hardware Acceleration of Canonical Graph Labelling., ARC 2007: 302-313
David B. Thomas, Wayne Luk, Philip Heng Wai Leong, John D. Villasenor, Gaussian random number generators., ACM Comput. Surv. 39(4): (2007)
David Chi-Leung Wong, Albert Cohen, María Jesús Garzarán, Christian Lengauer, Samuel P. Midkiff, 07361 Introduction -- Programming Models for Ubiquitous Parallelism., Programming Models for Ubiquitous Parallelism 2007
David Chi-Leung Wong, Albert Cohen, María Jesús Garzarán, Christian Lengauer, Samuel P. Midkiff, 07361 Abstracts Collection -- Programming Models for Ubiquitous Parallelism., Programming Models for Ubiquitous Parallelism 2007
David E. Singh, Alejandro Miguel, Félix García, Jesús Carretero, MASIPE: A Tool Based on Mobile Agents for Monitoring Parallel Environments., PPAM 2007: 870-879
David E. Singh, Florin Isaila, Alejandro Calderón, Félix García, Jesús Carretero, Multiple-Phase Collective I/O Technique for Improving Data Access Locality., PDP 2007: 534-542
David E. Singh, Florin Isaila, Juan Carlos Pichel, Jesús Carretero, A collective I/O implementation based on Inspector-Executor paradigm., PDPTA 2007: 683-689
David Gregg, Colm McSweeney, Ciarán McElroy, Fergal Connor, Séamas McGettrick, David Moloney, Dermot Geraghty, FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM Memory., FPL 2007: 786-791
David I. August, Jonathan Chang, Sylvain Girbal, Daniel Gracia Pérez, Gilles Mouchard, David A. Penry, Olivier Temam, Neil Vachharajani, UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development., Computer Architecture Letters 6(2): 45-48 (2007)
David J. Pearce, Matthew Webster, Robert Berry, Paul H. J. Kelly, Profiling with AspectJ., Softw. Pract. Exper. 37(7): 747-777 (2007)
David J. Pearce, Paul H. J. Kelly, Chris Hankin, Efficient field-sensitive pointer analysis of C., ACM Trans. Program. Lang. Syst. 30(1): (2007)
David R Lester, Topology in PVS: continuous mathematics with applications, AFM '07: Proceedings of the second workshop on Automated formal methods, ACM, November 2007
David Talby, Dror G. Feitelson, Adi Raveh, A Co-Plot analysis of logs and models of parallel workloads., ACM Trans. Model. Comput. Simul. 17(3): (2007)
David Verstraeten, Benjamin Schrauwen, Dirk Stroobandt, Adapting reservoir states to get Gaussian distributions., ESANN 2007: 495-500
David Verstraeten, Benjamin Schrauwen, Michiel D'Haene, Dirk Stroobandt, An experimental unification of reservoir computing methods., Neural Networks 20(3): 391-403 (2007)
Davide Bertozzi, Shashi Kumar, Maurizio Palesi, Networks-on-Chip, Networks-on-Chip, Hindawi Publishing Corporation, April 2007
Davy Genbrugge, Lieven Eeckhout, Statistical simulation of chip multiprocessors running multi-program workloads., ICCD 2007: 464-471
Demid Borodin, Ben H. H. Juurlink, Stamatis Vassiliadis, Instruction-Level Fault Tolerance Configurability., ICSAMOS 2007: 110-117
Denis Krivitski, Assaf Schuster, Ran Wolff, A Local Facility Location Algorithm for Large-scale Distributed Systems., J. Grid Comput. 5(4): 361-378 (2007)
Dennis Vermoen, Marc F. Witteman, Georgi Gaydadjiev, Reverse Engineering Java Card Applets Using Power Analysis., WISTP 2007: 138-149
Diego Andrade, Basilio B. Fraguela, Ramon Doallo, Precise automatable analytical modeling of the cache behavior of codes with indirections., TACO 4(3): (2007)
Diego Andrade, Manuel Arenaz, Basilio B. Fraguela, Juan Touriño, Ramon Doallo, Automated and accurate cache behavior analysis for codes with irregular access patterns., Concurrency and Computation: Practice and Experience 19(18): 2407-2423 (2007)
Diego R. Llanos, Review of “Grid Computing Security by Anirban Chakrabarti”, Springer, 2007, $69.95, ISBN: 3540444920, Queue , Volume 5 Issue 6, ACM, September 2007
Diego R. Llanos Ferraris, David Orden, Belén Palop, New Scheduling Strategies for Randomized Incremental Algorithms in the Context of Speculative Parallelization., IEEE Trans. Computers 56(6): 839-852 (2007)
Diego R. Martínez, Vicente Blanco Pérez, Marcos Boullón, José Carlos Cabaleiro, Casiano Rodríguez, Francisco F. Rivera, Software Tools for Performance Modeling of Parallel Programs., IPDPS 2007: 1-8
Diego R. Martínez, Vicente Blanco, Marcos Boullón, José Carlos Cabaleiro, Tomás F. Pena, Analytical Performance Models of Parallel Programs in Clusters., PARCO 2007: 99-106
Diego Sevilla, José M. García, Antonio F. Gómez-Skarmeta, Aspect-Oriented Programing Techniques to support Distribution Fault Tolerance and Load Balancing in the CORBA-LC Component Model., NCA 2007: 195-204
Diego Sevilla, José M. García, Antonio Gómez, Using AOP to Automatically Provide Distribution Fault Tolerance and Load Balancing to the CORBA-LC Component Model., PARCO 2007: 347-354
Dietmar Ebner, Florian Brandner, Andreas Krall, Leveraging Predicated Execution for Multimedia Processing., ESTImedia 2007: 85-90
Dirk Koch, Christian Haubelt, Jürgen Teich, Efficient hardware checkpointing: concepts overhead analysis and implementation., FPGA 2007: 188-196
Dirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich, Modeling and Synthesis of Hardware-Software Morphing., ISCAS 2007: 2746-2749
Dmitrijs Zaparanuks, Milan Jovic, Matthias Hauswirth, The potential of speculative class-loading., PPPJ 2007: 209-214
Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque, Adaptive L2 Cache for Chip Multiprocessors., Euro-Par Workshops 2007: 28-37
Dominique Chanet, Bjorn De Sutter, Bruno De Bus, Ludo Van Put, Koen De Bosschere, Automated reduction of the memory footprint of the Linux kernel., ACM Trans. Embedded Comput. Syst. 6(4): (2007)
Dragan Bosnacki, Alastair F. Donaldson, Michael Leuschel, Thierry Massart, Efficient Approximate Verification of Promela Models Via Symmetry Markers., ATVA 2007: 300-315
Dries Buytaert, Andy Georges, Michael Hind, Matthew Arnold, Lieven Eeckhout, Koen De Bosschere, Using hpm-sampling to drive dynamic compilation., OOPSLA 2007: 553-568
Dries Buytaert, Kris Venstermans, Lieven Eeckhout, Koen De Bosschere, GCH: Hints for Triggering Garbage Collections., T. HiPEAC 1: 74-94 (2007)
Dror Feitelson, Teaching TCP/IP Hands-On, IEEE Distributed Systems Online , Volume 8 Issue 11, IEEE Educational Activities Department, November 2007
Dror G. Feitelson, Asimov's Laws of Robotics Applied to Software., IEEE Software 24(4): 111-112 (2007)
Dror G. Feitelson, Introduction., Commun. ACM 50(11): 24-26 (2007)
Dror G. Feitelson, Locality of sampling and diversity in parallel system workloads., ICS 2007: 53-63
Dror G. Feitelson, Tokunbo O. S. Adeshiyan, Daniel Balasubramanian, Yoav Etsion, Gabor Madl, Esteban Osses, Sameer Singh, Karlkim Suwanmongkol, Minhui Xie, Stephen R. Schach, Fine-grain analysis of common coupling and its application to a Linux case study., Journal of Systems and Software 80(8): 1239-1255 (2007)
E. Moyano-Ávila, F. J. Quiles, L. Orozco-Barbosa, Development and evaluation of high-performance decorrelation algorithms for the nonalternating 3D wavelet transform, EURASIP Journal on Applied Signal Processing , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Ed F. Deprettere, Roger Woods, Ingrid Verbauwhede, Erwin A. de Kock, Transforming Signal Processing Applications into Parallel Implementations., EURASIP J. Adv. Sig. Proc. 2007: (2007)
Edi Shmueli, Dror G. Feitelson, Uncovering the Effect of System Performance on User Behavior from Traces of Parallel Systems., MASCOTS 2007: 274-280
Eduard Ayguadé, Gerald Baumgartner, J. Ramanujam, P. Sadayappan, Languages and Compilers for Parallel Computing: 18th International Workshop, LCPC 2005Hawthorne, NY, USA, October 20-22, 2005Revised Selected Papers (Lecture Notes in Computer Science), Languages and Compilers for Parallel Computing: 18th International Workshop, LCPC 2005Hawthorne, NY, USA, October 20-22, 2005Revised Selected Papers (Lecture Notes in Computer Science), Springer-Verlag New York, Inc., February 2007
Eduard Ayguadé, Matthias S. Müller, Special Issue on OpenMP - Guest Editors' Introduction., International Journal of Parallel Programming 35(4): 331-333 (2007)
Eduard Ayguadé, Matthias S. Müller, Introduction., International Journal of Parallel Programming 35(5): 437-439 (2007)
Eduard Ayguadé, Nawal Copty, Alejandro Duran, Jay Hoeflinger, Yuan Lin, Federico Massaioli, Ernesto Su, Priya Unnikrishnan, Guansong Zhang, A Proposal for Task Parallelism in OpenMP., IWOMP 2007: 1-12
Eduard Ayguade, Alejandro Duran, Jay Hoeflinger, Federico Massaioli, Xavier Teruel, An Experimental Evaluation of the New OpenMP Tasking Model., LCPC 2007: 63-77
Edwin Steiner, Andreas Krall, Christian Thalinger, Adaptive inlining and on-stack replacement in the CACAO virtual machine., PPPJ 2007: 221-226
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna, Configurable implementation of parallel memory based real-time video downscaler., Microprocessors and Microsystems 31(5): 283-292 (2007)
Eiko Yoneki, Pascal Felber, RDDS 2007 PC Co-chairs' Message., OTM Workshops (2) 2007: 1023
Eladio Gutierrez, Sergio Romero, Maria A. Trenas, Emilio L. Zapata, Simulation of quantum gates on a novel GPU architecture, ISTASC'07: Proceedings of the 7th Conference on 7th WSEAS International Conference on Systems Theory and Scientific Computation - Volume 7 , Volume 7, World Scientific and Engineering Academy and Society (WSEAS), August 2007
Electra Tamani, Paraskevas Evripidou, Combining Pragmatics and Intelligence in Semantic Web Service Discovery., OTM Workshops (2) 2007: 824-833
Electra Tamani, Paraskevas Evripidou, A Pragmatic Methodology to Web Service Discovery., ICWS 2007: 1168-1171
Eleftheria Katsiri, Jean Bacon, Alan Mycroft, SCAFOS: linking sensor data to context-aware applications using abstract events., Int. J. Pervasive Computing and Communications 3(4): 347-377 (2007)
Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis, The Molen compiler for reconfigurable processors., ACM Trans. Embedded Comput. Syst. 6(1): (2007)
Eli Pozniansky, Assaf Schuster, MultiRace: efficient on-the-fly data race detection in multithreaded C++ programs., Concurrency and Computation: Practice and Experience 19(3): 327-340 (2007)
Elias Athanasopoulos, Mema Roussopoulos, Kostas G. Anagnostakis, Evangelos P. Markatos, GAS: Overloading a File Sharing Network as an Anonymizing System., IWSEC 2007: 365-379
Elisabetta Farella, Luca Benini, Bruno Riccò, Andrea Acquaviva, MOCA: a low-power, low-cost motion capture system based on integrated accelerometers, Advances in Multimedia , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Emiliano Dolif, Michele Lombardi, Martino Ruggiero, Michela Milano, Luca Benini, Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip., EMSOFT 2007: 47-56
Emilio J. Padrón, Margarita Amor, Montserrat Bóo, Ramon Doallo, A Hierarchical Radiosity Method with Scene Distribution., PDP 2007: 134-138
Emre Özer, Alastair Reid, Stuart Biles, Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor., SBAC-PAD 2007: 37-44
Emre Özer, Stuart Biles, Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor., Asia-Pacific Computer Systems Architecture Conference 2007: 376-386
Encarnación Moyano-Ávila, Luis Orozco-Barbosa, Francisco J. Quiles, Entropy improvement by the Temporal-Window method for Alternating and Non-Alternating 3D wavelet transform over angiographies., Med. Biol. Engineering and Computing 45(11): 1121-1125 (2007)
Enno Lübbers, Marco Platzner, ReconOS: An RTOS supporting Hard- and Software Threads., FPL 2007: 441-446
Enric Jaén Villoldo, Joan Serrat-Fernandez, Emilio Luque, Improving Web Services Interoperability with Binding Extensions., ICWS 2007: 873-879
Enric Morancho, José María Llabería, Àngel Olivé, A comparison of two policies for issuing instructions speculatively., Journal of Systems Architecture 53(4): 170-183 (2007)
Enric Morancho, José María Llabería, Àngel Olivé, On reducing energy-consumption by late-inserting instructions into the issue queue., ISLPED 2007: 371-374
Enric Tejedor, Rosa M. Badia, Thilo Kielmann, Vladimir Getov, A Component-Based Integrated Toolkit., CoreGRID Workshop - Making Grids Work 2007: 139-151
Eric A. Antonelo, Benjamin Schrauwen, Xavier Dutoit, Dirk Stroobandt, Marnix Nuttin, Event Detection and Localization in Mobile Robot Navigation Using Reservoir Computing., ICANN (2) 2007: 660-669
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai, PROToFLEX: FPGA-accelerated Hybrid Functional Simulator., IPDPS 2007: 1-6
Erik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi, Parallel Computing with FPGAs - Concepts and Applications., PARCO 2007: 739-740
Ernie Chan, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn, Supermatrix out-of-order scheduling of matrix operations for SMP and multi-core architectures., SPAA 2007: 116-125
Ernie Chan, Field G. Van Zee, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn, Satisfying your dependencies with SuperMatrix., CLUSTER 2007: 91-99
Erno Salminen, Ari Kulmala, Timo D. Hämäläinen, On network-on-chip comparison., DSD 2007: 503-510
Erno Salminen, Tero Kangas, Vesa Lahtinen, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen, Benchmarking mesh and hierarchical bus networks in system-on-chip context., Journal of Systems Architecture 53(8): 477-488 (2007)
Ernst W. Biersack, Damiano Carra, Renato Lo Cigno, Pablo Rodriguez, Pascal Felber, Overlay architectures for file distribution: Fundamental performance analysis for homogeneous and heterogeneous cases., Computer Networks 51(3): 901-917 (2007)
Eun Jung Kim, Ki Hwan Yum, Chita R. Das, Mazin S. Yousif, José Duato, Exploring IBA Design Space for Improved Performance., IEEE Trans. Parallel Distrib. Syst. 18(4): 498-510 (2007)
Evangelos Koukis, Nectarios Koziris, Efficient Block Device Sharing over Myrinet with Memory Bypass., IPDPS 2007: 1-10
Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny, Routing table minimization for irregular mesh NoCs., DATE 2007: 942-947
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny, The Power of Priority: NoC Based Distributed Cache Coherency., NOCS 2007: 117-126
Ezequiel Herruzo, Emilio L. Zapata, Oscar G. Plata, Maximum and Sorted Cache Occupation Using Array Padding., ICSAMOS 2007: 178-185
Ezequiel Herruzo, Guillermo Ruíz, J. Ignacio Benavides, Oscar G. Plata, A New Parallel Sorting Algorithm based on Odd-Even Mergesort., PDP 2007: 18-22
Ezequiel Herruzo, J. Ignacio Benavides, Ricardo Quislant, Emilio L. Zapata, Oscar Plata, Simulating a Reconfigurable Cache System for Teaching Purposes, MSE '07: Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education, IEEE Computer Society, June 2007
Félix García Carballeira, Jesús Carretero, Alejandro Calderón, José Daniel García, Luis Miguel Sánchez, A global and parallel file system for grids., Future Generation Comp. Syst. 23(1): 116-122 (2007)
F. Castanedo, M. A. Patricio, J. Garcia, J. M. Molina, Bottom-up/top-down coordination in a multiagent visual sensor network, AVSS '07: Proceedings of the 2007 IEEE Conference on Advanced Video and Signal Based Surveillance - Volume 00 , Volume 00, IEEE Computer Society, September 2007
F. Cedo, Ana Cortés, Ana Ripoll, Miquel A. Senar, Emilio Luque, The Convergence of Realistic Distributed Load-Balancing Algorithms., Theory Comput. Syst. 41(4): 609-618 (2007)
F. Dahlgren, Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms, PATMOS '07: Proceedings of the 17th international workshop on Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Springer-Verlag, September 2007
F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera, Hardware support for adaptive tessellation of Bézier surfaces based on local tests., Journal of Systems Architecture 53(4): 233-250 (2007)
F. Lin, H. Ying, R. D. MacArthur, J. A. Cohn, D. Barth-Jones, L. R. Crane, Decision making in fuzzy discrete event systems, Information Sciences: an International Journal , Volume 177 Issue 18, Elsevier Science Inc., September 2007
Fabian Nowak, Rainer Buchty, Wolfgang Karl, A Run-time Reconfigurable Cache Architecture., PARCO 2007: 757-766
Fabio Garzia, Claudio Brunelli, Andrea Ferro, Jari Nurmi, Implementation of a 2D low-pass image filtering algorithm on a reconfigurable device., ReCoSoC 2007: 166-170
Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo, Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs., IESS 2007: 179-192
Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo, An Evolutionary Approach to Area-Time Optimization of FPGA designs., ICSAMOS 2007: 145-152
Fabrizio Petrini, Gordon Fossum, Juan Fernández, Ana Lucia Varbanescu, Michael Kistler, Michael Perrone, Multicore Surprises: Lessons Learned from Optimizing Sweep3D on the Cell Broadband Engine., IPDPS 2007: 1-10
Fadia Nemer, Hugues Cassé, Pascal Sainrat, Ali Awada, Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis., SIES 2007: 25-32
Faith Ellen, Panagiota Fatourou, Eric Ruppert, Time lower bounds for implementations of multi-writer snapshots., J. ACM 54(6): (2007)
Faith Ellen, Panagiota Fatourou, Eric Ruppert, The Space Complexity of Unbounded Timestamps., DISC 2007: 223-237
Farrukh Nadeem, Radu Prodan, Thomas Fahringer, Optimizing Performance of Automatic Training Phase for Application Performance Prediction in the Grid., HPCC 2007: 309-321
Faruk Bagci, Holger Schick, Jan Petzold, Wolfgang Trumler, Theo Ungerer, The reflective mobile agent paradigm implemented in a smart office environment., Personal and Ubiquitous Computing 11(1): 11-19 (2007)
Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli, Interactive presentation: Improving the fault tolerance of nanometric PLA designs., DATE 2007: 570-575
Federico Angiolini, Paolo Meloni, Salvatore Carta, Luigi Raffo, Luca Benini, A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs., IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 421-434 (2007)
Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy, R. Ramanarayanan, Balaji Vaidyanathan, A Process Scheduler-Based Approach to NoC Power Management., VLSI Design 2007: 77-82
Filip Blagojevic, Alexandros Stamatakis, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, RAxML-Cell: Parallel Phylogenetic Tree Inference on the Cell Broadband Engine., IPDPS 2007: 1-10
Filip Blagojevic, Dimitrios S. Nikolopoulos, Alexandros Stamatakis, Christos D. Antonopoulos, Dynamic multigrain parallelization on the cell broadband engine., PPOPP 2007: 90-100
Filip Blagojevic, Dimitrios S. Nikolopoulos, Alexandros Stamatakis, Christos D. Antonopoulos, Matthew Curtis-Maury, Runtime scheduling of dynamic parallelism on accelerator-based multi-core systems., Parallel Computing 33(10-11): 700-719 (2007)
Filipa Duarte, Stephan Wong, A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies., ASAP 2007: 397-402
Florent Bouchez, Alain Darte, Fabrice Rastello, On the complexity of spill everywhere under SSA form., LCTES 2007: 103-112
Florent Bouchez, Alain Darte, Fabrice Rastello, On the Complexity of Register Coalescing., CGO 2007: 102-114
Florian Brandner, Dietmar Ebner, Andreas Krall, Compiler generation from structural architecture descriptions., CASES 2007: 13-22
Florian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, MORPHEUS: Heterogeneous Reconfigurable Computing., FPL 2007: 409-414
Frédéric Gruau, Christine Eisenbeis, Programming self developing blob machines for spatial computing.., Computing Media and Languages for Space-Oriented Computation 2007
Francesc Giné, Francesc Solsona, Mauricio Hanzich, Porfidio Hernández, Emilio Luque, Cooperating CoScheduling: A Coscheduling Proposal Aimed at Non-Dedicated Heterogeneous NOWs., J. Comput. Sci. Technol. 22(5): 695-710 (2007)
Francesc Guim, Ivan Rodero, Julita Corbalán, Jesús Labarta, Ariel Oleksiak, Tomasz Kuczynski, Dawid Szejnfeld, Jarek Nabrzyski, Uniform job monitoring in the HPC-Europa project: data model API and services., IJWGS 3(3): 333-353 (2007)
Francesc Guim, Julita Corbalán, Jesús Labarta, Prediction f Based Models for Evaluating Backfilling Scheduling Policies., PDCAT 2007: 9-17
Francesc Guim, Julita Corbalán, Jesús Labarta, Modeling the Impact of Resource Sharing in Backfilling Policies using the Alvio Simulator., MASCOTS 2007: 145-150
Francesco D'Ascoli, Francesco Iozzi, Corrado Marino, Massimiliano Melani, Marco Tonarelli, Luca Fanucci, A. Giambastiani, A. Rocchi, Marco De Marinis, Low-g accelerometer fast prototyping for automotive applications., DATE 2007: 486-491
Francesco Poletti, Antonio Poggiali, Davide Bertozzi, Luca Benini, Pol Marchal, Mirko Loghi, Massimo Poncino, Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support., IEEE Trans. Computers 56(5): 606-621 (2007)
Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ie, A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies., ICSAMOS 2007: 209-214
Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar, Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits., DFT 2007: 508-516
Francisco Delicado, Pedro Cuenca, Luis Orozco-Barbosa, Hierarchical MPEG-4 video transmission over TDMA/TDD wireless LAN., Telecommunication Systems 36(1-3): 129-139 (2007)
Francisco Delicado, Pedro Cuenca, Luis Orozco-Barbosa, Developing a QoS framework for media streaming over TDMA/TDD wireless networks., IJWMC 2(2/3): 120-131 (2007)
Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero, On the Problem of Minimizing Workload Execution Time in SMT Processors., ICSAMOS 2007: 66-73
Francisco Javier Ridruejo Perez, Javier Navaridas, José Miguel-Alonso, Cruz Izu, Realistic Evaluation of Interconnection Network Performance at High Loads., PDCAT 2007: 97-104
Francisco Javier Ridruejo Perez, José Miguel-Alonso, Javier Navaridas, Concepts and components of full-system simulation of distributed memory parallel computers., HPDC 2007: 225-226
Francisco José Alfaro, José L. Sánchez, M. Menduiña, José Duato, A Formal Model to Manage the InfiniBand Arbitration Tables Providing QoS., IEEE Trans. Computers 56(8): 1024-1039 (2007)
Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev, Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array., ARC 2007: 1-13
Frederic Worm, Patrick Thiran, Paolo Ienne, Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs., ISQED 2007: 861-866
Frederik Vandeputte, Lieven Eeckhout, Koen De Bosschere, Exploiting program phase behavior for energy reduction on multi-configuration processors., Journal of Systems Architecture 53(8): 489-500 (2007)
Fredrik Dahlgren, Partial Continuous Functions and Admissible Domain Representations., J. Log. Comput. 17(6): 1063-1081 (2007)
Gabriel Rodríguez, Patricia González, María J. Martín, Juan Touriño, Enhancing Fault-Tolerance of Large-Scale MPI Scientific Applications., PaCT 2007: 153-161
Gala Yadgar, Michael Factor, Assaf Schuster, Karma: know-it-all replacement for a multilevel cache, FAST '07: Proceedings of the 5th USENIX conference on File and Storage Technologies, USENIX Association, February 2007
Gaspar Mora, Pedro Javier García, Jose Flich, José Duato, RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management., ICPP 2007: 74
George A. Constantinides, Special issue on Field-Programmable Technology., J. Real-Time Image Processing 2(4): 177-178 (2007)
George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis, Approaching Ideal NoC Latency with Pre-Configured Routes., NOCS 2007: 153-162
George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis, On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 2007), Rome, Italy, pp. 379-397, September 2007
Georges G. E. Gielen, Donatella Sciuto, Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design Automation and Test in Europe Conference]., IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 405-407 (2007)
Georgios I. Goumas, Nikolaos Drosinos, Vasileios Karakasis, Nectarios Koziris, Coarse-grain Parallel Execution for 2-dimensional PDE Problems., IPDPS 2007: 1-8
Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Cache replacement based on reuse-distance prediction., ICCD 2007: 245-250
Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras, Applying Decay to Reduce Dynamic Power in Set-Associative Caches., HiPEAC 2007: 38-53
Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Philip K. F. Hölzenspies, Marcel D. van de Burgwal, Paul M. Heysters, The Chameleon architecture for streaming DSP applications, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Gerardo Fernández-Escribano, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, Reducing Motion Estimation Complexity in MPEG-2 TO H.264 Transcoding., ICME 2007: 440-443
Gerardo Fernández-Escribano, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, A first approach to speeding-up the inter mode selection in MPEG-2/H.264 transcoders using machine learning., Multimedia Tools Appl. 35(2): 225-240 (2007)
Gerardo Fernández-Escribano, Jens Bialkowski, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, André Kaup, H.263 to H.264 Transconding using Data Mining., ICIP (4) 2007: 81-84
Giacomo Paci, Francesco Poletti, Luca Benini, Paul Marchal, Exploring temperature-aware design in low-power MPSoCs., IJES 3(1/2): 43-51 (2007)
Giacomo Paci, Paul Marchal, Luca Benini, Exploration of Low Power Adders for a SIMD Data Path., ASP-DAC 2007: 914-919
Gianluca Palermo, Cristina Silvano, Giovanni Mariani, Riccardo Locatelli, Marcello Coppola, Application-Specific Topology Design Customization for STNoC., DSD 2007: 547-550
Gianluca Palermo, Giovanni Mariani, Cristina Silvano, Riccardo Locatelli, Marcello Coppola, Mapping and Topology Customization Approaches for Application-Specific STNoC Designs., ASAP 2007: 61-68
Gianluca Palermo, Giovanni Mariani, Cristina Silvano, Riccardo Locatelli, Marcello Coppola, A topology design customization approach for STNoC, Nano-Net '07: Proceedings of the 2nd international conference on Nano-Networks, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), September 2007
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos, Sorter Based Permutation Units for Media-Enhanced Microprocessors., IEEE Trans. VLSI Syst. 15(6): 711-715 (2007)
Giovanni Agosta, Francesco Bruschi, Donatella Sciuto, An efficient cost-based canonical form for Boolean matching., ACM Great Lakes Symposium on VLSI 2007: 445-448
Giovanni Agosta, Francesco Bruschi, Gerardo Pelosi, Donatella Sciuto, A Unified Approach to Canonical Form-based Boolean Matching., DAC 2007: 841-846
Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto, A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip., DFT 2007: 132-141
Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Multi-Accuracy Power and Performance Transaction-Level Modeling., IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1830-1842 (2007)
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Efficient design space exploration for application specific systems-on-a-chip., Journal of Systems Architecture 53(10): 733-750 (2007)
Giuseppe Gentile, Massimo Rovini, Luca Fanucci, Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes., DSD 2007: 369-375
Gregorio Bernabé, Ricardo Fernández, Jose M. García, Manuel E. Acacio, José González, An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology, Parallel Computing , Volume 33 Issue 1, Elsevier Science Publishers B. V., February 2007
Gregorio Bernabé, Ricardo Fernández, José M. García, Manuel E. Acacio, José González, An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology., Parallel Computing 33(1): 54-72 (2007)
Grigori Fursin, Albert Cohen, Michael F. P. O'Boyle, Olivier Temam, Quick and Practical Run-Time Evaluation of Multiple Program Optimizations., T. HiPEAC 1: 34-53 (2007)
Grigori Fursin, John Cavazos, Michael F. P. O'Boyle, Olivier Temam, MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization., HiPEAC 2007: 245-260
Grzegorz Danilewicz, Wojciech Kabacinski, Marek Michalski, Mariusz Zal, Wide-Sense Nonblocking Multiplane Baseline Switching Networks Composed of d d Switches., ICC 2007: 6386-6391
Guillaume Chelius, Antoine Fraboulet, Eric Fleury, Worldsens: a fast and accurate development framework for sensor network applications., SAC 2007: 222-226
Guillermo L. Taboada, Carlos Teijeiro, Juan Touriño, High Performance Java Remote Method Invocation for Parallel Computing on Clusters., ISCC 2007: 233-239
Guillermo L. Taboada, Juan Touriño, Ramon Doallo, High Performance Java Sockets for Parallel Computing on Clusters., IPDPS 2007: 1-8
Gulay Yalcin, Oguz Ergin, Using Tag-Match Comparators for Detecting Soft Errors., Computer Architecture Letters 6(2): 53-56 (2007)
Gunnar Brataas, Jacqueline Floch, Romain Rouvoy, Pyrros Bratskas, George A. Papadopoulos, A basis for performance property prediction of ubiquitous self-adapting systems, ESSPE '07: International workshop on Engineering of software services for pervasive environments: in conjunction with the 6th ESEC/FSE joint meeting, ACM, September 2007
Gurmeet Singh, Karan Vahi, Arun Ramakrishnan, Gaurang Mehta, Ewa Deelman, Henan Zhao, Rizos Sakellariou, Kent Blackburn, Duncan Brown, Stephen Fairhurst, David Meyers, G. Bruce Berriman, John Good, Da, Optimizing workflow data footprint., Scientific Programming 15(4): 249-268 (2007)
Håkan Zeffer, Erik Hagersten, A case for low-complexity MP architectures., SC 2007: 19
Haakon Dybdahl, Per Stenström, Lasse Natvig, An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches, SIGARCH Computer Architecture News , Volume 35 Issue 4, ACM, September 2007
Haakon Dybdahl, Per Stenström, An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors., HPCA 2007: 2-12
Hadas Kogan, Isaac Keslassy, Optimal-Complexity Optical Router., INFOCOM 2007: 706-714
Hadas Kogan, Isaac Keslassy, Fundamental Complexity of Optical Systems., INFOCOM 2007: 2506-2510
Hadda Cherroun, Paul Feautrier, An Exact Resource Constrained-Scheduler using Graph Coloring technique., AICCSA 2007: 554-561
Hagit Attiya, Faith Ellen, Panagiota Fatourou, The complexity of updating multi-writer snapshot objects., PODC 2007: 318-319
Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli, Ozcan Ozturk, Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors., DAC 2007: 224-229
Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, ASIP architecture exploration for efficient IPSec encryption: A case study., ACM Trans. Embedded Comput. Syst. 6(2): (2007)
Hanno Scharwächter, Jonghee M. Yoon, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr, A code-generator generator for multi-output instructions., CODES+ISSS 2007: 131-136
Hans Vandierendonck, André Seznec, Fetch Gating Control Through Speculative Instruction Window Weighting., HiPEAC 2007: 120-135
Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat, By-passing the out-of-order execution pipeline to increase energy-efficiency., Conf. Computing Frontiers 2007: 97-104
Haohuan Fu, Oskar Mencer, Wayne Luk, Optimizing Logarithmic Arithmetic on FPGAs, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Harald Devos, Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt, Energy Scalability and the RESUME Scalable Video Codec., Power-aware Computing Systems 2007
Harald Devos, Kristof Beyls, Mark Christiaens, Jan M. Van Campenhout, Erik H. D'Hollander, Dirk Stroobandt, Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations., T. HiPEAC 1: 159-178 (2007)
Harald Servat, Cecilia Gonzalez, Xavier Aguilar, Daniel Cabrera, Daniel Jiménez-González, Drug Design on the Cell BroadBand Engine., PACT 2007: 425
Harald Servat, Cecilia Gonzalez, Xavier Aguilar, Daniel Cabrera, Daniel Jimenez, Drug Design on the Cell BroadBand Engine., PACT 2007: 425
Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, MTAP special issue on video transcoding to H.264., Multimedia Tools Appl. 35(2): 125-126 (2007)
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Austen McDonald, Chi Cao Minh, Woongki Baek, Christos Kozyrakis, Kunle Olukotun, A Scalable Non-blocking Approach to Transactional Memory., HPCA 2007: 97-108
Hector Pettenghi, Maria Jose Avedillo, Jose Maria Quintana, Non Return Mobile Logic Family, IEEE Proc. Int. Symp. on Circuits and Syst. (ISCAS07), pp. 125-128
Heikki Orsila, Tero Kangas, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen, Automated memory-aware application distribution for Multi-processor System-on-Chips., Journal of Systems Architecture 53(11): 795-815 (2007)
Heiko Falk, Peter Marwedel, Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems Nice France April 20 2007, SCOPES 2007
Heiner Giefers, Marco Platzner, A Many-core Implementation based on the Reconfigurable Mesh Model., FPL 2007: 41-46
Heinz Wörn, Uwe Brinkschulte, Echtzeitsysteme: Grundlagen, Funktionsweisen, Anwendungen (eXamen.press), Echtzeitsysteme: Grundlagen, Funktionsweisen, Anwendungen (eXamen.press), Springer-Verlag New York, Inc., January 2007
Hendrik Eeckhaut, Harald Devos, Dirk Stroobandt, The Energy Scalability of Wavelet-Based Scalable Video Decoding., PATMOS 2007: 363-372
Hendrik Eeckhaut, Harald Devos, Peter Lambert, Davy De Schrijver, Wim Van Lancker, Vincent Nollet, Prabhat Avasare, Tom Clerckx, Fabio Verdicchio, Mark Christiaens, Peter Schelkens, Rik Van de Walle, , Scalable Wavelet-Based Video: From Server to Hardware-Accelerated Client., IEEE Transactions on Multimedia 9(7): 1508-1519 (2007)
Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mark Christiaens, Dirk Stroobandt, FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder., SAMOS 2007: 169-178
Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt, Improving External Memory Access for Avalon Systems on Programmable Chips.., FPL 2007: 311-316
Henry Falconer, Paul H. J. Kelly, David M. Ingram, Michael R. Mellor, Tony Field, Olav Beckmann, A Declarative Framework for Analysis and Optimization., CC 2007: 218-232
Hildur Ólafsdóttir, Stéphanie Lanche, Tron A. Darvann, Nuno V. Hermann, Rasmus Larsen, Bjarne K. Ersbøll, Estanislao Oubel, Alejandro F. Frangi, Per Larsen, Chad A. Perlyn,, A Point-Wise Quantification of Asymmetry Using Deformation Fields: Application to the Study of the Crouzon Mouse Model., MICCAI (2) 2007: 452-459
Holger Blume, Georgi Gaydadjiev, C. John Glossner, Peter M. W. Knijnenburg, Proceedings of 2007 International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (IC-SAMOS 2007) Samos Greece July 16-19 2007, IEEE 2007
Hong Linh Truong, Schahram Dustdar, Thomas Fahringer, Performance metrics and ontologies for Grid workflows., Future Generation Comp. Syst. 23(6): 760-772 (2007)
Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier, Massively Parallel Processor Architectures: A Co-design Approach., ReCoSoC 2007: 61-68
Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich, Efficient control generation for mapping nested loop programs onto processor arrays., Journal of Systems Architecture 53(5-6): 300-309 (2007)
Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser, Model Transformations from a Data Parallel Formalism towards Synchronous Languages., FDL 2007: 255-260
Hugues Berry, Olivier Temam, Modeling self-developing biological neural networks., Neurocomputing 70(16-18): 2723-2734 (2007)
Humberto Calderon, Carlo Galuzzi, Georgi Gaydadjiev, Stamatis Vassiliadis, High-Bandwidth Address Generation Unit., SAMOS 2007: 251-262
Humberto Calderon, Georgi Gaydadjiev, Stamatis Vassiliadis, Reconfigurable Universal Adder., ASAP 2007: 186-191
Ian O'Connor, Faress Tissafi-Drissi, Frédéric Gaffiot, Joni Dambre, Michiel De Wilde, Jan Van Campenhout, D. Van Thourhout, Dirk Stroobandt, Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect., IEEE Trans. VLSI Syst. 15(8): 927-940 (2007)
Ian Watson, Chris C. Kirkham, Mikel Luján, A Study of a Transactional Parallel Routing Algorithm., PACT 2007: 388-398
Igor L. Markov, Louis Scheffer, Dirk Stroobandt, Special issue on System-Level Interconnect Prediction., Integration 40(4): 381 (2007)
Igor Loi, Federico Angiolini, Luca Benini, Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow, Nano-Net '07: Proceedings of the 2nd international conference on Nano-Networks, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), September 2007
Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli, Early wire characterization for predictable network-on-chip global interconnects., SLIP 2007: 57-64
Ilias Iliadis, Nikolaos Chrysos, Cyriel Minkenberg, Performance evaluation of the Data Vortex photonic switch., IEEE Journal on Selected Areas in Communications 25(S-6): 20-35 (2007)
Imran Rao, Nomica Imran, Salman Khan, Eui-nam Huh, TaeChoong Chung, Adaptive and Reconfigurable ResOurce Management for Wireless Sensors using Grid Technology., COMSWARE 2007
Ioannis Mavroidis, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman Problem., IEEE International Workshop on Rapid System Prototyping 2007: 41-47
Ioannis Mavroidis, Ioannis Papaefstathiou, Dionisios Pnevmatikatos, A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos, A buffered crossbar-based chip interconnection framework supporting quality of service., ACM Great Lakes Symposium on VLSI 2007: 90-95
Ioannis Papaefstathiou, Vassilis Papaefstathiou, Memory-Efficient 5D Packet Classification At 40 Gbps., INFOCOM 2007: 1370-1378
Ioannis Sarkas, Dimitrios Mavridis, Michail Papamichail, George Papadopoulos, Volterra Analysis Using Chebyshev Series., ISCAS 2007: 1931-1934
Iouliia Skliarova, Valery Sklyarov, Software/Configware Implementation of Combinatorial Algorithms., AICCSA 2007: 539-546
Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny, Access Regulation to Hot-Modules in Wormhole NoCs., NOCS 2007: 137-148
Ismo Hänninen, Jarmo Takala, Robust Adders Based on Quantum-Dot Cellular Automata., ASAP 2007: 391-396
Iván Díaz, Juan Touriño, Ramon Doallo, Towards Low-Latency Model-Oriented Distributed Systems Management., APNOMS 2007: 41-50
Ivan E. Villalon, Pedro Cuenca, Luis Orozco-Barbosa, Yongho Seok, Thierry Turletti, Cross-Layer Architecture for Adaptive Video Multicast Streaming Over Multirate Wireless LANs., IEEE Journal on Selected Areas in Communications 25(4): 699-711 (2007)
Ivan Pryanishnikov, Andreas Krall, R. Nigel Horspool, Compiler optimizations for processors with SIMD instructions., Softw. Pract. Exper. 37(1): 93-113 (2007)
Ivan Rodero, Francesc Guim, Julita Corbalán, Jesús Labarta, Design and Implementation of a General-Purpose API of Progress and Performance Indicators., PARCO 2007: 501-508
Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luca Benini, Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions., CODES+ISSS 2007: 217-226
Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson, Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology., T. HiPEAC 1: 239-258 (2007)
Izchak Sharfman, Assaf Schuster, Daniel Keren, Aggregate Threshold Queries in Sensor Networks., IPDPS 2007: 1-10
Izchak Sharfman, Assaf Schuster, Daniel Keren, A geometric approach to monitoring threshold functions over distributed data streams., ACM Trans. Database Syst. 32(4): (2007)
Jürgen Hofer, Thomas Fahringer, The Otho Toolkit - Synthesizing tailor-made scientific grid application wrapper services., Multiagent and Grid Systems 3(3): 281-298 (2007)
Jürgen Hofer, Thomas Fahringer, Grid Application Fault Diagnosis Using Wrapper Services and Machine Learning., ICSOC 2007: 233-244
Jürgen Teich, Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme)., it - Information Technology 49(3): 139- (2007)
Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet, A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation., ERSA 2007: 14-24
J. Gómez, Large vertex symmetric digraphs, Networks , Volume 50 Issue 4, Wiley-Interscience, December 2007
J. L. Martínez, Warnakulasuriya Anil Chandana Fernando, W. A. Rajitha Jayaruwan Weerakkody, J. Oliver, O. López, M. Martinez, M. Pérez, Pedro Cuenca, Francisco J. Quiles, Low-Complexity TTCM Based Distributed Video Coding Architecture., PSIVT 2007: 841-852
J. R. Cózar, N. Guil, J. M. González-Linares, E. L. Zapata, E. Izquierdo, Logotype detection to support semantic-based video annotation, Image Communication , Volume 22 Issue 7-8, Elsevier Science Inc., August 2007
Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis, Comparing memory systems for chip multiprocessors., ISCA 2007: 358-368
Jadwiga Indulska, Jianhua Ma, Laurence Tianruo Yang, Theo Ungerer, Jiannong Cao, Ubiquitous Intelligence and Computing 4th International Conference UIC 2007 Hong Kong China July 11-13 2007 Proceedings, Springer 2007
Jae Young Hur, Stephan Wong, Stamatis Vassiliadis, Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs., ARC 2007: 49-60
Jae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis, Customizing Reconfigurable On-Chip Crossbar Scheduler., ASAP 2007: 210-215
Jae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis, Systematic Customization of On-Chip Crossbar Interconnects., ARC 2007: 61-72
Jairo Balart, Marc González, Xavier Martorell, Eduard Ayguadé, Zehra Sura, Tong Chen, Tao Zhang, Kevin O'Brien, Kathryn M. O'Brien, A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor., LCPC 2007: 125-140
Jan Willem van den Brand, Calin Ciordas, Kees Goossens, Twan Basten, Congestion-controlled best-effort communication for networks-on-chip., DATE 2007: 948-953
Jan-David Mol, Dick H. J. Epema, Henk J. Sips, The Orchard Algorithm: Building Multicast Trees for P2P Video Multicasting Without Free-Riding., IEEE Transactions on Multimedia 9(8): 1593-1604 (2007)
Jangwoo Kim, Jared C. Smolens, Babak Falsafi, James C. Hoe, PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers., PRDC 2007: 298-305
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe, Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding., MICRO 2007: 197-209
Jari Heikkinen, Jarmo Takala, Effects of program compression., Journal of Systems Architecture 53(10): 679-688 (2007)
Jarmo Takala, Shuvra S. Bhattacharyya, Gang Qu, Editorial: embedded digital signal processing systems, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Jarmo Takala, Timo D. Hämäläinen, Andy D. Pimentel, Stamatis Vassiliadis, Editorial., Journal of Systems Architecture 53(8): 465 (2007)
Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala, Parallel Memory Architecture for TTA Processor., SAMOS 2007: 273-282
Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, Fuse: A Technique to Anticipate Failures due to Degradation in ALUs., IOLTS 2007: 15-22
Javed Absar, Min Li, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Arnout Vandecappelle, Francky Catthoor, Locality optimization in wireless applications., CODES+ISSS 2007: 125-130
Javier Navaridas, Francisco Javier Ridruejo Perez, José Miguel-Alonso, Evaluation of Interconnection Networks Using Full-System Simulators: Lessons Learned., Annual Simulation Symposium 2007: 155-162
Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero, FAME: FAirly MEasuring Multithreaded Architectures., PACT 2007: 305-316
Jay L. T. Cornwall, Paul H. J. Kelly, Phil Parsonage, Bruno Nicoletti, Explicit Dependence Metadata in an Active Visual Effects Library., LCPC 2007: 172-186
Jean Christophe Beyler, Philippe Clauss, Performance driven data cache prefetching in a dynamic software optimization system., ICS 2007: 202-209
Jens Gladigau, Christian Haubelt, Bernhard Niemann, Jürgen Teich, Mapping Actor-Oriented Models to TLM Architectures., FDL 2007: 128-133
Jens Knoop, George C. Necula, Wolf Zimmermann, Preface., Electr. Notes Theor. Comput. Sci. 176(3): 1-2 (2007)
Jeremy Singer, Gavin Brown, Ian Watson, John Cavazos, Intelligent selection of application-specific garbage collectors., ISMM 2007: 91-102
Jeremy Singer, Gavin Brown, Mikel Luján, Ian Watson, Towards intelligent analysis techniques for object pretenuring., PPPJ 2007: 203-208
Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero, Microarchitectural Support for Speculative Register Renaming., IPDPS 2007: 1-10
Jesús Delicado, Francisco Delicado, Luis Orozco-Barbosa, Study of the IEEE 802.16 Contention-based Request Mechanism., PWC 2007: 87-98
Jialin Dou, Marcelo Cintra, A compiler cost model for speculative parallelization, Transactions on Architecture and Code Optimization (TACO) , Volume 4 Issue 2, ACM, June 2007
Jianwei Chen, Michel Dubois, Per Stenström, SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators., IEEE Micro 27(4): 34-48 (2007)
Jie Tao, Asadollah Shahbahrami, Ben Juurlink, Rainer Buchty, Wolfgang Karl, Stamatis Vassiliadis, Optimizing Cache Performance of the Discrete Wavelet Transform Using a Visualization Tool, ISM '07: Proceedings of the Ninth IEEE International Symposium on Multimedia, IEEE Computer Society, December 2007
Jie Tao, Kim D. Hoàng, Wolfgang Karl, CMP Cache Architecture and the OpenMP Performance., IWOMP 2007: 77-88
Jie Tao, Thomas Dressler, Wolfgang Karl, An Interactive Graphical Environment for Code Optimization., International Conference on Computational Science (2) 2007: 831-838
Jie Tao, Tobias Gaugler, Wolfgang Karl, A Profiling Tool for Detecting Cache-Critical Data Structures., Euro-Par 2007: 52-61
Jinfeng Huang, Jeroen Voeten, Henk Corporaal, Predictable real-time software synthesis., Real-Time Systems 36(3): 159-198 (2007)
Jinfeng Huang, Jeroen Voeten, Marcel A. Groothuis, Jan F. Broenink, Henk Corporaal, A model-driven design approach for mechatronic systems., ACSD 2007: 127-136
Jisheng Zhao, Matthew Horsnell, Ian Rogers, Andrew Dinn, Chris C. Kirkham, Ian Watson, Optimizing Chip Multiprocessor Work Distribution Using Dynamic Compilation., Euro-Par 2007: 258-267
Jo Ebergen, Steve Furber, Arash Saifhashemi, Notes On Pulse Signaling, ASYNC '07: Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems, IEEE Computer Society, March 2007
João Bispo, Ioannis Sourdis, João M. P. Cardoso, Stamatis Vassiliadis, Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues., ARC 2007: 179-190
Joachim Keinert, Christian Haubelt, Jürgen Teich, Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow., ICSAMOS 2007: 161-168
Joachim Keinert, Joachim Falk, Christian Haubelt, Jürgen Teich, Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms., ESTImedia 2007: 113-118
Joan-Lluís Ferrer, Elvira Baydal, Antonio Robles, Pedro López, José Duato, Congestion Management in MINs through Marked and Validated Packets., PDP 2007: 254-261
Jochen Hollmann, Anders Ardö, Per Stenström, Effectiveness of caching in a distributed digital library system., Journal of Systems Architecture 53(7): 403-416 (2007)
Johan Cockx, Kristof Denolf, Bart Vanhoof, Richard Stahl, SPRINT: a tool to generate concurrent transaction-level models from sequential code, EURASIP Journal on Applied Signal Processing , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
John Cavazos, Grigori Fursin, Felix V. Agakov, Edwin V. Bonilla, Michael F. P. O'Boyle, Olivier Temam, Rapidly Selecting Good Compiler Optimizations using Performance Counters., CGO 2007: 185-197
John H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steven S. Lumetta, Wen-mei W. Hwu, CIGAR: Application Partitioning for a CPU/Coprocessor Architecture., PACT 2007: 317-326
John Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic, RAMP: Research Accelerator for Multiple Processors., IEEE Micro 27(2): 46-57 (2007)
Johnny Huynh, José Nelson Amaral, Paul Berube, Sid Ahmed Ali Touati, Evaluation of Offset Assignment Heuristics., HiPEAC 2007: 261-275
Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, On the feasibility of early routing capacitance estimation for FPGAs., FPL 2007: 234-239
Jonathan Rubin, Ian Watson, Investigating the Effectiveness of Applying Case-Based Reasoning to the Game of Texas Hold'em., FLAIRS Conference 2007: 417-422
JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally, Register pointer architecture for efficient embedded processors., DATE 2007: 600-605
Joonseok Park, Pedro C. Diniz, Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations., ARC 2007: 97-109
Jordi Guitart, David Carrera, Vicenç Beltran, Jordi Torres, Eduard Ayguadé, Designing an overload control strategy for secure e-commerce applications., Computer Networks 51(15): 4492-4510 (2007)
José Arturo González Gómez, Simulation as an intuition building tool for factory physics, SCSC: Proceedings of the 2007 summer computer simulation conference, Society for Computer Simulation International, July 2007
José A. de Holanda, Jecel Assumpcao, Denis F. Wolf, Eduardo Marques, João M. P. Cardoso, On Adapting Power Estimation Models for Embedded Soft-Core Processors., SIES 2007: 345-348
José C. Castillo, Teresa Olivares, Luis Orozco-Barbosa, Implementation of a rule-based routing protocol for wireless sensor networks., PM2HW2N 2007: 19-25
José Carlos Mouriño, María J. Martín, Patricia González, Ramon Doallo, Fault-tolerant solutions for a MPI compute intensive application., PDP 2007: 246-253
José Flich, José Duato, Logic-Based Distributed Routing for NoCs., Computer Architecture Letters 7(1): 13-16 (2007)
José Gabriel F. Coutinho, M. P. T. Juvonen, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang, Designing a Posture Analysis System with Hardware Implementation., VLSI Signal Processing 47(1): 33-45 (2007)
José Ignacio Aliaga, Matthias Bollhöfer, Alberto F. Martín, Enrique S. Quintana-Ortí, Parallelization of Multilevel Preconditioners Constructed from Inverse-Based ILUs on Shared-Memory Multiprocessors., PARCO 2007: 287-294
José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest, Energy-aware compilation and hardware design for VLIW embedded systems., IJES 3(1/2): 73-82 (2007)
José Luis Ayala, Anya Apavatjrut, David Atienza, Marisa López-Vallejo, Carlos A. López-Barrio, Thermal Characterization and Thermal Management in Processor-Based Systems., Power-aware Computing Systems 2007
José M. Badía, Peter Benner, Maribel Castillo, Heike Faßbender, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Strategies for Parallelizing the Solution of Rational Matrix Equations., PARCO 2007: 255-262
José M. Claver, G. León, High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs., FPL 2007: 629-632
José M. Claver, P. Agustí, G. León, Manel Canseco, A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA., FPL 2007: 567-570
José Manuel Velasco, David Atienza, Katzalin Olcoz, Francisco Tirado, Efficient Object Placement including Node Selection in a Distributed Virtual Machine., PARCO 2007: 509-516
José Villalón, Pedro Cuenca, Luis Orozco-Barbosa, On the capabilities of IEEE 802.11e for multimedia communications over heterogeneous 802.11/802.11e WLANs., Telecommunication Systems 36(1-3): 27-38 (2007)
Jose Flich, A. Mejia, Pedro López, José Duato, Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips., NOCS 2007: 183-194
Jose Flich, Andres Mejia, Pedro López, José Duato, Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips., NOCS 2007: 183-194
Jose Gonzalez-Mora, Fernando De la Torre, Rajesh Murthi, Nicolas Guil, Emilio L. Zapata, Bilinear Active Appearance Models., ICCV 2007: 1-8
Jose L. Ayala, Anya Apavatjrut, David Atienza, Marisa Lopez-Vallejo, Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems, IWIA '07: Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IEEE Computer Society, January 2007
Jose M. Camara, Miquel Moretó, Enrique Vallejo, Ramón Beivide, José Miguel-Alonso, Carmen Martínez, Javier Navaridas, Mixed-radix Twisted Torus Interconnection Networks., IPDPS 2007: 1-10
Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen, The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens)., it - Information Technology 49(3): 143- (2007)
Josep Domènech, Ana Pont, Julio Sahuquillo, José A. Gil, A user-focused evaluation of web prefetching algorithms., Computer Communications 30(10): 2213-2224 (2007)
Josep M. Pérez, Pieter Bellens, Rosa M. Badia, Jesús Labarta, CellSs: Making it easier to program the Cell Broadband Engine processor., IBM Journal of Research and Development 51(5): 593-604 (2007)
Juan A. Lorenzo, Julio L. Albín, Tomás F. Pena, Francisco F. Rivera, David E. Singh, An Inspector/Executor Based Strategy to Efficiently Parallelize N-Body Simulation Programs on Shared Memory Systems., ISPDC 2007: 45-52
Juan Hamers, Lieven Eeckhout, Resource prediction for media stream decoding., DATE 2007: 594-599
Juan Hamers, Lieven Eeckhout, Koen De Bosschere, Exploiting Video Stream Similarity for Energy-Efficient Decoding., MMM (2) 2007: 11-22
Juan M. Cebrian, Juan L. Aragón, José M. García, Leakage Energy Reduction in Value Predictors through Static Decay., IPDPS 2007: 1-7
Juan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras, Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors., Conf. Computing Frontiers 2007: 113-122
Juan Piernas, Toni Cortes, José M. García, The Design of New Journaling File Systems: The DualFS Case., IEEE Trans. Computers 56(2): 267-281 (2007)
Juan Segarra, Vicent Cholvi, Convergence of periodic broadcasting and video-on-demand., Computer Communications 30(5): 1136-1141 (2007)
Juan Touriño, Basilio B. Fraguela, Ramon Doallo, Manuel Arenaz, Special Issue: Current Trends in Compilers for Parallel Computers., Concurrency and Computation: Practice and Experience 19(18): 2313-2316 (2007)
Juho Antikainen, Perttu Salmela, Olli Silvén, Markku J. Juntti, Jarmo Takala, Markus Myllylä, Application-Specific Instruction Set Processor Implementation of List Sphere Detector., EURASIP J. Emb. Sys. 2007: (2007)
Jukka Suhonen, Mikko Kohvakka, Mauri Kuorilehto, Marko Hännikäinen, Timo D. Hämäläinen, Cost-aware capacity optimization in dynamic multi-hop WSNs., DATE 2007: 666-671
Jun Qin, Marek Wieczorek, Kassia Plankensteiner, Thomas Fahringer, Towards a Light-weight Workflow Engine in the Asklon Grid Environment., CoreGRID 2007: 239-251
Jun Qin, Thomas Fahringer, Advanced data flow support for scientific grid workflow applications., SC 2007: 42
Kalle Holma, Mikko Setälä, Erno Salminen, Timo D. Hämäläinen, Evaluating the Model Accuracy in Automated Design Space Exploration., DSD 2007: 173-180
Karel Bruneel, Peter Bertels, Dirk Stroobandt, A Method for Fast Hardware Specialization at run-time., FPL 2007: 35-40
Karim Ammous, Nasser Benameur, Smail Niar, Java virtual machines behavior on embedded systems, SE'07: Proceedings of the 25th conference on IASTED International Multi-Conference: Software Engineering, ACTA Press, February 2007
Karthik Baddam, Mark Zwolinski, Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure., VLSI Design 2007: 854-862
Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek, Transaction-Based Communication-Centric Debug., NOCS 2007: 95-106
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic, MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture., ARC 2007: 26-38
Kenneth Hoste, Lieven Eeckhout, Microarchitecture-Independent Workload Characterization., IEEE Micro 27(3): 63-72 (2007)
Kenneth Hoste, Lieven Eeckhout, Hendrik Blockeel, Analyzing commercial processor performance numbers for predicting performance of applications of interest., SIGMETRICS 2007: 375-376
Keqiu Li, Chris R. Jesshope, Hai Jin, Jean-Luc Gaudiot, Network and Parallel Computing IFIP International Conference NPC 2007 Dalian China September 18-21 2007 Proceedings, Springer 2007
Kevin Casey, M. Anton Ertl, David Gregg, Optimizing indirect branch prediction accuracy in virtual machine interpreters., ACM Trans. Program. Lang. Syst. 29(6): (2007)
Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Increasing data-bandwidth to instruction-set extensions through register clustering., ICCAD 2007: 166-171
Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis, HARTES Toolchain Early Evaluation: Profiling Compilation and HDL Generation., FPL 2007: 402-408
Koen Bertels, Walid A. Najjar, Arjan J. van Genderen, Stamatis Vassiliadis, FPL 2007 International Conference on Field Programmable Logic and Applications Amsterdam The Netherlands 27-29 August 2007, IEEE 2007
Koen De Bosschere, David R. Kaeli, Per Stenström, David B. Whalley, Theo Ungerer, High Performance Embedded Architectures and Compilers Second International Conference HiPEAC 2007 Ghent Belgium January 28-30 2007 Proceedings, Springer 2007
Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier, High-Performance Embedded Architecture and Compilation Roadmap., T. HiPEAC 1: 5-29 (2007)
Kolin Paul, Joel Porquet, Josep Llosa, Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration., DSD 2007: 317-324
Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis, Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications., Integration 40(2): 74-93 (2007)
Kostas Papadopoulos, Kyriakos Stavrou, Pedro Trancoso, HelperCore_DB: Exploiting Multicore Technology for Databases., PACT 2007: 420
Kostas Siozios, Dimitrios Soudris, A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs., ISVLSI 2007: 55-60
Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris, Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support., FPL 2007: 652-655
Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris, A software-supported methodology for designing high-performance 3D FPGA architectures., VLSI-SoC 2007: 54-59
Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis, Designing Heterogeneous FPGAs with Multiple SBs., ARC 2007: 91-96
Kris Venstermans, Lieven Eeckhout, Koen De Bosschere, Java object header elimination for reduced memory consumption in 64-bit virtual machines., TACO 4(3): (2007)
Kris Venstermans, Lieven Eeckhout, Koen De Bosschere, Object-Relative Addressing: Compressed Pointers in 64-Bit Java Virtual Machines., ECOOP 2007: 79-100
Kristof Denolf, Adrian Chirila-Rus, Paul Schumacher, Robert Turney, Kees Vissers, Diederik Verkest, Henk Corporaal, A systematic approach to design low-power video codec cores, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Kristof Denolf, Marco Jan Gerrit Bekooij, Johan Cockx, Diederik Verkest, Henk Corporaal, Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations., EURASIP J. Adv. Sig. Proc. 2007: (2007)
Krisztián Flautner, Architectural Trade-Offs for Fault Tolerant Multi-Core Systems., IOLTS 2007: 261
Krisztián Flautner, Blurring the Layers of Abstractions: Time to Take a Step Back?, IOLTS 2007: 127
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar, Optimizing instruction-set extensible processors under data bandwidth constraints., DATE 2007: 588-593
Kyoko Iwasawa, Alan Mycroft, Choosing Method of the Most Effective Nested Loop Shearing for Parallelism., PDCAT 2007: 267-276
Kyriakos Neocleous, Marios D. Dikaiakos, Paraskevi Fragopoulou, Evangelos P. Markatos, Failure Management in Grids: the Case of the EGEE Infrastructure., Parallel Processing Letters 17(4): 391-410 (2007)
Kyriakos Stavrou, Pedro Trancoso, Thermal-aware scheduling for future chip multiprocessors, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Kyriakos Stavrou, Pedro Trancoso, Thermal-Aware Scheduling for Future Chip Multiprocessors., EURASIP J. Emb. Sys. 2007: (2007)
Kyriakos Vlachos, Theofanis Orphanoudakis, Yannis Papaefstathiou, Nikos A. Nikolaou, Dionisios N. Pnevmatikatos, George E. Konstantoulakis, Jorge-A. Sanchez-P., Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units., Microprocessors and Microsystems 31(3): 188-199 (2007)
Lars Bauer, Muhammad Shafique, Dirk Teufel, Jorg Henkel, A Self-Adaptive Extensible Embedded Processor, SASO '07: Proceedings of the First International Conference on Self-Adaptive and Self-Organizing Systems, IEEE Computer Society, July 2007
Lars Bauer, Muhammad Shafique, Simon Kramer, Jörg Henkel, RISPP: rotating instruction set processing platform, DAC '07: Proceedings of the 44th annual conference on Design automation, ACM, June 2007
Laurence T. Yang, Jose G. Delgado-Frias, Yiming Li, Mohammed Niamat, Dimitrios Soudris, Srinivasa R. Vemuru, Preface of Special Issue on VLSI Design and Test, Microelectronic Engineering , Volume 84 Issue 2, Elsevier Science Ltd., February 2007
Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Y. Niamat, Dimitrios Soudris, Srinivasa Vemuru, Preface., Integration 40(2): 61 (2007)
Lazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, N. Voros, Data Structure Exploration of Dynamic Applications., PACT 2007: 421
Lazaros Papadopoulos, Christos Baloukas, Nikolaos Zompakis, Dimitrios Soudris, Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems., ICSAMOS 2007: 58-65
Lazaros Papadopoulos, Dimitrios Soudris, System-Level Application-Specific NoC Design for Network and Multimedia Applications., PATMOS 2007: 1-9
Lazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Application - specific NoC platform design based on System Level Optimization., ISVLSI 2007: 311-316
Leandro Fiorin, Cristina Silvano, Mariagiovanna Sami, Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations., DSD 2007: 539-542
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Cristina Silvano, A data protection unit for NoC-based architectures., CODES+ISSS 2007: 167-172
Lei Gao, Chao Li, Chengjun Zhu, Zhang Xiong, A Motion Compensated De-interlacing Algorithm for Motive Object Capture., HCI (12) 2007: 74-81
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, A fast and generic hybrid simulation approach using C virtual machine., CASES 2007: 3-12
Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jef L. van Meerbergen, Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring., SAMOS 2007: 385-395
Lennart Yseboodt, Michael De Nil, Mladen Berekovic, Electrocardiogram on Wireless Sensor Nodes., Power-aware Computing Systems 2007
Leonel Augusto Sousa, Noel E. O'Connor, Marco Mattavelli, Antonio Nunez, Embedded Systems for Portable and Mobile Video Platforms., EURASIP J. Emb. Sys. 2007: (2007)
Leonel Sousa, Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli., IEEE Symposium on Computer Arithmetic 2007: 240-250
Leonel Sousa, Moisés Simões Piedade, J. Germano, Teresa Mendes de Almeida, Paulo Alexandre Crisóstomo Lopes, Filipe Cardoso, Paulo Freitas, Generic Architecture Designed for Biomedical Embedded Systems., IESS 2007: 353-362
Leticia Pascual, Alejandro Torrentí, Julio Sahuquillo, Jose Flich, Understanding cache hierarchy interactions with a program-driven simulator., WCAE 2007: 30-35
Li Zhang, Chris R. Jesshope, On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores., Euro-Par Workshops 2007: 38-48
Liliana Cucu, Joël Goossens, Feasibility intervals for multiprocessor fixed-priority scheduling of arbitrary deadline periodic systems., DATE 2007: 1635-1640
Lily R. Liang, Vinay Mandal, Yi Lu, Deepak Kumar, Multi-dimensional Cluster Misclassification Test for Pathway Differential Analysis of Diabetes., IMSCCS 2007: 84-91
Limor Fix, Orna Grumberg, Amnon Heyman, Tamir Heyman, Assaf Schuster, Verifying Very Large Industrial Circuits Using 100 Processes and Beyond., Int. J. Found. Comput. Sci. 18(1): 45-62 (2007)
Lingxiang Xiang, Jiangwei Huang, Weihua Sheng, Tianzhou Chen, The Design and Implementation of the DVS Based Dynamic Compiler for Power Reduction., APPT 2007: 233-240
Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, R. Ramanarayanan, Balaji Vaidyanathan, Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors., VLSI Design 2007: 251-258
Liping Xue, Ozcan Ozturk, Mahmut T. Kandemir, A Memory-Conscious Code Parallelization Scheme., DAC 2007: 230-233
Liza Fireman, Erez Petrank, Ayal Zaks, New Algorithms for SIMD Alignment., CC 2007: 1-15
Lotfi Mhamdi, Georgi Gaydadjiev, Stamatis Vassiliadis, Efficient Multicast Support in High-Speed Packet Switches., JNW 2(3): 28-35 (2007)
Louis-Noël Pouchet, Cédric Bastoul, Albert Cohen, Nicolas Vasilache, Iterative Optimization in the Polyhedral Model: Part I One-Dimensional Time., CGO 2007: 144-156
Luca Benini, Carlotta Guiducci, Christian Paulus, Electronic Detection of DNA Hybridization: Toward CMOS Microarrays., IEEE Design & Test of Computers 24(1): 38-48 (2007)
Luca Benini, Naehyuck Chang, Ulrich Kremer, Christian W. Probst, Power-aware Computing Systems 21.01. - 26.01.2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI) Schloss Dagstuhl Germany 2007
Luca Benini, Naehyuck Chang, Ulrich Kremer, Christian W. Probst, 07041 Summary - Power-aware Computing Systems., Power-aware Computing Systems 2007
Luca Benini, Naehyuck Chang, Ulrich Kremer, Christian W. Probst, 07041 Abstracts Collection - Power-aware Computing Systems., Power-aware Computing Systems 2007
Luca Fossati, Handshake Games., Electr. Notes Theor. Comput. Sci. 171(3): 21-41 (2007)
Luca Fossati, Pier Luca Lanzi, Kumara Sastry, David E. Goldberg, Osvaldo Gómez, A Simple Real-Coded Extended Compact Genetic Algorithm., IEEE Congress on Evolutionary Computation 2007: 342-348
Ludo Van Put, Dominique Chanet, Koen De Bosschere, Whole-program linear-constant analysis with applications to link-time optimization., SCOPES 2007: 61-70
Luis A. Plana, Steve B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang, A GALS Infrastructure for a Massively Parallel Multiprocessor, IEEE Design & Test , Volume 24 Issue 5, IEEE Computer Society Press, September 2007
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Victor Viñals, Data prefetching in a cache hierarchy with high bandwidth and capacity, SIGARCH Computer Architecture News , Volume 35 Issue 4, ACM, September 2007
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals, Data prefetching in a cache hierarchy with high bandwidth and capacity., SIGARCH Computer Architecture News 35(4): 37-44 (2007)
Luis Orozco-Barbosa, Pedro Cuenca, Editorial., Telecommunication Systems 36(1-3): 1-2 (2007)
Lurng-Kuo Liu, Qiang Liu, Apostol Natsev, Kenneth A. Ross, John R. Smith, Ana Lucia Varbanescu, Digital Media Indexing on the Cell Processor., ICME 2007: 1866-1869
M. Goyeneche, Jesús E. Villadangos, José Javier Astrain, Manuel Prieto, Alberto Córdoba, A Distributed Data Gathering Algorithm for Wireless Sensor Networks with Uniform Architecture., PDP 2007: 373-380
M. Hartmann, V. Pantazis, Tom Vander Aa, Mladen Berekovic, Christian Hochberger, Bjorn De Sutter, Still Image Processing on Coarse-Grained Reconfigurable Array Architectures., ESTImedia 2007: 67-72
M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli, Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays., ICCAD 2007: 765-772
M. M. Waliullah, Per Stenström, Starvation-Free Transactional Memory-System Protocols., Euro-Par 2007: 280-291
M. M. Waliullah, Per Stenstrom, Starvation-free commit arbitration policies for transactional memory systems, SIGARCH Computer Architecture News , Volume 35 Issue 1, ACM, March 2007
Magnus Själander, Per Larsson-Edefors, Magnus Björk, A Flexible Datapath Interconnect for Embedded Applications., ISVLSI 2007: 15-20
Mahmood Ahmadi, Stephan Wong, A Cache Architecture for Counting Bloom Filters., ICON 2007: 218-223
Mahmood Ahmadi, Stephan Wong, A performance model for network processor architectures in packet processing system, PDCS '07: Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems, ACTA Press, November 2007
Mahmood Ahmadi, Stephan Wong, Modified collision packet classification using counting bloom filter in tuple space., Parallel and Distributed Computing and Networks 2007: 295-300
Mahmut T. Kandemir, Ozcan Ozturk, Vijay Degalahal, Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings., VLSI Design 2007: 227-232
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son, Ozcan Ozturk, Memory bank aware dynamic loop scheduling., DATE 2007: 1671-1676
Malgorzata Steinder, Ian Whalley, David Carrera, Ilona Gaweda, David M. Chess, Server virtualization in autonomic management of heterogeneous workloads., Integrated Network Management 2007: 139-148
Manish Verma, Peter Marwedel, Advanced Memory Optimization Techniques for Low-Power Embedded Processors, 1st edition, Advanced Memory Optimization Techniques for Low-Power Embedded Processors, 1st edition, Springer Publishing Company, Incorporated, May 2007
Manoj Gupta, Fermín Sánchez, Josep Llosa, Cluster-level simultaneous multithreading for VLIW processors., ICCD 2007: 121-128
Manoj Gupta, Fermín Sánchez, Josep Llosa, Merge Logic for Clustered Multithreaded VLIW Processors., DSD 2007: 353-360
Manoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksrishnan, Energy Based Design Space Exploration of Multiprocessor VLIW Architectures., DSD 2007: 307-310
Manolis Marazakis, Vassilis Papaefstathiou, Angelos Bilas, Optimization and bottleneck analysis of network block I/O in commodity storage systems., ICS 2007: 33-42
Manuel Arenaz, Juan Touriño, Ramon Doallo, Program Behavior Characterization Through Advanced Kernel Recognition., Euro-Par 2007: 237-247
Manuel Nickschas, Uwe Brinkschulte, Using Multi-Agent Principles for Implementing an Organic Real-Time Middleware., ISORC 2007: 189-195
María Dolores R-Moreno, Manuel Prieto, Daniel Meziat, AN AI ELECTRICAL GROUND SUPPORT EQUIPMENT FOR CONTROLLING AND TESTING A SPACE INSTRUMENT, Applied Artificial Intelligence , Volume 21 Issue 2, Taylor & Francis, Inc., February 2007
María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida, Area optimization of multi-cycle operators in high-level synthesis., DATE 2007: 449-454
María Dolores Rodríguez-Moreno, Manuel Prieto, Daniel Meziat, An AI Electrical Ground Support Equipment for Controlling and Testing a Space Instrument., Applied Artificial Intelligence 21(2): 81-98 (2007)
Marc Casas, Rosa M. Badia, Jesús Labarta, Automatic Phase Detection of MPI Applications., PARCO 2007: 129-136
Marc Casas, Rosa M. Badia, Jesús Labarta, Automatic Structure Extraction from MPI Applications Tracefiles., Euro-Par 2007: 3-12
Marc Daumas, David Lester, Stochastic Formal Methods: An Application to Accuracy of Numeric Software., HICSS 2007: 262
Marc Duranton, Programmable Engines for Embedded Systems: The New Challenges., ISQED 2007: 556-557
Marc Sanchez Artigas, Pedro Garcia Lopez, Antonio F. Skarmeta, A Comparative Study of Hierarchical DHT Systems, LCN '07: Proceedings of the 32nd IEEE Conference on Local Computer Networks, IEEE Computer Society, October 2007
Marcel Arrufat, Gerard Paris, Pedro Garcia Lopez, Antonio F. Gomez Skarmeta, SCOMET: Adapting Collaborative Working Environments to the MANET Scenario, WETICE '07: Proceedings of the 16th IEEE International Workshops on Enabling Technologies: Infrastructure for Collaborative Enterprises, IEEE Computer Society, June 2007
Marcello Mura, Marco Paolieri, SC2 StateCharts to SystemC: Automatic Executable Models Generation., FDL 2007: 198-203
Marcello Mura, Marco Paolieri, Luca Negri, Mariagiovanna Sami, StateCharts to systemc: a high level hardware simulation approach., ACM Great Lakes Symposium on VLSI 2007: 505-508
Marco Aldinucci, Marco Danelutto, Skeleton-based parallel programming: Functional and parallel semantics in a single shot., Computer Languages Systems & Structures 33(3-4): 179-192 (2007)
Marco Aldinucci, Marco Danelutto, The cost of security in skeletal systems., PDP 2007: 213-220
Marco Aldinucci, Marco Danelutto, Massimo Torquati, Francesco Polzella, Gianmarco Spinatelli, Marco Vanneschi, Alessandro Gervaso, Manuel Cacitti, Pierfrancesco Zuccato, VirtuaLinux: Virtualized High-Density Clusters with no Single Point of Failure., PARCO 2007: 355-362
Marco Aldinucci, Marco Danelutto, Peter Kilpatrick, Management in Distributed Systems: A Semi-formal Approach., Euro-Par 2007: 651-661
Marco Aldinucci, Marco Danelutto, Peter Kilpatrick, Adding metadata to Orc to support reasoning about grid programs., CoreGRID 2007: 205-214
Marco Aldinucci, Marco Danelutto, Peter Kilpatrick, A Framework for Prototyping and Reasoning about Distributed Systems., PARCO 2007: 235-242
Marco Aldinucci, Sonia Campa, Marco Danelutto, Patrizio Dazzi, Domenico Laforenza, Nicola Tonellotto, Peter Kilpatrick, Behavioural Skeletons for Component Autonomic Management on Grids., CoreGRID Workshop - Making Grids Work 2007: 3-15
Marco Alexandre Cravo Gomes, Gabriel Falcão Paiva Fernandes, Vítor Manuel Mendes da Silva, Vitor Ferreira, Alexandre Sengo, Miguel Falcão, Flexible Parallel Architecture for DVB-S2 LDPC Decoders., GLOBECOM 2007: 3265-3269
Marco D. Santambrogio, Seda Ogrenci Memik, Vincenzo Rana, Umut A. Acar, Donatella Sciuto, A novel SoC design methodology combining adaptive software and reconfigurable hardware., ICCAD 2007: 303-308
Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero, Implicit Transactional Memory in Kilo-Instruction Multiprocessors., Asia-Pacific Computer Systems Architecture Conference 2007: 339-353
Marco Mantovani, Simone Leardini, Martino Ruggiero, Andrea Acquaviva, Luca Benini, A lightweight parallel java execution environment for embedded multiprocessor systems-on-chip., ACM Great Lakes Symposium on VLSI 2007: 509-512
Marco Paolieri, Ivano Bonesana, Marco D. Santambrogio, ReCPU: A parallel and pipelined architecture for regular expression matching., VLSI-SoC 2007: 19-24
Maria Andréia Formico Rodrigues, Ricardo Régis Cavalcante Chaves, Performance and user based analysis of a collaborative virtual environment system, GRAPHITE '07: Proceedings of the 5th international conference on Computer graphics and interactive techniques in Australia and Southeast Asia, ACM, December 2007
Marina Alonso, Salvador Coll, Vicente Santonja, Juan Miguel Martínez, Pedro López, José Duato, Power-Aware Fat-Tree Networks Using On/Off Links., HPCC 2007: 472-483
Marina Biberstein, Eitan Farchi, Shmuel Ur, Choosing among alternative pasts., Concurrency and Computation: Practice and Experience 19(3): 341-353 (2007)
Mark Thompson, Andy D. Pimentel, Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration., SAMOS 2007: 222-232
Mark Thompson, Hristo Nikolov, Todor Stefanov, Andy D. Pimentel, Cagkan Erbas, Simon Polstra, Ed F. Deprettere, A framework for rapid system-level exploration synthesis and programming of multimedia MP-SoCs., CODES+ISSS 2007: 9-14
Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner, The Next Generation Challenge for Software Defined Radio., SAMOS 2007: 343-354
Martin Karlsson, Erik Hagersten, Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution., IPDPS 2007: 1-10
Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Solving Multi-objective Pseudo-Boolean Problems., SAT 2007: 56-69
Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, SAT-decoding in evolutionary algorithms for discrete constrained optimization problems., IEEE Congress on Evolutionary Computation 2007: 935-942
Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström, FlexCore: Utilizing Exposed Datapath Control for Efficient Computing., ICSAMOS 2007: 18-25
Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci, A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes., GLOBECOM 2007: 3270-3274
Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci, A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes., VLSI-SoC 2007: 236-241
Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda, The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer., VLSI Signal Processing 47(1): 15-31 (2007)
Matteo Giaconia, Marco Macchetti, Francesco Regazzoni, Kai Schramm, Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes., VLSI Design 2007: 731-737
Matteo Giani, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto, Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity., ERSA 2007: 78-84
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, Exploration of distributed shared memory architectures for NoC-based multiprocessors., Journal of Systems Architecture 53(10): 719-732 (2007)
Matthew Barnes, Hugh Leather, D. K. Arvind, Emergency Evacuation using Wireless Sensor Networks., LCN 2007: 851-857
Matthew Curtis-Maury, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, A comparison of online and offline strategies for program adaptation., ACM Southeast Regional Conference 2007: 162-167
Matthew Curtis-Maury, Karan Singh, Sally A. McKee, Filip Blagojevic, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz, Identifying energy-efficient concurrency levels using machine learning., CLUSTER 2007: 488-495
Matthias Alles, Torben Brack, Norbert Wehn, A Reliability-Aware LDPC Code Decoding Algorithm., VTC Spring 2007: 1544-1548
Matthias May, Christian Neeb, Norbert Wehn, Evaluation of High Throughput Turbo-Decoder Architectures., ISCAS 2007: 2770-2773
Matthias Woehrle, Christian Plessl, Jan Beutel, Lothar Thiele, Increasing the reliability of wireless sensor networks with a distributed testing framework., EmNets 2007: 93-97
Matthieu Leclercq, Ali Erdem Özcan, Vivien Quéma, Jean-Bernard Stefani, Supporting Heterogeneous Architecture Descriptions in an Extensible Toolset., ICSE 2007: 209-219
Mauri Kuorilehto, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen, Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network., SAMOS 2007: 396-407
Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen, SensorOS: A New Operating System for Time Critical WSN Applications., SAMOS 2007: 431-442
Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero, Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications., ISPASS 2007: 62-71
Mauricio Alvarez, Esther Salami, Alex Ramirez, Mateo Valero, HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications, IISWC '07: Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization - Volume 00 , Volume 00, IEEE Computer Society, September 2007
Maurizio Palesi, Shashi Kumar, Rickard Holsmark, Vincenzo Catania, Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms., IPDPS 2007: 1-8
Md. Mafijul Islam, On the Limitations of Compilers to Exploit Thread-Level Parallelism in Embedded Applications., ACIS-ICIS 2007: 60-66
Md. Mafijul Islam, Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications., SBAC-PAD 2007: 54-61
Md. Mafijul Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenström, Loop-level Speculative Parallelism in Embedded Applications., ICPP 2007: 3
Md. Mafijul Islam, Per Stenström, Energy and Performance Trade-offs between Instruction Reuse and Trivial Computations for Embedded Applications., SIES 2007: 86-93
Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar, Adaptive Sampling for Efficient MPSoC Architecture Simulation., MASCOTS 2007: 186-192
Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang, A Combined Hardware/Software Optimization Framework for Signal Representation and Recognition., International Conference on Computational Science (1) 2007: 1230-1237
Michael Behar, Avi Mendelson, Avinoam Kolodny, Trace cache sampling filter., ACM Trans. Comput. Syst. 25(1): (2007)
Michael Dalton, Hari Kannan, Christos Kozyrakis, Raksha: a flexible information flow architecture for software security., ISCA 2007: 482-493
Michael F. P. O'Boyle, François Bodin, José González, Lucian N. Vintan, Topic 4 High-Performance Architectures and Compilers., Euro-Par 2007: 235
Michael F. P. O'Boyle, François Bodin, Marcelo Cintra, Introduction to Part 2., T. HiPEAC 1: 139 (2007)
Michael Ferdman, Babak Falsafi, Last-Touch Correlated Data Streaming., ISPASS 2007: 105-115
Michael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich, Interactive presentation: Reliability-aware system synthesis., DATE 2007: 409-414
Michael Klemm, Jean Christophe Beyler, Ronny T. Lampert, Michael Philippsen, Philippe Clauss, Esodyp+: Prefetching in the Jackal Software DSM., Euro-Par 2007: 563-573
Michael Med, Andreas Krall, Instruction Set Encoding Optimization for Code Size Reduction., ICSAMOS 2007: 9-17
Michael Sass Hansen, Hildur Ólafsdóttir, Tron A. Darvann, Nuno V. Hermann, Estanislao Oubel, Rasmus Larsen, Bjarne K. Ersbøll, Alejandro F. Frangi, Per Larsen, Chad A. Perlyn, Gil, Estimation of Independent Non-Linear Deformation Modes for Analysis of Craniofacial Malformations in Crouzon Mice., ISBI 2007: 1296-1299
Michael Van Biesbrouck, Lieven Eeckhout, Brad Calder, Representative Multiprogram Workloads for Multithreaded Processor Simulation, IISWC '07: Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization - Volume 00 , Volume 00, IEEE Computer Society, September 2007
Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Automated framework for partitioning DSP applications in hybrid reconfigurable platforms., Microprocessors and Microsystems 31(1): 1-14 (2007)
Michalis Polychronakis, Kostas G. Anagnostakis, Evangelos P. Markatos, Network-level polymorphic shellcode detection using emulation., Journal in Computer Virology 2(4): 257-274 (2007)
Michalis Polychronakis, Kostas G. Anagnostakis, Evangelos P. Markatos, Emulation-Based Detection of Non-self-contained Polymorphic Shellcode., RAID 2007: 87-106
Miguel Lozano, Juan M. Orduña, Vicente Cavero, A Genetic Approach for Distributing Semantic Databases of Crowd Simulations., IPDPS 2007: 1-8
Miguel Lozano, Pedro Morillo, Juan M. Orduña, Vicente Cavero, On the Design of an Efficient Architecture for Supporting Large Crowds of Autonomous Agents., AINA 2007: 716-723
Miguel Peon-Quiros, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris, Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption., PATMOS 2007: 373-383
Miguel Ribeiro, Leonel Sousa, A Run-time Reconfigurable Processor for Video Motion Estimation., FPL 2007: 726-729
Miloš Milovanović, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrian Cristal, Eduard Ayguadé, Mateo Valero, Multithreaded software transactional memory and OpenMP, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Milos Milovanovic, Roger Ferrer, Osman S. Unsal, Adrián Cristal, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Transactional Memory and OpenMP., IWOMP 2007: 37-53
Miltiadis Hatzimihail, Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis, A Methodology for Detecting Performance Faults in Microprocessor Speculative Execution Units via Hardware Performance Monitoring, IEEE International Test Conference (ITC 2007), Santa Clara, California, USA, October 2007.
Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson, Overdrive Power-Gating Techniques for Total Power Minimization., ISVLSI 2007: 125-132
Minh B. Do, J. Benton, Menkes Van Den Briel, Subbarao Kambhampati, Planning with goal utility dependencies, IJCAI'07: Proceedings of the 20th international joint conference on Artifical intelligence, Morgan Kaufmann Publishers Inc., January 2007
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson, Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays., ISQED 2007: 185-191
Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis, High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process., DSD 2007: 249-256
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Online Prediction of Applications Cache Utility., ICSAMOS 2007: 169-177
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Explaining Dynamic Cache Partitioning Speed Ups., Computer Architecture Letters 6(1): 1-4 (2007)
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, MLP-Aware Dynamic Cache Partitioning., PACT 2007: 418
Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero, A Flexible Heterogeneous Multi-Core Architecture., PACT 2007: 13-24
Mirko Loghi, Luca Benini, Massimo Poncino, Power macromodeling of MPSoC message passing primitives., ACM Trans. Embedded Comput. Syst. 6(4): (2007)
Mladen Berekovic, Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring., DSD 2007: 16-18
Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel, Run-time adaptive on-chip communication scheme, ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, IEEE Press, November 2007
Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari, Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors., AICCSA 2007: 528-534
Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi, A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services., DDECS 2007: 247-250
Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi, A UML Based System Level Failure Rate Assessment Technique for SoC Designs., VTS 2007: 243-248
Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi, Low test application time resource binding for behavioral synthesis., ACM Trans. Design Autom. Electr. Syst. 12(2): (2007)
Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi, A New Approach for Design and Verification of Transaction Level Models., ISCAS 2007: 3760-3763
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi, On-Chip Verification of NoCs Using Assertion Processors., DSD 2007: 535-538
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi, Functional Test-Case Generation by a Control Transaction Graph for TLM Verification., DSD 2007: 157-164
Mohammad Reza Nami, Koen Bertels, A Survey of Autonomic Computing Systems, ICAS '07: Proceedings of the Third International Conference on Autonomic and Autonomous Systems, IEEE Computer Society, June 2007
Mohammed Fellahi, Albert Cohen, Sid Touati, Code-size conscious pipelining of imperfectly nested loops, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Montserrat Bóo, Margarita Amor, Jürgen Döllner, Unified Hybrid Terrain Representation Based on Local Convexifications., GeoInformatica 11(3): 331-357 (2007)
Mostafa I. H. Abd-El-Barr, Salman A. Khan, Design and analysis of a fault tolerant hybrid mobile scheme, Information Sciences: an International Journal , Volume 177 Issue 12, Elsevier Science Inc., June 2007
Mourad Alia, Viktor S. Wold Eide, Nearchos Paspallis, Frank Eliassen, Svein O. Hallsteinsen, George A. Papadopoulos, A Utility-Based Adaptivity Model for Mobile Applications, AINAW '07: Proceedings of the 21st International Conference on Advanced Information Networking and Applications Workshops - Volume 02 , Volume 02, IEEE Computer Society, May 2007
Muhammad Omer Cheema, Lionel Lacassagne, Omar Hammami, System-platforms-based SystemC TLM design of image processing chains for embedded applications, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Muhammad Omer Cheema, Omar Hammami, Lionel Lacassagne, Alain Merigot, Hardware /software codesign of image processing applications using Transaction Level Modeling, ASAP '07: Proceedings of the 2007 IEEE International Conf. on Application-Specific Systems, Architectures and Processors (ASAP) - Volume 00 , Volume 00, IEEE Computer Society, July 2007
Mumtaz Siddiqui, Alex Villazón, Thomas Fahringer, Semantic-Based On-demand Synthesis of Grid Activities for Automatic Workflow Generation., eScience 2007: 43-50
Mumtaz Siddiqui, Thomas Fahringer, Semantically-enhanced on-demand resource provision and management for the grid., Multiagent and Grid Systems 3(3): 327-339 (2007)
N. Pete Sedcole, Peter Y. K. Cheung, Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis., FPGA 2007: 178-187
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Run-Time Integration of Reconfigurable Video Processing Systems., IEEE Trans. VLSI Syst. 15(9): 1003-1016 (2007)
Nabil Hasasneh, Ian Bell, Chris R. Jesshope, Asynchronous arbiter for micro-threaded chip multiprocessors., Journal of Systems Architecture 53(5-6): 253-262 (2007)
Nabil Hasasneh, Ian Bell, Chris R. Jesshope, High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids., AICCSA 2007: 301-308
Nadine Azémard, Lars J. Svensson, Integrated Circuit and System Design. Power and Timing Modeling Optimization and Simulation 17th International Workshop PATMOS 2007 Gothenburg Sweden September 3-5 2007 Proceedings, Springer 2007
Nathan Clark, Amir Hormati, Sami Yehia, Scott A. Mahlke, Krisztián Flautner, Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping., HPCA 2007: 216-227
Neil Bergmann, Marco Platzner, Jürgen Teich, Editorial: dynamically reconfigurable architectures, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Neil W. Bergmann, Yi Lu, John A. Williams, Automatic Self-Reconfiguration of System-on-Chip Peripherals., FCCM 2007: 313-316
Nhut Thanh Quach, Bahman Zafarifar, G. N. Gaydadjiev, Real-time FPGA-implementation for blue-sky Detection., ASAP 2007: 76-82
Nicholas Beck, Ian Johnson, Shaping TinyOS to deal with evolving device architectures: experiences porting TinyOS-2.0 to the Chipcon CC2430., EmNets 2007: 83-87
Nicola E. L'Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni, Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems., DSD 2007: 361-368
Nicolas Fournel, Antoine Fraboulet, Guillaume Chelius, Eric Fleury, Bruno Allard, Olivier Brevet, Worldsens: from lab to sensor network application development and deployment., IPSN 2007: 551-552
Nicolas Fournel, Antoine Fraboulet, Paul Feautrier, eSimu: a Fast and Accurate Energy Consumption Simulator for Real Embedded System., WOWMOM 2007: 1-6
Nicolas Fournel, Antoine Fraboulet, Paul Feautrier, Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements., PATMOS 2007: 10-19
Nicolas Guil, J. M. González-Linares, Julián Ramos Cózar, Emilio L. Zapata, A Clustering Technique for Video Copy Detection., IbPRIA (1) 2007: 451-458
Nicolas Vasilache, Albert Cohen, Louis-Noël Pouchet, Automatic Correction of Loop Transformations., PACT 2007: 292-304
Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha, Tutorial 5: SoC Communication Architectures: Technology Current Practice Research and Trends., VLSI Design 2007: 8
Nikolaos Chrysos, Congestion management for non-blocking clos networks., ANCS 2007: 117-126
Nikolaos Zompakis, Lazaros Papadopoulos, Georgios Ch. Sirakoulis, Dimitrios Soudris, Implementing cellular automata modeled applications on network-on-chip platforms., VLSI-SoC 2007: 288-291
Nikolas Kroupis, Dimitrios Soudris, Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate., PATMOS 2007: 505-515
Nikos Hardavellas, Ippokratis Pandis, Ryan Johnson, Naju Mancheril, Anastassia Ailamaki, Babak Falsafi, Database Servers on Chip Multiprocessors: Limitations and Opportunities., CIDR 2007: 79-87
Nikos Pogkas, George E. Karastergios, Christos D. Antonopoulos, Stavros A. Koubias, George Papadopoulos, Architecture Design and Implementation of an Ad-Hoc Network for Disaster Relief Operations., IEEE Trans. Industrial Informatics 3(1): 63-72 (2007)
Nils Agne Nordbotten, Tor Skeie, A Routing Methodology for Dynamic Fault Tolerance in Meshes and Tori., HiPC 2007: 514-527
Nir Shavit, Nicolas Schabanel, Pascal Felber, Christos Kaklamanis, Topic 12 Theory and Algorithms for Parallel Computation., Euro-Par 2007: 793
Nitzan Peleg, Bilha Mendelson, Detecting Change in Program Behavior for Adaptive Optimization., PACT 2007: 150-162
Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun, ATLAS: a chip-multiprocessor with transactional memory support., DATE 2007: 3-8
Nuno Roma, Leonel Sousa, Efficient hybrid DCT-domain algorithm for video spatial downscaling, EURASIP Journal on Advances in Signal Processing , Volume 2007 Issue 2, Hindawi Publishing Corp., June 2007
Ohad Shacham, Mooly Sagiv, Assaf Schuster, Scaling model checking of dataraces using dynamic information., J. Parallel Distrib. Comput. 67(5): 536-550 (2007)
Oliver Schliebusch, Heinrich Meyr, Rainer Leupers, Optimized ASIP Synthesis from Architecture Description Language Models, Optimized ASIP Synthesis from Architecture Description Language Models, Springer-Verlag New York, Inc., February 2007
Oliverio J. Santana, Alex Ramírez, Mateo Valero, Enlarging Instruction Streams., IEEE Trans. Computers 56(10): 1342-1357 (2007)
Olivier Zendra, Eric Jul, Roland Ducournau, Etienne Gagnon, Richard E. Jones, Chandra Krintz, Philippe Mulet, Jan Vitek, Implementation Compilation Optimization of Object-Oriented Languages Programs and Systems., ECOOP Workshops 2007: 50-64
Orna Grumberg, Assaf Schuster, Avi Yadgar, 3-Valued Circuit SAT for STE with Automatic Refinement., ATVA 2007: 457-473
Ozcan Ozturk, Guilin Chen, Mahmut T. Kandemir, Mustafa Karaköy, Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems., CGO 2007: 232-243
Ozcan Ozturk, Mahmut T. Kandemir, Seung Woo Son, An ilp based approach to reducing energy consumption in nocbased CMPS., ISLPED 2007: 411-414
Pål Grønsund, Paal Engelstad, Moti Ayoun, Tor Skeie, Real Life Field Trial over a Pre-mobile WiMAX System with 4th Order Diversity., NEW2AN 2007: 121-132
Pål Grønsund, Paal Engelstad, Torbjørn Johnsen, Tor Skeie, The physical performance and path loss in a fixed WiMAX deployment., IWCMC 2007: 439-444
Pablo Abad, Valentin Puente, José-Ángel Gregorio, Pablo Prieto, Rotary router: an efficient architecture for CMP interconnection networks., ISCA 2007: 116-125
Panagiota Fatourou, Nikolaos D. Kallimanis, Time-optimal space-efficient single-scanner snapshots & multi-scanner snapshots using CAS., PODC 2007: 33-42
Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen, Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks., SAMOS 2007: 443-453
Paola Caymes-Scutari, Anna Morajko, Tomàs Margalef, Emilio Luque, Automatic Generation of Dynamic Tuning Techniques., Euro-Par 2007: 13-22
Paolo Montuschi, Javier D. Bruguera, Luigi Ciminiera, José-Alejandro Piñeiro, A Digit-by-Digit Algorithm for mth Root Extraction., IEEE Trans. Computers 56(12): 1696-1706 (2007)
Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne, Introduction of Architecturally Visible Storage in Instruction Set Extensions., IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 435-446 (2007)
Pascal Felber, Calton Pu, Aad P. A. van Moorsel, DOA 2007 PC Co-chairs' Message., OTM Conferences (1) 2007: 437
Patrick Th. Eugster, Pascal Felber, Fabrice Le Fessant, The "art" of programming gossip-based systems., Operating Systems Review 41(5): 37-42 (2007)
Paul Carpenter, David Ródenas, Xavier Martorell, Alex Ramírez, Eduard Ayguadé, A Streaming Machine Description and Programming Model., SAMOS 2007: 107-116
Paul Kaufmann, Marco Platzner, Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution., ARCS 2007: 199-208
Paul Kaufmann, Marco Platzner, MOVES: A Modular Framework for Hardware Evolution., AHS 2007: 447-454
Paul Lokuciejewski, Heiko Falk, Martin Schwarzer, Peter Marwedel, Henrik Theiling, Influence of procedure cloning on WCET prediction., CODES+ISSS 2007: 137-142
Paula Cecilia Fritzsche, Dolores Rexachs, Emilio Luque, Applying Data Mining to Define TSP Asymptotic Time Complexity., ICTAI (2) 2007: 189-192
Paula Cecilia Fritzsche, Dolores Rexachs, Emilio Luque, Extracting Knowledge to Predict TSP Asymptotic Time Complexity., ICDM Workshops 2007: 309-318
Paula Cecilia Fritzsche, Dolores Rexachs, Emilio Luque, A knowledge-based methodology to predict performance order of data-dependent applications., DMIN 2007: 359-368
Paula Cecilia Fritzsche, Dolores Rexachs, Emilio Luque, A Computational Approach to TSP Performance Prediction Using Data Mining., AINA Workshops (1) 2007: 252-259
Paulo Alexandre Crisóstomo Lopes, J. Germano, T. M. Almeida, Leonel Sousa, Moisés Simões Piedade, Filipe Cardoso, H. A. Ferreira, P. P. Freitas, A New Handheld Biochip-based Microsystem., ISCAS 2007: 2379-2382
Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, João M. P. Cardoso, Reconfigurable Computing: Architectures Tools and Applications Third International Workshop ARC 2007 Mangaratiba Brazil March 27-29 2007., Springer 2007
Pedro Garcia Lopez, Marc Sanchez Artigas, Jordi Pujol Ahull, The p2pWeb Model: A Glue for the Web, WETICE '07: Proceedings of the 16th IEEE International Workshops on Enabling Technologies: Infrastructure for Collaborative Enterprises, IEEE Computer Society, June 2007
Pedro Morillo, Silvia Rueda, Juan M. Orduña, José Duato, A Latency-Aware Partitioning Method for Distributed Virtual Environment Systems., IEEE Trans. Parallel Distrib. Syst. 18(9): 1215-1226 (2007)
Pedro Trancoso, Watt Matters Most? Design Space Exploration of High-Performance Microprocessors for Power-Performance Efficiency., Journal of Circuits Systems and Computers 16(3): 357-378 (2007)
Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala, Resource Conflict Detection in Simulation of Function Unit Pipelines., SAMOS 2007: 233-240
Pepijn J. de Langen, Ben H. H. Juurlink, Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors., SAMOS 2007: 75-85
Per Stenström, Introduction to Part 1., T. HiPEAC 1: 33 (2007)
Per Stenström, IPDPS Panel: Is the Multi-Core Roadmap going to Live Up to its Promises?, IPDPS 2007: 14
Per Stenström, Michael F. P. O'Boyle, François Bodin, Marcelo Cintra, Sally A. McKee, Transactions on High-Performance Embedded Architectures and Compilers I, Springer 2007
Peter Benner, Maribel Castillo, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Stabilizing large-scale generalized systems on parallel computers using multithreading and message-passing., Concurrency and Computation: Practice and Experience 19(4): 531-542 (2007)
Peter van Stralen, Andy D. Pimentel, Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration., ESTImedia 2007: 33-38
Petri Kukkala, Mikko Setälä, Tero Arpinen, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Implementing a WLAN video terminal using UML and fully automated design flow, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Philip Brisk, Ajay K. Verma, Paolo Ienne, Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design., ICCAD 2007: 172-179
Philip Brisk, Ajay K. Verma, Paolo Ienne, An optimistic and conservative register assignment heuristic for chordal graphs., CASES 2007: 209-217
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar, Enhancing FPGA Performance for Arithmetic Circuits., DAC 2007: 334-337
Philippe Faes, Mark Christiaens, Dirk Stroobandt, Mobility of Data in Distributed Hybrid Computing Systems., IPDPS 2007: 1-7
Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser, Massively parallel processing on a chip., Conf. Computing Frontiers 2007: 277-286
Philippe Millet, Jean-Claude Heudin, Web Mining in the EVA Intelligent Agent Architecture., Web Intelligence/IAT Workshops 2007: 368-371
Pierfrancesco Foglia, Cosimo Antonio Prete, Michele Zanda, Modelling Public Administration Portals., Encyclopedia of Portal Technologies and Applications 2007: 606-614
Pierfrancesco Foglia, F. Giuntoli, Cosimo Antonio Prete, Michele Zanda, Assisting e-government users with animated talking faces., Interactions 14(1): 24-26 (2007)
Piero Zappi, Elisabetta Farella, Luca Benini, Enhancing the spatial resolution of presence detection in a PIR based wireless surveillance network., AVSS 2007: 295-300
Pierre Boulet, Philippe Marquet, Éric Piel, Julien Taillard, Repetitive Allocation Modelling with MARTE., FDL 2007: 280-285
Pierre Michaud, André Seznec, Damien Fetis, Yiannakis Sazeides, Theofanis Constantinou, A study of thread migration in temperature-constrained multicores., TACO 4(2): (2007)
Prashant Agrawal, R. Srinivasa, Ajit N. Oke, Saurabh Vijay, A path based modeling approach for dynamic power estimation., ACM Great Lakes Symposium on VLSI 2007: 588-593
Prashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay, A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs., ISVLSI 2007: 389-394
Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal, Very wide register: an asymmetric register file organization for low power embedded processors., DATE 2007: 1066-1071
Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo, Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors., ISCAS 2007: 121-124
Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest, Semi Custom Design: A Case Study on SIMD Shufflers., PATMOS 2007: 433-442
Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors., ARCS 2007: 57-68
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung, Automatic On-chip Memory Minimization for Data Reuse, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Quan Shi, Ning Xi, Weihua Sheng, Recursive Measurement Process for Improving Accuracy of Dimensional Inspection of Automotive Body Parts., ICRA 2007: 4764-4769
R. González-del-Campo, F. Sáenz-Pérez, Programmed Search in a Timetabling Problem over Finite Domains, Electronic Notes in Theoretical Computer Science (ENTCS) , Volume 177, Elsevier Science Publishers B. V., June 2007
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, Comparing the latency performance of the DTable and DRR schedulers., IPDPS 2007: 1-8
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser, An MPSoC Performance Estimation Framework Using Transaction Level Modeling., RTCSA 2007: 525-533
Radu Prodan, Thomas Fahringer, Grid Computing Experiment Management Tool Integration and Scientific Workflows, Springer 2007
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Houcine Hassan, Pedro Lopez, Leakage Current Reduction in Data Caches on Embedded Systems, IPC '07: Proceedings of the The 2007 International Conference on Intelligent Pervasive Computing, IEEE Computer Society, October 2007
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors., SBAC-PAD 2007: 62-68
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato, VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors., PACT 2007: 429
Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou, Synthetic Trace-Driven Simulation of Cache Memory., AINA Workshops (1) 2007: 764-771
Raimund Kirner, Jens Knoop, Adrian Prantl, Markus Schordan, Ingomar Wenzel, WCET Analysis: The Annotation Language Challenge., WCET 2007
Rami Rom, Jacob Erel, Michael Glikson, Randy A. Lieberman, Kobi Rosenblum, Ofer Binah, Ran Ginosar, David L. Hayes, Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme., IEEE Transactions on Neural Networks 18(2): 542-550 (2007)
Ramon Bertran, John Cavazos, Nacho Navarro, Mike O'Boyle, Synergy between Compiler Optimizations and Partitioning on the Cell processor., ACACES 2007
Ramon Nou, Ferran Julià, David Carrera, Kevin Hogan, Jordi Caubet, Jesús Labarta, Jordi Torres, Monitoring and Analysis Framework for Grid Middleware., PDP 2007: 129-133
Raphaël Chand, Pascal Felber, Minos N. Garofalakis, Tree-Pattern Similarity Estimation for Scalable Content-based Routing., ICDE 2007: 1016-1025
Raul Wirz, Raúl Marín, José M. Claver, Josep Fernández, Enric Cervera, Transport Protocols for Remote Programming of Network Robots within the context of Telelaboratories for Education: A Comparative Analysis., ICCCN 2007: 1315-1320
Ravi K. Garimella, Weihua Sheng, Dynamic localization of multiple mobile subjects in wireless Ad Hoc networks., IROS 2007: 2003-2008
Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor, Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method., IEEE Trans. VLSI Syst. 15(8): 952-962 (2007)
Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato, A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures., HPCA 2007: 157-168
Ricardo Fernandez-Pascual, Jose M. Garcia, Manuel E. Acacio, Jose Duato, A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures, HPCA '07: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, IEEE Computer Society, February 2007
Ricardo Ferreira, Alisson Garcia, Tiago Teixeira, João M. P. Cardoso, A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures., ISVLSI 2007: 61-66
Ricardo Menotti, Eduardo Marques, João M. P. Cardoso, Aggressive Loop Pipelining for Reconfigurable Architectures., FPL 2007: 501-502
Richard Tran Mills, Chuan Yue, Andreas Stathopoulos, Dimitrios S. Nikolopoulos, Runtime and Programming Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory., J. Grid Comput. 5(2): 213-234 (2007)
Richard Vincent Bennett, Alastair Colin Murray, Björn Franke, Nigel P. Topham, Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems., LCTES 2007: 83-92
Rickard Holsmark, Shashi Kumar, Corrections to Chen and Chiu's Fault Tolerant Routing Algorithm for Mesh Networks., J. Inf. Sci. Eng. 23(6): 1649-1662 (2007)
Rob Hoes, Twan Basten, Chen-Khong Tham, Marc Geilen, Henk Corporaal, Analysing qos trade-offs in wireless sensor networks., MSWiM 2007: 60-69
Robbie Schaefer, Wolfgang Mueller, Andres Marán López, Daniel Díaz Sánchez, Using smart cards for secure and device independent user interfaces, Mobility '07: Proceedings of the 4th international conference on mobile technology, applications, and systems and the 1st international symposium on Computer human interaction in mobile technology, ACM, September 2007
Robert D. Mullins, Simon W. Moore, Demystifying Data-Driven and Pausible Clocking Schemes., ASYNC 2007: 175-185
Robert Pyka, Christoph Faßbach, Manish Verma, Heiko Falk, Peter Marwedel, Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications., SCOPES 2007: 41-50
Roberto Giorgi, Paolo Bennati, Reducing leakage in power-saving capable caches for embedded systems by using a filter cache, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems., SBAC-PAD 2007: 263-270
Roberto R. Osorio, Javiefr D. Bruguera, Entropy Coding on a Programmable Processor Array for Multimedia SoC, IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP)
Roberto R. Osorio, Javier D. Bruguera, Entropy Coding on a Programmable Processor Array for Multimedia SoC., ASAP 2007: 222-227
Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis, A Quantitative Prediction Model for Hardware/Software Partitioning., FPL 2007: 735-739
Ron Gabor, Shlomo Weiss, Avi Mendelson, Fairness enforcement in switch on event multithreading., TACO 4(3): (2007)
Rong Huang, Shurong Tong, Weihua Sheng, Zhun Fan, A Problem Solving Environment for Combinatorial Optimization Based on Parallel Meta-heuristics., CIRA 2007: 432-437
Rosa Filgueira, David E. Singh, Florin Isaila, Jesús Carretero, Antonio Garcia Loureiro, Optimization and evaluation of parallel I/O in BIPS3D parallel irregular application., IPDPS 2007: 1-8
Rosa M. Badia, Christian Pérez, Artur Andrzejak, Alvaro Arenas, Topic 6 Grid and Cluster Computing., Euro-Par 2007: 359
Rosa M. Badia, Raúl Sirvent, Marian Bubak, Wlodzimierz Funika, Piotr Machner, Performance monitoring of GRID superscalar with OCM-G/G-PM: improvements., CoreGRID Workshop - Making Grids Work 2007: 273-283
Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon, QNoC Asynchronous Router with Dynamic Virtual Channel Allocation., NOCS 2007: 218
Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny, High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link., ASYNC 2007: 3-14
Rubing Duan, Radu Prodan, Thomas Fahringer, Performance and cost optimization for multiple large-scale grid workflow applications., SC 2007: 12
Rui Rodrigues, João M. P. Cardoso, On Pipelining Sequences of Data-Dependent Loops., J. UCS 13(3): 419-439 (2007)
Rui Rodrigues, Joao M. P. Cardoso, Pedro C. Diniz, A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli, Timing-Error-Tolerant Network-on-Chip Design Methodology., IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1297-1310 (2007)
Ryan Johnson, Nikos Hardavellas, Ippokratis Pandis, Naju Mancheril, Stavros Harizopoulos, Kivanc Sabirli, Anastassia Ailamaki, Babak Falsafi, To Share or Not To Share?, VLDB 2007: 351-362
Ryan Johnson, Stavros Harizopoulos, Nikos Hardavellas, Kivanc Sabirli, Ippokratis Pandis, Anastasia Ailamaki, Naju G. Mancheril, Babak Falsafi, To share or not to share?, VLDB '07: Proceedings of the 33rd international conference on Very large data bases, VLDB Endowment, September 2007
Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser, Multiple Abstraction Views of FPGA to Map Parallel Applications., ReCoSoC 2007: 90-97
Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser, A Design Flow to Map Parallel Applications onto FPGAs., FPL 2007: 605-608
Sérgio F. Martins, Leonel Sousa, João Martins, Additive Logistic Regression Applied to Retina Modelling., ICIP (3) 2007: 309-312
S. Arash Ostadzadeh, B. Maryam Elahi, Zeinab Zeinalpour, M. Amir Moulavi, Koen Bertels, A Two-phase Practical Parallel Algorithm for Construction of Huffman Codes., PDPTA 2007: 284-291
S. Bartolini, P. Foglia, C. A. Prete, MEmory performance: DEaling with applications, systems and architecture, SIGARCH Computer Architecture News , Volume 35 Issue 4, ACM, September 2007
S. Corbetta, Fabrizio Ferrandi, Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto, Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System., ISVLSI 2007: 457-458
S. Estévez-Martín, A. J. Fernández, T. Hortalá-González, M. Rodríguez-Artalejo, F. Sáenz-Pérez, R. del Vado-Vírseda, A Proposal for the Cooperation of Solvers in Constraint Functional Logic Programming, Electronic Notes in Theoretical Computer Science (ENTCS) , Volume 188, Elsevier Science Publishers B. V., July 2007
S. Shervin Ostadzadeh, Fereidoon Shams Aliee, S. Arash Ostadzadeh, An MDA-Based Generic Framework to Address Various Aspects of Enterprise Architecture., SCSS (1) 2007: 455-460
Sabina Serbu, Peter Kropf, Pascal Felber, Improving the Dependability of Prefix-Based Routing in DHTs., OTM Conferences (1) 2007: 206-225
Sabina Serbu, Silvia Bianchi, Peter G. Kropf, Pascal Felber, Dynamic Load Sharing in Peer-to-Peer Systems: When Some Peers Are More Equal than Others., IEEE Internet Computing 11(4): 53-61 (2007)
Sabine Glesner, Jens Knoop, Rolf Drechsler, Preface., Electr. Notes Theor. Comput. Sci. 190(4): 1-2 (2007)
Sabri Pllana, Ivona Brandic, Siegfried Benkner, Performance Modeling and Prediction of Parallel and Distributed Computing Systems: A Survey of the State of the Art., CISIS 2007: 279-284
Safouan Taha, Ansgar Radermacher, Sébastien Gérard, Jean-Luc Dekeyser, MARTE: UML-based Hardware Design from Modelling to Simulation., FDL 2007: 274-279
Safouan Taha, Ansgar Radermacher, Sebastien Gerard, Jean-Luc Dekeyser, An Open Framework for Detailed Hardware Modeling., SIES 2007: 118-125
Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero, PPM Reduction on Embedded Memories in System on Chip., European Test Symposium 2007: 85-90
Salman A. Khan, Andries P. Engelbrecht, A new fuzzy operator and its application to topology design of distributed local area networks, Information Sciences: an International Journal , Volume 177 Issue 13, Elsevier Science Inc., July 2007
Salman Khan, Polychronis Xekalakis, John Cavazos, Marcelo Cintra, Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore Systems., PACT 2007: 327-338
Salvatore Carta, Andrea Acquaviva, Pablo Garcia Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias, Multi-processor operating system emulation framework with thermal feedback for systems-on-chip., ACM Great Lakes Symposium on VLSI 2007: 311-316
Salvatore Carta, Andrea Alimonda, Alessandro Pisano, Andrea Acquaviva, Luca Benini, A control theoretic approach to energy-efficient pipelined computation in MPSoCs., ACM Trans. Embedded Comput. Syst. 6(4): (2007)
Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal, Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs., DAC 2007: 777-782
Sandro Bartolini, Cinzia Castagnini, Enrico Martinelli, Inclusion of a Montgomery Multiplier Unit into an Embedded Processor’s Datapath to Speed-up Elliptic Curve Cryptography., IAS 2007: 95-100
Sanna Määttä, Jari Nurmi, Experiences of Using Object Oriented Programming Methods in High Level Network-on-Chip and System-on-Chip Design., ReCoSoC 2007: 84-89
Sarah Thompson, Alan Mycroft, Abstract interpretation of combinational asynchronous circuits., Sci. Comput. Program. 64(1): 166-183 (2007)
Sasa Tomic, Adrián Cristal, Osman S. Unsal, Mateo Valero, Hardware Transactional Memory with Operating System Support HTMOS., Euro-Par Workshops 2007: 8-17
Sascha Uhrig, Jörg Mische, Theo Ungerer, An IP Core for Embedded Java Systems., SAMOS 2007: 263-272
Sascha Uhrig, Jörg Wiese, jamuth: an IP processor core for embedded Java real-time systems., JTRES 2007: 230-237
Sean Rul, Hans Vandierendonck, Koen De Bosschere, Function level parallelism driven by data dependencies, SIGARCH Computer Architecture News , Volume 35 Issue 1, ACM, March 2007
Sebastián Reyes, Camelia Muñoz-Caro, Alfonso Niño, Rosa M. Badia, José M. Cela, Performance of computationally intensive parameter sweep applications on Internet-based Grids of computers: the mapping of molecular potential energy hypersurfaces., Concurrency and Computation: Practice and Experience 19(4): 463-481 (2007)
Sebastian Schuster, Uwe Brinkschulte, Model-Driven Development of Ubiquitous Applications for Sensor-Actuator-Networks with Abstract State Machines., SEUS 2007: 527-536
Sergio Barrachina, Peter Benner, Enrique S. Quintana-Ortí, Efficient algorithms for generalized algebraic Bernoulli equations based on the matrix sign function., Numerical Algorithms 46(4): 351-368 (2007)
Sergio Romero, Maria A. Trenas, Eladio Gutierrez, Emilio L. Zapata, Locality-improved FFT implementation on a graphics processor, ISCGAV'07: Proceedings of the 7th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision, World Scientific and Engineering Academy and Society (WSEAS), August 2007
Sergio Saponara, Esa Petri, Marco Tonarelli, Iacopo Del Corona, Luca Fanucci, FPGA-based networking systems for high data-rate and reliable in-vehicle communications., DATE 2007: 480-485
Sergio Saponara, Luca Fanucci, Stefano Marsi, Giovanni Ramponi, Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing., J. Real-Time Image Processing 1(4): 267-283 (2007)
Seung Woo Son, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir, Alok N. Choudhary, Compiler-Directed Energy Optimization for Parallel Disk Based Systems., IEEE Trans. Parallel Distrib. Syst. 18(9): 1241-1257 (2007)
Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun, A practical FPGA-based framework for novel CMP research., FPGA 2007: 116-125
Seyed Masoud Sadjadi, J. Martínez, T. Soldo, L. Atencio, Rosa M. Badia, Jorge Ejarque, Improving Separation of Concerns in the Development of Scientific Applications., SEKE 2007: 456-461
Shabnam Mirshokraie, Mojtaba Sabeghi, Mahmoud Naghibzadeh, Koen Bertels, Performance Evaluation of Real-Time Message Delivery in RDM Algorithm., ICNS 2007: 74
Shady Copty, Itai Jaeger, Yoav Katz, Michael Vinov, Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation., DAC 2007: 891-895
Shashi Kumar, Sanjeev Kumar, Prakash, Ravi Shankar, M. K. Tiwari, Shashi Bhushan Kumar, Prediction of flow stress for carbon steels using recurrent self-organizing neuro fuzzy networks., Expert Syst. Appl. 32(3): 777-788 (2007)
Shekhar Borkar, Norman P. Jouppi, Per Stenström, Microprocessors in the era of terascale integration., DATE 2007: 237-242
Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry, Chris Wilkerson, Scheduling threads for constructive cache sharing on CMPs., SPAA 2007: 105-115
Shinichi Yamagiwa, Leonel Sousa, Design and implementation of a stream-based distributedcomputing platform using graphics processing units., Conf. Computing Frontiers 2007: 197-204
Shinichi Yamagiwa, Leonel Sousa, Caravela: A Novel Stream-Based Distributed Computing Environment., IEEE Computer 40(5): 70-77 (2007)
Shinichi Yamagiwa, Leonel Sousa, Diogo Antão, Data buffering optimization methods toward a uniform programming interface for gpu-based applications., Conf. Computing Frontiers 2007: 205-212
Shinichi Yamagiwa, Leonel Sousa, Tomás Brandão, Meta-Pipeline: A New Execution Mechanism for Distributed Pipeline Processing., ISPDC 2007: 17-24
Shun Long, Grigori Fursin, Björn Franke, A Cost-Aware Parallel Workload Allocation Approach Based on Machine Learning Techniques., NPC 2007: 506-515
Sid Ahmed Ali Touati, On the Periodic Register Need in Software Pipelining., IEEE Trans. Computers 56(11): 1493-1504 (2007)
Siham Tabik, Jesús M. Vías, Emilio L. Zapata, Luis F. Romero, Fast Insolation Computation in Large Territories., International Conference on Computational Science (1) 2007: 54-61
Silvia Bianchi, Ajoy Kumar Datta, Pascal Felber, Maria Gradinariu, Stabilizing Peer-to-Peer Spatial Filters., ICDCS 2007: 27
Silvia Bianchi, Pascal Felber, Maria Gradinariu, Content-Based Publish/Subscribe Using Distributed R-Trees., Euro-Par 2007: 537-548
Silvia Rueda, Pedro Morillo, Juan M. Orduña, A Peer-To-Peer platform for simulating distributed virtual environments., ICPADS 2007: 1-8
Silvia Rueda, Pedro Morillo, Juan M. Orduña, José Duato, A genetic approach for adding QoS to distributed virtual environments., Computer Communications 30(4): 731-739 (2007)
Silvia Rueda, Pedro Morillo, Juan M. Orduña, José Duato, On the Characterization of Peer-To-Peer Distributed Virtual Environments., VR 2007: 107-114
Silvia Rueda, Pedro Morillo, Juan M. Orduna, A Saturation Avoidance Technique for Peer-to-Peer Distributed Virtual Environments, CW '07: Proceedings of the 2007 International Conference on Cyberworlds, IEEE Computer Society, October 2007
Simon Kluyskens, Lieven Eeckhout, Branch History Matching: Branch Predictor Warmup for Sampled Simulation., HiPEAC 2007: 153-167
Simon Marlow, Alexey Rodriguez Yakushev, Simon L. Peyton Jones, Faster laziness using dynamic pointer tagging., ICFP 2007: 277-288
Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini, Reducing Interconnect Cost in NoC through Serialized Asynchronous Links., NOCS 2007: 219
Simone Medardoni, Davide Bertozzi, Enrico Macii, Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies., ISLPED 2007: 159-164
Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto, Interactive presentation: Capturing the interaction of the communication memory and I/O subsystems in memory-centric industrial MPSoC platforms., DATE 2007: 660-665
Soledad Escolar, Jesús Carretero, Florin Isaila, Félix García Carballeira, A driver model based on Linux for TinyOS., SIES 2007: 361-364
Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich, Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS 2007 Salzburg Austria September 30 - October 3 2007, ACM 2007
Spiros Antonatos, Kostas Anagnostakis, Evangelos Markatos, Honey@home: a new approach to large-scale threat monitoring, WORM '07: Proceedings of the 2007 ACM workshop on Recurring malcode, ACM, November 2007
Spyros Antonatos, Periklis Akritidis, Evangelos P. Markatos, Kostas G. Anagnostakis, Defending against hitlist worms using network address space randomization., Computer Networks 51(12): 3471-3490 (2007)
Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen Boyd, Giovanni De Micheli, Temperature-aware processor frequency assignment for MPSoCs using convex optimization., CODES+ISSS 2007: 111-116
Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo, Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors., IEEE Trans. VLSI Syst. 15(8): 869-880 (2007)
Srinivasan Murali, Luca Benini, Giovanni De Micheli, An Application-Specific Design Methodology for On-Chip Crossbar Generation., IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1283-1296 (2007)
Stamatis Vassiliadis, Filipa Duarte, Stephan Wong, A Load/Store Unit for a Memcpy Hardware Accelerator., FPL 2007: 537-541
Stamatis Vassiliadis, Ioannis Sourdis, FLUX interconnection networks on demand., Journal of Systems Architecture 53(10): 777-793 (2007)
Stamatis Vassiliadis, Mladen Berekovic, Timo D. Hämäläinen, Embedded Computer Systems: Architectures Modeling and Simulation 7th International Workshop SAMOS 2007 Samos Greece July 16-19 2007 Proceedings, Springer 2007
Stefan Farfeleder, Andreas Krall, R. Nigel Horspool, Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures., Journal of Systems Architecture 53(8): 501-510 (2007)
Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, HySim: a fast simulation framework for embedded software development., CODES+ISSS 2007: 75-80
Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations., DATE 2007: 1349-1354
Stefan Raaijmakers, Stephan Wong, Run-time Partial Reconfiguration for Removal Placement and Routing on the Virtex-II-Pro., FPL 2007: 679-683
Stefano Baraldi, Alberto Del Bimbo, Lea Landucci, Nicola Torpei, Omar Cafini, Elisabetta Farella, Augusto Pieracci, Luca Benini, Introducing tangerine: a tangible interactive natural environment., ACM Multimedia 2007: 831-834
Stefano Ceri, Cristiana Bolchini, Daniele Braga, Marco Brambilla, Alessandro Campi, Sara Comai, Piero Fraternali, Pier Luca Lanzi, Marco Masseroli, Maristella Matera, Mauro Negri, Giuseppe Pelagatti, , Data and web management research at Politecnico di Milano., SIGMOD Record 36(4): 43-48 (2007)
Stephane Piskorski, Lionel Lacassagne, Samir Bouaziz, Daniel Etiemble, Customizing CPU instructions for embedded vision systems, ASAP '07: Proceedings of the 2007 IEEE International Conf. on Application-Specific Systems, Architectures and Processors (ASAP) - Volume 00 , Volume 00, IEEE Computer Society, July 2007
Stephen R. Schach, Tokunbo O. S. Adeshiyan, Daniel Balasubramanian, Gabor Madl, Esteban Osses, Sameer Singh, Karlkim Suwanmongkol, Minhui Xie, Dror G. Feitelson, Common coupling and pointer variables with application to a Linux case study., Software Quality Journal 15(1): 99-113 (2007)
Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton, A synthesizable datapath-oriented embedded FPGA fabric., FPGA 2007: 33-41
Stewart Massie, Nirmalie Wiratunga, Susan Craw, Alessandro Donati, Emmanuel Vicari, From Anomaly Reports to Cases., ICCBR 2007: 359-373
Stijn Eyerman, Lieven Eeckhout, A Memory-Level Parallelism Aware Fetch Policy for SMT Processors., HPCA 2007: 240-249
Stijn Eyerman, Lieven Eeckhout, James E. Smith, Studying Compiler-Microarchitecture Interactions through Interval Analysis., PACT 2007: 406
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith, A Top-Down Approach to Architecting CPI Component Performance Counters., IEEE Micro 27(1): 84-93 (2007)
Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis, Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement., Journal of Systems Architecture 53(7): 417-436 (2007)
Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor, Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns., DATE 2007: 1036-1041
Su-Shin Ang, George Constantinides, Wayne Luk, Peter Cheung, A Hybrid Memory Sub-system for Video Coding Applications, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk, Real-time hardware acceleration of the trace transform., J. Real-Time Image Processing 2(4): 235-248 (2007)
Sungroh Yoon, Luca Benini, Giovanni De Micheli, Co-clustering: A Versatile Tool for Data Analysis in Biomedical Informatics., IEEE Transactions on Information Technology in Biomedicine 11(4): 493-494 (2007)
Sutjipto Arifin, Peter Y. K. Cheung, A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional information., ACM Multimedia 2007: 68-77
Sutjipto Arifin, Peter Y. K. Cheung, A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information., ICIP (6) 2007: 333-336
Sutjipto Arifin, Peter Y. K. Cheung, A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on "Working Memory"., ICSC 2007: 147-154
Suzanne Rivoire, Mehul A. Shah, Parthasarathy Ranganathan, Christos Kozyrakis, JouleSort: a balanced energy-efficiency benchmark., SIGMOD Conference 2007: 365-376
Suzanne Rivoire, Mehul A. Shah, Parthasarathy Ranganathan, Christos Kozyrakis, Justin Meza, Models and Metrics to Enable Energy-Efficiency Optimizations., IEEE Computer 40(12): 39-48 (2007)
Sven Karlsson, Stavros Passas, George Kotsis, Angelos Bilas, MultiEdge: An Edge-based Communication Subsystem for Scalable Commodity Servers., IPDPS 2007: 1-10
Sven Verdoolaege, Rachid Seghir, Kristof Beyls, Vincent Loechner, Maurice Bruynooghe, Counting Integer Points in Parametric Polytopes Using Barvinok's Rational Functions., Algorithmica 48(1): 37-66 (2007)
Sven-Arne Reinemo, Tor Skeie, Effective Shortest Path Routing for Gigabit Ethernet., ICC 2007: 6419-6424
T. Dias, S. Momcilovic, N. Roma, L. Sousa, Adaptive motion estimation processor for autonomous video devices, EURASIP Journal on Embedded Systems , Volume 2007 Issue 1, Hindawi Publishing Corp., January 2007
Taewhan Kim, Pascal Sainrat, Steven S. Lumetta, Nacho Navarro, Proceedings of the 2007 International Conference on Compilers Architecture and Synthesis for Embedded Systems CASES 2007 Salzburg Austria September 30 - October 3 2007, ACM 2007
Talal Bonny, Jörg Henkel, Instruction splitting for efficient code compression, DAC '07: Proceedings of the 44th annual conference on Design automation, ACM, June 2007
Talal Bonny, Joerg Henkel, Efficient code density through look-up table compression, DATE '07: Proceedings of the conference on Design, automation and test in Europe, EDA Consortium, April 2007
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero, Energy saving through a simple load control mechanism, SIGARCH Computer Architecture News , Volume 35 Issue 4, ACM, September 2007
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero, Runahead Threads: Reducing Resource Contention in SMT Processors., PACT 2007: 423
Tarik Saidani, Lionel Lacassagne, Joel Falcou, Claude Tadonki, Parallelization Schemes for Memory Optimization on the Cell Processor : A Case Study on the Harris Corner Detector, PACT MEDEA
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, Taj Muhammad Khan, Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor., ISPA 2007: 104-112
Tarik Saidani, Stéphane Piskorski, Lionel Lacassagne, Samir Bouaziz, Parallelization schemes for memory optimization on the cell processor: a case study of image processing algorithm, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Taylan Yemliha, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir, Vijay Degalahal, Compiler-Directed Code Restructuring for Operating with Compressed Arrays., VLSI Design 2007: 221-226
Teemu Pitkänen, Tero Partanen, Jarmo Takala, Low-Power Twiddle Factor Unit for FFT Computation., SAMOS 2007: 65-74
Tero Arpinen, Mikko Setälä, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Modeling Embedded Software Platforms with a UML Profile., FDL 2007: 237-242
Terrence S. T. Mak, K. P. Lam, H. S. Ng, G. Rachmuth, C.-S. Poon, A Current-Mode Analog Circuit for Reinforcement Learning Problems., ISCAS 2007: 1301-1304
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, K. P. Lam, A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing., NOCS 2007: 173-182
Tessa E. Pronk, Andy D. Pimentel, Marco Roos, Timo M. Breit, Taking the example of computer systems engineering for the analysis of biological cell systems., Biosystems 90(3): 623-635 (2007)
Tessa E. Pronk, Simon Polstra, Andy D. Pimentel, Timo M. Breit, Evaluating the Design of Biological Cells Using a Computer Workbench., Annual Simulation Symposium 2007: 88-98
Théodore Marescaux, Erik Brockmeyer, Henk Corporaal, The Impact of Higher Communication Layers on NoC Supported MP-SoCs., NOCS 2007: 107-116
Théodore Marescaux, Henk Corporaal, Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT., DAC 2007: 116-121
Thilo Streichert, Michael Glaß, Christian Haubelt, Jürgen Teich, Design space exploration of reliable networked embedded systems., Journal of Systems Architecture 53(10): 751-763 (2007)
Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg, Strategies for Compiling µ TC to Novel Chip Multiprocessors., SAMOS 2007: 127-138
Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos, Mechanisms for store-wait-free multiprocessors., ISCA 2007: 266-277
Thomas Fahringer, Christoph Anthes, Alexis Arragon, Arton Lipaj, Jens Müller-Iden, Christopher J. Rawlings, Radu Prodan, Mike Surridge, The edutain@grid Project., GECON 2007: 182-187
Thomas J. Ashby, Anthony D. Kennedy, Stephen M. Watt, Generation and optimisation of code using coxeter lattice paths., PASCO 2007: 1-10
Thomas Piquet, Olivier Rochecouste, André Seznec, Exploiting Single-Usage for Effective Memory Management., Asia-Pacific Computer Systems Architecture Conference 2007: 90-101
Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor, Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals., SAMOS 2007: 322-332
Thuy Duong Vu, Chris R. Jesshope, Formalizing SANE Virtual Processor in Thread Algebra., ICFEM 2007: 345-365
Tiago Dias, Nuno Roma, Leonel Sousa, Miguel Ribeiro, Reconfigurable architectures and processors for real-time video motion estimation., J. Real-Time Image Processing 2(4): 191-205 (2007)
Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguadé, Fabrizio Gagliardi, Burton Smith, Mateo Valero, Transactional Memory: An Overview., IEEE Micro 27(3): 8-29 (2007)
Tim Harris, Satnam Singh, Feedback directed implicit parallelism., ICFP 2007: 251-264
Tim Kindberg, Timothy Jones, \"Merolyn the Phone\": A Study of Bluetooth Naming Practices (Nominated for the Best Paper Award)., Ubicomp 2007: 318-335
Tim Todman, Wayne Luk, Domain Specific Transformations for Hardware Ray Tracing., CPA 2007: 479-492
Timo Alho, Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen, Compact hardware design of Whirlpool hashing core., DATE 2007: 1247-1252
Timo Alho, Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen, Compact modular exponentiation accelerator for modern FPGA devices., Computers & Electrical Engineering 33(5-6): 383-391 (2007)
Timo D. Hämäläinen, Stephan Wong, John Glossner, Stamatis Vassiliadis, Editorial., Journal of Systems Architecture 53(10): 677-678 (2007)
Timo Vanhatupa, Marko Hännikäinen, Timo D. Hämäläinen, Evaluation of throughput estimation models and algorithms for WLAN frequency planning., Computer Networks 51(11): 3110-3124 (2007)
Timo Viero, Kim Rounioja, Teemu Sipilä, Raimo Verkasalo, Jarmo Takala, Jorma Lilleberg, Dual Antenna Receivers for High Data Rate Terminals, Wireless Personal Communications: An International Journal , Volume 43 Issue 2, Kluwer Academic Publishers, October 2007
Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration, FCCM '07: Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, April 2007
Tobias Schumacher, Enno Lübbers, Paul Kaufmann, Marco Platzner, Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster., PARCO 2007: 749-756
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney, Understanding Measurement Perturbation in Trace-based Data., IPDPS 2007: 1-6
Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan, Time Interpolation: So Many Metrics So Few Registers., MICRO 2007: 286-300
Tom Vander Aa, Bing-Feng Mei, Bjorn De Sutter, A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots, CASES '07: Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, ACM, September 2007
Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter, A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots., CASES 2007: 229-237
Tommaso Cucinotta, Luigi Palopoli, Feedback Scheduling for Pipelines of Tasks., HSCC 2007: 131-144
Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Friedbert Berens, Andreas Ruegg, A Survey on LDPC Codes and Decoders for OFDM-based UWB Systems., VTC Spring 2007: 1549-1553
Torben Brack, Matthias Alles, Timo Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L'Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci, Low complexity LDPC code decoders for next generation standards., DATE 2007: 331-336
Torvald Riegel, Christof Fetzer, Heiko Sturzrehm, Pascal Felber, From causal to z-linearizable transactional memory., PODC 2007: 340-341
Torvald Riegel, Christof Fetzer, Pascal Felber, Time-based transactional memory with scalable time bases., SPAA 2007: 221-228
Tsenka Stoyanova, Fotis Kerasiotis, Aggeliki S. Prayati, George Papadopoulos, Evaluation of impact factors on RSS accuracy for localization and tracking applications., MOBIWAC 2007: 9-16
Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala, Stride Permutation Networks for Array Processors., VLSI Signal Processing 49(1): 51-71 (2007)
Utpal Banerjee, José Moreira, Michel Dubois, Per Stenström, Proceedings of the 4th Conference on Computing Frontiers 2007 Ischia Italy May 7-9 2007, ACM 2007
Uwe Brinkschulte, Mathias Pacher, Alexander von Renteln, Towards an Artificial Hormone System for Self-organizing Real-Time Task Allocation., SEUS 2007: 339-347
Uwe Brinkschulte, Sunggu Lee, Editorial., Real-Time Systems 36(1-2): 1-2 (2007)
Víctor H. Escobar-Jeria, María J. Martín-Bautista, Daniel Sánchez, María-Amparo Vila, Web Usage Mining Via Fuzzy Logic Techniques, IFSA '07: Proceedings of the 12th international Fuzzy Systems Association world congress on Foundations of Fuzzy Logic and Soft Computing, Springer-Verlag, June 2007
Valentin Puente, José-Ángel Gregorio, Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks., IEEE Trans. Parallel Distrib. Syst. 18(6): 776-788 (2007)
Valery Sklyarov, Iouliia Skliarova, Encoding Algorithms for Logic Synthesis., AICCSA 2007: 359-366
Valery Sklyarov, Iouliia Skliarova, Reuse Technique in Hardware Design., IRI 2007: 36-41
Valery Sklyarov, Iouliia Skliarova, Manuel Almeida, Bruno Figueiredo Pimentel, A prototyping system for mobile devices., IWCMC 2007: 505-510
Vanderlei Bonato, Rafael Peron, Denis F. Wolf, José A. M. de Holanda, Eduardo Marques, João M. P. Cardoso, An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics., SIES 2007: 148-155
Vasilis F. Pavlidis, Eby G. Friedman, 3-D Topologies for Networks-on-Chip., IEEE Trans. VLSI Syst. 15(10): 1081-1090 (2007)
Vassilis Dimopoulos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems., ICSAMOS 2007: 186-193
Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis, Prototyping Efficient Interprocessor Communication Mechanisms., ICSAMOS 2007: 26-33
Vassos Soteriou, Li-Shiuan Peh, Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks., IEEE Trans. Parallel Distrib. Syst. 18(3): 393-408 (2007)
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh, Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks., IEEE Trans. VLSI Syst. 15(8): 855-868 (2007)
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh, Software-directed power-aware interconnection networks., TACO 4(1): (2007)
Veerle Desmet, Hans Vandierendonck, Koen De Bosschere, Clustered indexing for branch predictors., Microprocessors and Microsystems 31(3): 168-177 (2007)
Vicenç Beltran, Jordi Torres, Eduard Ayguadé, Improving disk bandwidth-bound applications through main memory compression, MEDEA '07: Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2007
Vijayanand Nagarajan, Rajiv Gupta, Matias Madou, Xiangyu Zhang, Bjorn De Sutter, Matching Control Flow of Program Versions., ICSM 2007: 84-93
Viktor Yarmolenko, Rizos Sakellariou, Towards increased expressiveness in service level agreements., Concurrency and Computation: Practice and Experience 19(14): 1975-1990 (2007)
Vincenzo Catania, Maurizio Palesi, Davide Patti, Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario., Journal of Circuits Systems and Computers 16(5): 819-846 (2007)
Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto, An adaptive genetic algorithm for dynamically reconfigurable modules allocation., VLSI-SoC 2007: 128-133
Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Dynamic Reconfigurability in Embedded System Design., ISCAS 2007: 2734-2737
Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert, Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux., IPDPS 2007: 1-8
Vitaliy Tykhomyrov, Alexander Sayenko, Henrik Martikainen, Olli Alanen, Timo Hämäläinen, Performance Evaluation of the IEEE 802.16 ARQ Mechanism., NEW2AN 2007: 148-161
W. A. Rajitha Jayaruwan Weerakkody, Warnakulasuriya Anil Chandana Fernando, José Luis Martínez, Pedro Cuenca, Francisco J. Quiles, An Iterative Refinement Technique for Side Information Generation in DVC., ICME 2007: 164-167
W. G. Osborne, Ray C. C. Cheung, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer, Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems., FPL 2007: 617-620
Weihua Sheng, Girma S. Tewolde, Robot Workload Distribution in Active Sensor Networks., CIRA 2007: 224-229
Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. , Implicitly Parallel Programming Models for Thousand-Core Microprocessors., DAC 2007: 754-759
Werner Dubitzky, Assaf Schuster, Peter M. A. Sloot, Michael Schroeder, Mathilde Romberg, Distributed High-Performance and Grid Computing in Computational Biology International Workshop GCCB 2006 Eilat Israel January 21 2007 Proceeding, Springer 2007
Wheeler Ruml, Minh B. Do, Best-first utility-guided search, IJCAI'07: Proceedings of the 20th international joint conference on Artifical intelligence, Morgan Kaufmann Publishers Inc., January 2007
Wim Heirman, Joni Dambre, I. Artundo, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan M. Van Campenhout, Predicting reconfigurable interconnect performance in distributed shared-memory systems., Integration 40(4): 382-393 (2007)
Wim Heirman, Joni Dambre, Jan Van Campenhout, Synthetic traffic generation as a tool for dynamic interconnect evaluation., SLIP 2007: 65-72
Wojciech Kabacinski, Marek Michalski, Achille Pattavina, The Control Algorithm and WSNB Operation of Log2(N 1 p) Switching Fabrics., GLOBECOM 2007: 2374-2378
Wolfgang Trumler, Andreas Pietzowski, Benjamin Satzger, Theo Ungerer, Adaptive Self-optimization in Distributed Dynamic Environments., SASO 2007: 320-323
Wolfgang Trumler, Jörg Ehrig, Andreas Pietzowski, Benjamin Satzger, Theo Ungerer, A Distributed Self-healing Data Store., ATC 2007: 458-467
Woongki Baek, Chi Cao Minh, Martin Trautmann, Christos Kozyrakis, Kunle Olukotun, The OpenTM Transactional Application Programming Interface., PACT 2007: 376-387
Woongki Baek, JaeWoong Chung, Chi Cao Minh, Christos Kozyrakis, Kunle Olukotun, Towards soft optimization techniques for parallel cognitive applications., SPAA 2007: 59-60
Xavier Teruel, Xavier Martorell, Alejandro Duran, Roger Ferrer, Eduard Ayguadé, Support for OpenMP tasks in Nanos v4., CASCON 2007: 256-259
Xiaoxuan She, Mark Zwolinski, A novel self-routing reconfigurable fault-tolerant cell array., AHS 2007: 725-731
Xin Wang, Tapani Ahonen, Jari Nurmi, Applying CDMA Technique to Network-on-Chip., IEEE Trans. VLSI Syst. 15(10): 1091-1100 (2007)
Y. V. Gomeniuk, A. N. Nazarov, Ya. N. Vovk, V. S. Lysenko, Yi Lu, Octavian Buiu, Steve Hall, R. J. Potter, P. Chalker, Charge trapping and interface states in hydrogen annealed HfO2-Si structures., Microelectronics Reliability 47(4-5): 714-717 (2007)
Yan Li, Tim Courtney, Roland N. Ibbett, Nigel Topham, Performance evaluation of RAID6 systems, FAST '07: Proceedings of the 5th USENIX conference on File and Storage Technologies, USENIX Association, February 2007
Yana Yankova, Koen Bertels, Georgi Kuzmanov, Georgi Gaydadjiev, Yi Lu, Stamatis Vassiliadis, DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator., FPL 2007: 697-701
Yana Yankova, Koen Bertels, Stamatis Vassiliadis, Roel Meeuws, Arcilio Virginia, Automated HDL Generation: Comparative Evaluation., ISCAS 2007: 2750-2753
Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion., FPL 2007: 345-350
Yang Qu, Juha-Pekka Soininen, Jari Nurmi, Static scheduling techniques for dependent tasks on dynamically reconfigurable devices., Journal of Systems Architecture 53(11): 861-876 (2007)
Yang Qu, Juha-Pekka Soininen, Jari Nurmi, A Genetic Algorithm for Scheduling Tasks onto Dynamically Reconfigurable Hardware., ISCAS 2007: 161-164
Yang Qu, Juha-Pekka Soininen, Jari Nurmi, Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices., DATE 2007: 147-152
Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi, System-Level Design for Partially Reconfigurable Hardware., ISCAS 2007: 2738-2741
Yanqing Ji, Hao Ying, John Yen, Shizhuo Zhu, Daniel C. Barth-Jones, Richard E. Miller, R. Michael Massanari, A distributed adverse drug reaction detection system using intelligent agents with a fuzzy recognition-primed decision model: Research Articles, International Journal of Intelligent Systems , Volume 22 Issue 8, John Wiley & Sons, Inc., August 2007
Yehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz, Michael Vinov, Eitan s Marcu, Gil Shurek, Constraint-Based Random Stimuli Generation for Hardware Verification., AI Magazine 28(3): 13-30 (2007)
Yi Guo, Yi Long, Weihua Sheng, Global Trajectory Generation for Nonholonomic Robots in Dynamic Environments., ICRA 2007: 1324-1329
Yi Lu, Computer simulation of a 3D free-form surface normal machining by 4SPS + RPS and 5SPS/UPU parallel machine tools., IJCAT 30(1/2): 147-153 (2007)
Yi Lu, Balaji Prabhakar, Flavio Bonomi, ElephantTrap: A low cost device for identifying large flows, HOTI '07: Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007) - Volume 00 , Volume 00, IEEE Computer Society, August 2007
Yoav Etsion, Dan Tsafrir, Scott Kirkpatrick, Dror G. Feitelson, Fine grained kernel logging with KLogger: experience and insights., EuroSys 2007: 259-272
Yoav Etsion, Dror G. Feitelson, L1 Cache Filtering Through Random Selection of Memory References, Parallel Architectures and Compilation Techniques (PACT)
Yoav Etsion, Dror G. Feitelson, Probabilistic Prediction of Temporal Locality., Computer Architecture Letters 6(1): 17-20 (2007)
Yoav Etsion, Dror G. Feitelson, L1 Cache Filtering Through Random Selection of Memory References., PACT 2007: 235-244
Yolanda Gil, Ewa Deelman, Mark H. Ellisman, Thomas Fahringer, Geoffrey Fox, Dennis Gannon, Carole A. Goble, Miron Livny, Luc Moreau, Jim Myers, Examining the Challenges of Scientific Workflows., IEEE Computer 40(12): 24-32 (2007)
Yongsheng Ding, Lei Gao, Da Ruan, Communication mechanisms in ecological network-based grid middleware for service emergence., Inf. Sci. 177(3): 722-733 (2007)
Yu Ding, Eunshin Byon, Chiwoo Park, Jiong Tang, Yi Lu, Xin Wang, Dynamic Data-Driven Fault Diagnosis of Wind Turbine Systems., International Conference on Computational Science (1) 2007: 1197-1204
Yu M. Chi, Paul Carpenter, Kent Colling, Gert Cauwenberghs, Ralph Etienne-Cummings, ISCAS Special Session Demo: Wireless Video Sensor for Ad-hoc Networks., ISCAS 2007: 1185
Yu M. Chi, Ralph Etienne-Cummings, Gert Cauwenberghs, Paul Carpenter, Kent Colling, Video Sensor Node for Low-Power Ad-hoc Wireless Networks., CISS 2007: 244-247
Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha, Vt balancing and device sizing towards high yield of sub-threshold static logic gates., ISLPED 2007: 355-358
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner, SODA: A High-Performance DSP Architecture for Software-Defined Radio., IEEE Micro 27(1): 114-123 (2007)
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai, Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors., ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Optimizing Test Length for Soft Faults in DRAM Devices., VTS 2007: 59-66
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Manifestation of Precharge Faults in High Speed DRAM Devices., DDECS 2007: 179-184
Zhijiang Chang, Georgi Gaydadjiev, Stamatis Vassiliadis, Infrastructure for Cross-Layer Designs Interaction., ICCCN 2007: 19-25
Zoltán Herczeg, Ákos Kiss, Daniel Schmidt, Norbert Wehn, Tibor Gyimóthy, XEEMU: An Improved XScale Power Simulator., PATMOS 2007: 300-309

2008

Andrea Marongiu, Luca Benini, Andrea Acquaviva, Andrea Bartolini, Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology., DSD 2008: 259-266
Andreas Fidjeland, Wayne Luk, Stephen Muggleton, A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming., BCS Int. Acad. Conf. 2008: 318-330
Antonio Roldao Lopes, George A. Constantinides, A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation., ARC 2008: 75-86
Bin Jiang, Ed F. Deprettere, Bart Kienhuis, Hierarchical run time deadlock detection in process networks., SiPS 2008: 239-244
Björn Nilsson, Lars Bengtsson, Bertil Svensson, Selecting back off algorithm in active RFID CSMA/CA based medium-access protocols., SIES 2008: 265-270
Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides, Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA., ARC 2008: 231-242
Chrysoulis Zambas, Mikel Luján, Introducing Aspects to the Implementation of a Java Fork/Join Framework., ICA3PP 2008: 294-304
Crispín Gómez Requena, Francisco Gilabert Villamón, María Engracia Gómez, Pedro Juan López Rodríguez, José Duato, RUFT: Simplifying the Fat-Tree Topology., ICPADS 2008: 153-160
D. Piso, Javier D. Bruguera, A New Rounding Algorithm for Variable Latency Division and Square Root Implementations., DSD 2008: 760-767
David Boland, George A. Constantinides, An FPGA-based implementation of the MINRES algorithm., FPL 2008: 379-384
Demid Borodin, Ben H. H. Juurlink, A Low-Cost Cache Coherence Verification Method for Snooping Systems., DSD 2008: 219-227
E. Mejía-Roa, Pedro Carmona-Saez, R. Nogales, Cesar Vicente, M. Vázquez, X. Y. Yang, Carlos García, Francisco Tirado, Alberto D. Pascual-Montano, bioNMF: a web-based tool for nonnegative matrix factorization in biology., Nucleic Acids Research 36(Web-Server-Issue): 523-528 (2008)
Fabio Cancare, Marco D. Santambrogio, Donatella Sciuto, , A design flow tailored for self dynamic reconfigurable architecture., IPDPS 2008: 1-8
Fadia Nemer, Hugues Cassé, Pascal Sainrat, Jean Paul Bahsoun, Inter-task WCET computation for a-way instruction caches., SIES 2008: 169-176
Faruk Bagci, Florian Kluge, Nader Bagherzadeh, Theo Ungerer, LocSens - An Indoor Location Tracking System using Wireless Sensors., ICCCN 2008: 887-891
Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata, SIMD Enhancements for a Hough Transform Implementation., DSD 2008: 899-903
George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong, Guest Editorial: Field Programmable Technology., Signal Processing Systems 51(1): 1-2 (2008)
Giacomo Paci, A. Nackaerts, Francky Catthoor, Luca Benini, Paul Marchal, How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design., DSD 2008: 550-557
Guido Marco Bertoni, Luca Breveglieri, Roberto Farina, Francesco Regazzoni, A 640 Mbit/S 32-Bit Pipelined Implementation of the AES Algorithm., SECRYPT 2008: 453-459
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere, Systematic and Automated Multiprocessor System Design Programming and Implementation., IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 542-555 (2008)
Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser, Safe design of high-performance embedded systems in an MDE framework., ISSE 4(3): 215-222 (2008)
Jörg Keller, Christoph W. Kessler, Optimized Pipelined Parallel Merge Sort on the Cell BE., Euro-Par Workshops 2008: 131-140
Jörg Keller, Christoph W. Kessler, Kalle König, Wolfgang Heenes, Hybrid Parallel Sort on the Cell Processor., PASA 2008: 107-112
Javier Forment, Francisco Gilabert, Antonio Robles, Vicente Conejero, Fernando Nuez, Jose M. Blanca, , EST2uni: an open parallel tool for automated EST analysis and database creation with a data mining web interface and microarray expression data integration., BMC Bioinformatics 9: (2008)
Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero, Selection of the Register File Size and the Resource Allocation Policy on SMT Processors., SBAC-PAD 2008: 63-70
Jesper Andersson, Morgan Ericsson, Christoph W. Keßler, Welf Löwe, Profile-Guided Composition., Software Composition 2008: 157-164
Jordi Torres, David Carrera, Vicenç Beltran, Nicolás Poggi, Kevin Hogan, Josep Lluis Berral, Ricard Gavaldà, Eduard Ayguadé, Toni Moreno, Jordi Guitart, Tailoring Resources: The Energy Efficient Consolidation Strategy Goes Beyond Virtualization., ICAC 2008: 197-198
José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum, A hardware mechanism to reduce the energy consumption of the register file of in-order architectures., IJES 3(4): 285-293 (2008)
Karl Ridgeway, David Bernstein, John Magnotti, Using Java's generics mechanism to improve type safety in the command pattern., ACM Southeast Regional Conference 2008: 231-236
Lily R. Liang, Vinay Mandal, Yi Lu, Deepak Kumar, MCM-test: a fuzzy-set-theory-based approach to differential analysis of gene pathways., BMC Bioinformatics 9(S-6): (2008)
Luca Fanucci, 11th Euromicro Conference on Digital System Design: Architectures Methods and Tools DSD 2008 Parma Italy September 3-5 2008, IEEE 2008
Martino Ruggiero, Michele Lombardi, Michela Milano, Luca Benini, Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE Processor., DSD 2008: 645-650
Matthias Hauswirth, Informa: An Extensible Framework for Group Response Systems., CollaborateCom 2008: 271-286
Mattias V. Eriksson, Oskar Skoog, Christoph W. Kessler, Optimal vs. heuristic integrated code generation for clustered VLIW architectures., SCOPES 2008: 11-20
Perttu Salmela, Harri Sorokin, Jarmo Takala, Low-complexity polynomials modulo integer with linearly incremented variable., SiPS 2008: 251-256
Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero, Measuring Operating System Overhead on CMT Processors., SBAC-PAD 2008: 133-140
Pieter Buteneers, Benjamin Schrauwen, David Verstraeten, Dirk Stroobandt, Real-Time Epileptic Seizure Detection on Intra-cranial Rat Data Using Reservoir Computing., ICONIP (1) 2008: 56-63
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung, Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation., BCS Int. Acad. Conf. 2008: 295-304
Reiner Hartenstein, The von Neumann Syndrome and the CS Education Dilemma., ARC 2008: 3
Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Jari Nurmi, Manfred Glesner, Fernando Moraes, Validation of executable application models mapped onto network-on-chip platforms., SIES 2008: 118-125
Seyed Masoud Sadjadi, Liana Fong, Rosa M. Badia, Javier Figueroa, Javier Delgado, Xabriel J. Collazo-Mojica, Khalid Saleem, Raju Rangaswami, Shu Shimizu, Hector A. Duran-Limon, Pat Welsh, Sandeep Pat, Transparent grid enablement of weather research and forecasting., Mardi Gras Conference 2008: 39
Simone Campanoni, Giovanni Agosta, Stefano Crespi-Reghizzi, A parallel dynamic compiler for CIL bytecode., SIGPLAN Notices 43(4): 11-20 (2008)
Slobodan Lukovic, Nikola Puzovic, Milos Stanisavljevic, An Enhanced Service Provider Communication Interface with Client Prioritization - Case Study on Fast-food Chain Restaurants., ICE-B 2008: 197-202
Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere, Deriving efficient control in Process Networks with Compaan/Laura., IJES 3(3): 170-180 (2008)
Vanderlei Bonato, Eduardo Marques, George A. Constantinides, A Parallel Hardware Architecture for Image Feature Detection., ARC 2008: 136-147
Vasileios Karakasis, Andreas Stafylopatis, Efficient Evolution of Accurate Classification Rules Using a Combination of Gene Expression Programming and Clonal Selection., IEEE Trans. Evolutionary Computation 12(6): 662-678 (2008)
Weihua Sheng, Hongjun Chen, Ning Xi, Navigating a Miniature Crawler Robot for Engineered Structure Inspection., IEEE T. Automation Science and Engineering 5(2): 368-373 (2008)
Álvaro Vázquez, Elisardo Antelo, New insights on Ling adders., ASAP 2008: 227-232
A. Elouardi, Samir Bouaziz, Antoine Dupret, Lionel Lacassagne, Jacques-Olivier Klein, Roger Reynaud, A Smart Architecture for Low-Level Image Computing., IJCSA 5(3a): 1-19 (2008)
A. Elyada, Ran Ginosar, U. Weiser, Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors., IEEE Trans. VLSI Syst. 16(9): 1243-1248 (2008)
A. Martínez, F. J. Alfaro, J. L. Sánchez, J. Duato, Providing Full QoS with 2 VCs in High-Speed Switches, Information Networking. Towards Ubiquitous Networking and Services, Springer-Verlag, November 2008
A. Montone, F. Redaelli, M. D. Santambrogio, S. Ogrenci Memik, A Reconfiguration-Aware Floorplacer for FPGAs, RECONFIG '08: Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs - Volume 00 , Volume 00, IEEE Computer Society, December 2008
A. Moreno, Eduardo César, A. Guevara, Joan Sorribes, Tomàs Margalef, Emilio Luque, Dynamic Pipeline Mapping (DPM)., Euro-Par 2008: 295-304
Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser, Modeling and Formal Validation of High-Performance Embedded Systems., ISPDC 2008: 215-222
Abid M. Malik, Jim McInnes, Peter van Beek, Optimal Basic Block Instruction Scheduling for Multiple-Issue Processors Using Constraint Programming., International Journal on Artificial Intelligence Tools 17(1): 37-54 (2008)
Abid M. Malik, Michael Chase, Tyrel Russell, Peter van Beek, An Application of Constraint Programming to Superblock Instruction Scheduling., CP 2008: 97-111
Abid M. Malik, Tyrel Russell, Michael Chase, Peter van Beek, Learning heuristics for basic block instruction scheduling., J. Heuristics 14(6): 549-569 (2008)
Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser, MARTE-based Design of a Multimedia Application and Formal Analysis., FDL 2008: 160-166
Adrian Prantl, Markus Schordan, Jens Knoop, TuBound - A Conceptually New Tool for Worst-Case Execution Time Analysis., WCET 2008
Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal, Enabling MPSoC Design Space Exploration on FPGAs., IMTIC 2008: 412-421
Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John, Distilling the essence of proprietary workloads into miniature benchmarks., TACO 5(2): (2008)
Ajay K. Verma, Philip Brisk, Paolo Ienne, Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design., DATE 2008: 1250-1255
Ajay K. Verma, Philip Brisk, Paolo Ienne, Fast quasi-optimal and pipelined instruction-set extensions., ASP-DAC 2008: 334-339
Ajay K. Verma, Philip Brisk, Paolo Ienne, Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits., IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1761-1774 (2008)
Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John, Ciji Isen, Automated microprocessor stressmark generation., HPCA 2008: 229-239
Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha, Analyzing composability of applications on MPSoC platforms., Journal of Systems Architecture - Embedded Systems Design 54(3-4): 369-383 (2008)
Akash Kumar, Kees van Berkel, Vectorization of Reed Solomon Decoding and Mapping on the EVP, DATE
Akash Kumar, Kees van Berkel, Vectorization of Reed Solomon Decoding and Mapping on the EVP., DATE 2008: 450-455
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal, Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA., ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
Alain Ketterlin, Philippe Clauss, Prediction and trace compression of data access addresses through nested loop recognition., CGO 2008: 94-103
Alastair D. Reid, Krisztián Flautner, Edmund Grimley-Evans, Yuan Lin, SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip., CASES 2008: 95-104
Alastair F. Donaldson, Alice Miller, Automatic Symmetry Detection for Promela., J. Autom. Reasoning 41(3-4): 251-293 (2008)
Alastair F. Donaldson, Paul Keir, Anton Lokhmotov, Compile-Time and Run-Time Issues in an Auto-Parallelisation System for the Cell BE Processor., Euro-Par Workshops 2008: 163-173
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung, Integrated Floorplanning Module-Selection and Architecture Generationfor Reconfigurable Devices., IEEE Trans. VLSI Syst. 16(6): 733-744 (2008)
Alastair Murray, Björn Franke, Fast source-level data assignment to dual memory banks., SCOPES 2008: 43-52
Albert Cohen, Louis Mandel, Florence Plateau, Marc Pouzet, Abstraction of Clocks in Synchronous Data-Flow Systems., APLAS 2008: 237-254
Albert Cohen, María Jesús Garzarán, Christian Lengauer, Samuel P. Midkiff, Programming Models for Ubiquitous Parallelism 02.09. - 07.09.2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI) Schloss Dagstuhl Germany 2008
Alberto A. Del Barrio, Maria C. Molina, Jose M. Mendias, Esther Andres, Roman Hermida, Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado, Applying speculation techniques to implement functional units., ICCD 2008: 74-80
Alberto Ferrante, Simone Medardoni, Davide Bertozzi, Network Interface Sharing Techniques for Area Optimized NoC Architectures, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Alberto Núñez, Javier Fernández, Jose D. Garcia, Laura Prada, Jesús Carretero, SIMCAN: a SIMulator framework for computer architectures and storage networks, Simutools '08: Proceedings of the 1st international conference on Simulation tools and techniques for communications, networks and systems & workshops, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), March 2008
Alberto Nuñez, Javier Fernández, José Daniel García, Jesús Carretero, New techniques for simulating high performance MPI applications on large storage networks., CLUSTER 2008: 444-452
Alberto Nuñez, Javier Fernández, José Daniel García, Jesús Carretero, Analyzing Scalable High-Performance I/O Architectures., PDPTA 2008: 631-637
Alberto Nuñez, Javier Fernández, José Daniel García, Laura Prada, Jesús Carretero, New Techniques for Modeling File Data Distribution on Storage Nodes., Annual Simulation Symposium 2008: 175-182
Alberto Nuñez, Javier Fernández, José Daniel García, Laura Prada, Jesús Carretero, M-PLAT: Multi-Programming Language Adaptive Tutor., ICALT 2008: 649-651
Alberto Ros, Manuel E. Acacio, José M. García, DiCo-CMP: Efficient cache coherency in tiled CMP architectures., IPDPS 2008: 1-11
Alberto Ros, Manuel E. Acacio, José M. García, Scalable Directory Organization for Tiled CMP Architectures., CDES 2008: 112-118
Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio, José M. García, Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors, Journal of Parallel and Distributed Computing , Volume 68 Issue 11, Academic Press, Inc., November 2008
Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio, José M. García, Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors., J. Parallel Distrib. Comput. 68(11): 1413-1424 (2008)
Alejandra Rodríguez, Javier Fernández, Jesús Carretero, Model for on-demand virtual computing architectures - OVCA., ISCC 2008: 447-454
Alejandro Duran, Josep M. Pérez, Eduard Ayguadé, Rosa M. Badia, Jesús Labarta, Extending the OpenMP Tasking Model to Allow Dependent Tasks., IWOMP 2008: 111-122
Alejandro Duran, Julita Corbalán, Eduard Ayguadé, An adaptive cut-off for task parallelism., SC 2008: 36
Alejandro Duran, Julita Corbalán, Eduard Ayguadé, Evaluation of OpenMP Task Scheduling Strategies., IWOMP 2008: 100-110
Alejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, Mateo Valero, LPA: A First Approach to the Loop Processor Architecture., HiPEAC 2008: 273-287
Alejandro Martínez-Vicente, George Apostolopoulos, Francisco José Alfaro, José L. Sánchez, José Duato, Efficient Deadline-Based QoS Algorithms for High-Performance Networks., IEEE Trans. Computers 57(7): 928-939 (2008)
Aleksandar Ilic, Frederico Pratas, Leonel Sousa, Distributed Web-based Platform for Computer Architecture Simulation., ISPDC 2008: 317-324
Aleksandar Ilic, Frederico Pratas, Leonel Sousa, Distributed Web-based Platform for Computer Architecture Simulation, 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008)
Aleksandar Ilic, Leonel Sousa, A distributed platform for large scale simulation and classification, In Fourth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems - ACACES2008
Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo A. Prete, Performance Sensitivity of NUCA Caches to On-Chip Network Parameters, SBAC-PAD '08: Proceedings of the 2008 20th International Symposium on Computer Architecture and High Performance Computing - Volume 00 , Volume 00, IEEE Computer Society, October 2008
Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström, Leveraging Data Promotion for Low Power D-NUCA Caches, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne, Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs., FPGA 2008: 181-190
Alessandro G. Di Nuovo, Vincenzo Catania, Santo Di Nuovo, Serafino Buono, Psychology with soft computing: An integrated approach and its applications., Appl. Soft Comput. 8(1): 829-837 (2008)
Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow., DELTA 2008: 405-409
Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Francesco Bruschi, A Requirements-Driven Simulation Framework for Communication Infrastructures Design., FDL 2008: 111-117
Alessio Bechini, Andrea Tomasi, Jacopo Viotto, Enabling ontology-based document classification and management in ebXML registries., SAC 2008: 1145-1150
Alessio Bechini, Cosimo Antonio Prete, Special track on Embedded Systems: Applications Solutions and Techniques: editorial message., SAC 2008: 1476
Alessio Bechini, Mario G. C. A. Cimino, Francesco Marcelloni, Andrea Tomasi, Patterns and technologies for enabling supply chain traceability through collaborative e-business., Information & Software Technology 50(4): 342-359 (2008)
Alessio Montone, Marco D. Santambrogio, Donatella Sciuto, A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems., DELTA 2008: 450-453
Alessio Montone, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures., IPDPS 2008: 1-8
Alex Conconi, Todor Ganchev, Otilia Kocsis, George Papadopoulos, Fernando Fernández-Aranda, Susana Jiménez-Murcia, PlayMancer: A Serious Gaming 3D Environment, AXMEDIS '08: Proceedings of the 2008 International Conference on Automated solutions for Cross Media Content and Multi-channel Distribution, IEEE Computer Society, November 2008
Alex Piñeiro, Javier D. Bruguera, Fabrizio Lamberti, Paolo Montuschi, A Radix-2 Digit-by-Digit Architecture for Cube Root., IEEE Trans. Computers 57(4): 562-566 (2008)
Alex Ramírez, Gianfranco Bilardi, Michael Gschwind, Proceedings of the 5th Conference on Computing Frontiers 2008 Ischia Italy May 5-7 2008, ACM 2008
Alexander A. Shvartsman, Pascal Felber, Structural Information and Communication Complexity 15th International Colloquium SIROCCO 2008 Villars-sur-Ollon Switzerland June 17-20 2008 Proceedings, Springer 2008
Alexander Sayenko, Olli Alanen, Timo Hämäläinen, Scheduling solution for the IEEE 802.16 base station., Computer Networks 52(1): 96-115 (2008)
Alexander von Renteln, Uwe Brinkschulte, Michael Weiss, Examinating Task Distribution by an Artificial Hormone System Based Middleware., ISORC 2008: 119-123
Alexandre Coveliers, Karine Heydemann, Nathalie Drach, Étude de la sensibilité aux jeux de données de la compilation itérative., Technique et Science Informatiques 27(6): 757-777 (2008)
Alexandre Otto Stube, Dolores Rexachs, Emilio Luque, Software Probes: Towards a Quick Method for Machine Characterization and Application Performance Prediction., ISPDC 2008: 23-30
Alexandros Bartzas, Miguel Peon-Quiros, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information., ASP-DAC 2008: 434-439
Alexey Rodriguez, Johan Jeuring, Patrik Jansson, Alex Gerdes, Oleg Kiselyov, Bruno C. d. S. Oliveira, Comparing libraries for generic programming in haskell., Haskell 2008: 111-122
Amedeo Cesta, Gabriella Cortellessa, Michel Denis, Alessandro Donati, Simone Fratini, Angelo Oddi, Nicola Policella, Erhard Rabenau, Jonathan Schulster, Continuous Plan Management Support for Space Missions: the RAXEM Case., ECAI 2008: 703-707
Amine Marref, Guillem Bernat, Towards Predicated WCET Analysis., WCET 2008
Amit Golander, Shlomo Weiss, Hiding the misprediction penalty of a resource-efficient high-performance processor., TACO 4(4): (2008)
Amit Golander, Shlomo Weiss, Ronny Ronen, DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals, IEEE Computer Architecture Letters , Volume 7 Issue 2, IEEE Computer Society, July 2008
Ana Lucia Varbanescu, Alexander S. van Amesfoort, Tim Cornwell, Andrew Mattingly, Bruce G. Elmegreen, Rob van Nieuwpoort, Ger van Diepen, Henk J. Sips, Radioastronomy Image Synthesis on the Cell/B.E.., Euro-Par 2008: 749-762
Anastasios Gounaris, Christos Yfoulis, Rizos Sakellariou, Marios D. Dikaiakos, Robust Runtime Optimization of Data Transfer in Queries over Web Services., ICDE 2008: 596-605
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Compositional dynamic cache management for embedded chip multiprocessors., DATE 2008: 991-996
Andrea Calimera, Luca Benini, Enrico Macii, Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints., DATE 2008: 973-978
Andrea Cuoccio, Paolo R. Grassi, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, A Generation Flow for Self-Reconfiguration Controllers Customization., DELTA 2008: 279-284
Andrea Marongiu, Luca Benini, Andrea Acquaviva, Andrea Bartolini, Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis, Functional Self-Testing for Bus-Based Symmetric Multiprocessors, ACM/IEEE Design Automation and Test in Europe Conference (DATE 2008), Munich, Germany, pp. 1304-1309, March 2008.
Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij, Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip., NOCS 2008: 211-212
Andreas Merentitis, Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, Low Energy On-Line SBST of Embedded Processors, IEEE International Test Conference (ITC 2008), Santa Clara, California, USA, October 2008.
Andreas Wieferink, Heinrich Meyr, Rainer Leupers, Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms, 1 edition, Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms, 1 edition, Springer Publishing Company, Incorporated, July 2008
Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr, SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends., IJES 3(3): 109-118 (2008)
Andres Garcia, Mladen Berekovic, Tom Vander Aa, Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor., ASAP 2008: 245-250
Andres Mejia, Jose Flich, José Duato, On the Potentials of Segment-Based Routing for NoCs., ICPP 2008: 594-603
Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk, An analytical model describing the relationships between logic architecture and FPGA density., FPL 2008: 221-226
Andrey Brito, Christof Fetzer, Heiko Sturzrehm, Pascal Felber, Speculative out-of-order event processing with software transaction memory., DEBS 2008: 265-275
Andy D. Pimentel, The Artemis workbench for system-level performance evaluation of embedded systems., IJES 3(3): 181-196 (2008)
Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas, Calibration of Abstract Performance Models for System-Level Design Space Exploration., Signal Processing Systems 50(2): 99-114 (2008)
Andy D. Pimentel, Todor Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere, Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study., SAMOS 2008: 167-176
Andy Georges, Lieven Eeckhout, Dries Buytaert, Java performance evaluation through rigorous replay compilation., OOPSLA 2008: 367-384
Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest, Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor., VLSI Design 2008: 201-207
Anthony Danalis, Aaron Brown, Lori L. Pollock, D. Martin Swany, John Cavazos, Gravel: A Communication Library to Fast Path MPI., PVM/MPI 2008: 111-119
Antonino Tumeo, Christian Pilato, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi, Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems., ICSAMOS 2008: 142-149
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications., DATE 2008: 1039-1044
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, Lightweight DMA management mechanisms for multiprocessors on FPGA., ASAP 2008: 275-280
Antonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro, Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications., DATE 2008: 1208-1213
Antonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro, Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems., ARC 2008: 111-123
Antonio Deledda, Claudio Mucci, Arseni Vitkovski, Philippe Bonnot, Arnaud Grasset, P. Millet, Matthias Kühnle, F. Ries, Michael Hübner, Jürgen Becker, Massimo Coppola, Lorenzo Pieralisi, Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor., DATE 2008: 1352-1357
Antonio Flores, Juan L. Aragón, Manuel E. Acacio, An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures., The Journal of Supercomputing 45(3): 341-364 (2008)
Antonio Flores, Manuel E. Acacio, Juan L. Aragón, Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs., ICPP 2008: 295-303
Antonio Jimeno, Higinio Mora, Jose L. Sanchez, Francisco Pujol, A BCD-based architecture for fast coordinate rotation, Journal of Systems Architecture: the EUROMICRO Journal , Volume 54 Issue 8, Elsevier North-Holland, Inc., August 2008
Antonio Manuel Ortiz, Teresa Olivares, Luis Orozco-Barbosa, Martín Perez-Juana, Measurements with different role-based wireless sensor network organizations., PM2HW2N 2008: 9-16
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Åshild Grønstad Solheim, Deadlock-Free Dynamic Network Reconfiguration Based on Close Up*/Down* Graphs., Euro-Par 2008: 940-949
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, Evaluation of a Fabric Management Mechanism for Advanced Switching in Presence of Traffic., PDP 2008: 120-125
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles, Tor Skeie, José Duato, A proposal for managing ASI fabrics., Journal of Systems Architecture - Embedded Systems Design 54(7): 664-678 (2008)
Antonis Krithinakis, Lubomir Stroetmann, Elias Athanasopoulos, Georgios Kopidakis, Evangelos P. Markatos, WSIM: A Software Platform to Simulate All-Optical Security Operations, EC2ND '08: Proceedings of the 2008 European Conference on Computer Network Defense - Volume 00 , Volume 00, IEEE Computer Society, December 2008
Antonis Theocharides, Demetres Antoniades, Michalis Polychronakis, Elias Athanasopoulos, Evangelos P. Markatos, Topnet: A Network-aware top(1)., LISA 2008: 145-157
Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors., ACM Trans. Embedded Comput. Syst. 7(4): (2008)
Anupam Chattopadhyay, Rainer Leupers, Heinrich Meyr, Gerd Ascheid, Language-driven Exploration and Implementation of Partially Re-configurable ASIPs, 1st edition, Language-driven Exploration and Implementation of Partially Re-configurable ASIPs, 1st edition, Springer Publishing Company, Incorporated, December 2008
Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures., DATE 2008: 1334-1339
Arash Ahmadi, Mark Zwolinski, Symbolic noise analysis approach to computational hardware optimization., DAC 2008: 391-396
Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens, Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism, ETS '08: Proceedings of the 2008 13th European Test Symposium - Volume 00 , Volume 00, IEEE Computer Society, May 2008
Arik Friedman, Ran Wolff, Assaf Schuster, Providing k-anonymity in data mining., VLDB J. 17(4): 789-804 (2008)
Aris Lanaridis, Vasileios Karakasis, Andreas Stafylopatis, Clonal Selection-Based Neural Classifier., HIS 2008: 655-660
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny, Timing optimization in logic with interconnect., SLIP 2008: 19-26
Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez, Analysis of video filtering on the cell processor., ISCAS 2008: 488-491
Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramirez, Parallel H.264 Decoding on an Embedded Multicore Processor, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Arseni Vitkovski, Georgi Kuzmanov, Georgi Gaydadjiev, Memory Organization with Multi-Pattern Parallel Accesses., DATE 2008: 1420-1425
Asadollah Shahbahrami, Ben H. H. Juurlink, Optimization of Content-Based Image Retrieval Functions., ISM 2008: 607-612
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis, Implementing the 2-D Wavelet Transform on SIMD-Enhanced General-Purpose Processors., IEEE Transactions on Multimedia 10(1): 43-51 (2008)
Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis, Versatility of extended subwords and the matrix register file., TACO 5(1): (2008)
Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits., ISCAS 2008: 2761-2764
Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, A Scalable Algorithmic Framework for Row-Based Power-Gating., DATE 2008: 379-384
Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Optimal sleep transistor synthesis under timing and area constraints., ACM Great Lakes Symposium on VLSI 2008: 177-182
Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating., PATMOS 2008: 42-51
Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction., ISLPED 2008: 51-56
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers., IEEE Trans. VLSI Syst. 16(6): 639-649 (2008)
Ashwin M. Aji, Wu-chun Feng, Filip Blagojevic, Dimitrios S. Nikolopoulos, Cell-SWat: modeling and scheduling wavefront computations on the cell broadband engine., Conf. Computing Frontiers 2008: 13-22
Ayose Falcón, Paolo Faraboschi, Daniel Ortega, An Adaptive Synchronization Technique for Parallel Simulation of Networked Clusters., ISPASS 2008: 22-31
B. Mei, B. Sutter, T. Aa, M. Wouters, A. Kanstein, S. Dupont, Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder, Journal of Signal Processing Systems , Volume 51 Issue 3, Kluwer Academic Publishers, June 2008
Babak Falsafi, Pascal Felber, Introduction, SIGPLAN Notices , Volume 43 Issue 5, ACM, May 2008
Barbara M. Chapman, Weimin Zheng, Guang R. Gao, Mitsuhisa Sato, Eduard Ayguadé, Dongsheng Wang, A Practical Programming Model for the Multi-Core Era 3rd International Workshop on OpenMP IWOMP 2007 Beijing China June 3-7 2007 Proceedings, Springer 2008
Bart Vermeulen, Kees Goossens, Siddharth Umrani, Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip., NOCS 2008: 3-12
Bartosz Biskupski, Marc Schiely, Pascal Felber, René Meier, Tree-Based Analysis of Mesh Overlays for Peer-to-Peer Streaming., DAIS 2008: 126-139
Behnaz Pourebrahimi, Koen Bertels, Auction Protocols for Resource Allocations in Ad-Hoc Grids., Euro-Par 2008: 520-533
Behnaz Pourebrahimi, Koen Bertels, Adaptation to Dynamic Resource Availability in Ad Hoc Grids through a Learning Mechanism., CSE 2008: 171-178
Behram Khan, Matthew Horsnell, Ian Rogers, Mikel Luján, Andrew Dinn, Ian Watson, An Object-Aware Hardware Transactional Memory System., HPCC 2008: 93-102
Behram Khan, Matthew Horsnell, Ian Rogers, Mikel Luján, Andrew Dinn, Ian Watson, A first insight into object-aware hardware transactional memory., SPAA 2008: 107-109
Ben Breech, Lori L. Pollock, John Cavazos, RUGRAT: Runtime Test Case Generation Using Dynamic Compilers., ISSRE 2008: 137-146
Ben Cope, Peter Y. K. Cheung, Wayne Luk, Systematic design space exploration for customisable multi-processor architectures., ICSAMOS 2008: 57-64
Ben Cope, Peter Y. K. Cheung, Wayne Luk, Using Reconfigurable Logic to Optimise GPU Memory Accesses., DATE 2008: 44-49
Ben Juurlink, Iosif Antochi, Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, GRAAL: A Framework for Low-Power 3D Graphics Accelerators, IEEE Computer Graphics and Applications , Volume 28 Issue 4, IEEE Computer Society Press, July 2008
Benjamin Satzger, Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer, Using Automated Planning for Trusted Self-organising Organic Computing Systems., ATC 2008: 60-72
Benjamin Satzger, Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer, A Lazy Monitoring Approach for Heartbeat-Style Failure Detectors., ARES 2008: 404-409
Benjamin Satzger, Theo Ungerer, Grouping algorithms for scalable self-monitoring distributed systems., Autonomics 2008: 35
Benjamin Schrauwen, Marion Wardermann, David Verstraeten, Jochen J. Steil, Dirk Stroobandt, Improving reservoirs using intrinsic plasticity., Neurocomputing 71(7-9): 1159-1171 (2008)
Benny Akesson, Liesbeth Steffens, Eelke Strooisma, Kees Goossens, Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration, RTCSA '08: Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications - Volume 00 , Volume 00, IEEE Computer Society, August 2008
Benoît Dupont de Dinechin, Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors., Euro-Par 2008: 370-381
Benoit Boissinot, Sebastian Hack, Daniel Grund, Benoît Dupont de Dinechin, Fabrice Rastello, Fast liveness checking for ssa-form programs., CGO 2008: 35-44
Bertrand Le Gal, Emmanuel Casseau, Caaliph Andriamisaina, Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau., Technique et Science Informatiques 27(9-10): 1129-1154 (2008)
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont, Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder., Signal Processing Systems 51(3): 225-243 (2008)
Björn Franke, Fast cycle-approximate instruction set simulation., SCOPES 2008: 69-78
Bjorn De Sutter, Bertrand Anckaert, Jens Geiregat, Dominique Chanet, Koen De Bosschere, Instruction Set Limitation in Support of Software Diversity., ICISC 2008: 152-165
Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei, Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays., LCTES 2008: 151-160
Blas Cuesta, Antonio Robles, José Duato, Switch-Based Packing Technique for Improving Token Coherence Scalability., PDCAT 2008: 83-90
Blas Cuesta, Antonio Robles, José Duato, Improving Token Coherence by Multicast Coherence Messages., PDP 2008: 269-273
Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii, Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style., DATE 2008: 967-972
Boris Feigin, Alan Mycroft, Jones optimality and hardware virtualization: a report on work in progress., PEPM 2008: 169-175
Borja Bergua, Félix García Carballeira, Alejandro Calderón, Luis Miguel Sánchez, Jesús Carretero, Comparing Grid Data Transfer Technologies in the Expand Parallel File System., PDP 2008: 110-114
Bruno Bougard, Bjorn De Sutter, Diederik Verkest, Liesbet Van der Perre, Rudy Lauwereins, A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing, IEEE Micro , Volume 28 Issue 4, IEEE Computer Society Press, July 2008
Bruno Bougard, Bjorn De Sutter, Sebastien Rabou, David Novo, Osman Allam, Steven Dupont, Liesbet Van der Perre, A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio., DATE 2008: 716-721
Bruno Bougard, Paul Marchal, Luca Benini, Doris Keitel-Schulz, N. Checka, HOT TOPIC - 3D Integration or How to Scale in the 21st Century., DATE 2008: 1516
C. Bolchini, A. Miele, M. Rebaudengo, F. Salice, D. Sciuto, L. Sterpone, M. Violante, Software and Hardware Techniques for SEU Detection in IP Processors, Journal of Electronic Testing: Theory and Applications , Volume 24 Issue 1-3, Kluwer Academic Publishers, June 2008
Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten, A monitoring-aware network-on-chip design flow., Journal of Systems Architecture - Embedded Systems Design 54(3-4): 397-410 (2008)
Calin Glitia, Pierre Boulet, High Level Loop Transformations for Systematic Signal Processing Embedded Applications., SAMOS 2008: 187-196
Carlo Brandolese, William Fornaciari, Measurement Analysis and Modeling of RTOS System Calls Timing., DSD 2008: 618-625
Carlo Curino, Luca Fossati, Vincenzo Rana, Francesco Redaelli, Marco D. Santambrogio, Donatella Sciuto, The Shining embedded system design methodology based on self dynamic reconfigurable architectures., ASP-DAC 2008: 595-600
Carlo Galuzzi, Dimitris Theodoropoulos, Koen Bertels, Clustering method for the identification of convex disconnected Multiple Input Multiple Output instructions., ICSAMOS 2008: 65-73
Carlo Galuzzi, Dimitris Theodoropoulos, Roel Meeuws, Koen Bertels, Automatic Instruction-Set Extensions with the Linear Complexity Spiral Search, RECONFIG '08: Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs - Volume 00 , Volume 00, IEEE Computer Society, December 2008
Carlo Galuzzi, Koen Bertels, A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures., ARC 2008: 278-283
Carlo Galuzzi, Koen Bertels, The Instruction-Set Extension Problem: A Survey., ARC 2008: 207-218
Carlos Amiama, Javier Bueno, Carlos José Álvarez, José Manuel Pereira, Design and field test of an automatic data acquisition system in a self-propelled forage harvester, Computers and Electronics in Agriculture , Volume 61 Issue 2, Elsevier Science Publishers B. V., May 2008
Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero, Software-Controlled Priority Characterization of POWER5 Processor, ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, ACM, June 2008
Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation., ARCS 2008: 173-187
Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero, Balancing HPC applications through smart allocation of resources in MT processors., IPDPS 2008: 1-12
Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero, A dynamic scheduler for balancing HPC applications., SC 2008: 41
Carlos Domínguez, Houcine Hassan, Alfons Crespo, Emotional Architecture for Robotic Agents., IC-AI 2008: 693-699
Carlos Morra, João Bispo, João M. P. Cardoso, Jürgen Becker, Combining Rewriting-Logic Architecture Generation and Simulation to Exploit Coarse-Grained Reconfigurable Architectures., FCCM 2008: 320-321
Carlos Morra, João M. P. Cardoso, João Bispo, Jürgen Becker, Retargeting Evaluating and Generating Reconfigurable Array-Based Architectures., SASP 2008: 34-41
Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors., ICPP 2008: 173-181
Carmen Martínez, Ramón Beivide, Esteban Stafford, Miquel Moretó, Ernst M. Gabidulin, Modeling Toroidal Networks with the Gaussian Integers, IEEE Transactions on Computers , Volume 57 Issue 8, IEEE Computer Society, August 2008
Carmen Martínez, Ramón Beivide, E. Stafford, Miquel Moretó, Ernst M. Gabidulin, Modeling Toroidal Networks with the Gaussian Integers., IEEE Trans. Computers 57(8): 1046-1056 (2008)
Carolina Bonacic, Carlos García, Mauricio Marín, Manuel Prieto, Francisco Tirado, Exploiting Hybrid Parallelism in Web Search Engines., Euro-Par 2008: 414-423
Carolina Bonacic, Carlos García, Mauricio Marín, Manuel Prieto, Francisco Tirado, Cesar Vicente, Improving Search Engines Performance on Multithreading Processors., VECPAR 2008: 201-213
Chao Wang, Stefan Maier, Xiaoning Nie, Xuehai Zhou, Jinsong Ji, An Accurate Multi-processing Simulator Based on ADL, SEC '08: Proceedings of the 2008 Fifth IEEE International Symposium on Embedded Computing - Volume 00 , Volume 00, IEEE Computer Society, October 2008
Chengjun Zhu, Chao Li, Lei Gao, Zhang Xiong, Skew Estimation and Segmentation of Text Line in Video Frames., ISIP 2008: 379-383
Chi Cao Minh, JaeWoong Chung, Christos Kozyrakis, Kunle Olukotun, STAMP: Stanford Transactional Applications for Multi-Processing., IISWC 2008: 35-46
Chris R. Jesshope, Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips., Parallel Processing Letters 18(2): 257-274 (2008)
Chris R. Jesshope, Building a Concurrency and Resource Allocation Model into a Processor's ISA., Euro-Par Workshops 2008: 129-130
Chris R. Jesshope, Introduction to Programming Multicores., SAMOS 2008: 207
Chris R. Jesshope, Jean-Marc Philippe, Michiel van Tol, An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency., SAMOS 2008: 218-228
Christian Fensch, Marcelo Cintra, An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs, IEEE
Christian Fensch, Marcelo Cintra, An OS-based alternative to full hardware coherence on tiled CMPs., HPCA 2008: 355-366
Christian Neeb, Norbert Wehn, Designing efficient irregular networks for heterogeneous systems-on-chip., Journal of Systems Architecture - Embedded Systems Design 54(3-4): 384-396 (2008)
Christian Pilato, Antonino Tumeo, Gianluca Palermo, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, Improving evolutionary exploration to area-time optimization of FPGA designs., Journal of Systems Architecture - Embedded Systems Design 54(11): 1046-1057 (2008)
Christian Pilato, Daniele Loiacono, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis., IEEE Congress on Evolutionary Computation 2008: 3334-3341
Christian Tenllado, Javier Setoain, Manuel Prieto, Luis Piñuel, Francisco Tirado, Parallel Implementation of the 2D Discrete Wavelet Transform on Graphics Processing Units: Filter Bank versus Lifting., IEEE Trans. Parallel Distrib. Syst. 19(3): 299-310 (2008)
Christian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich, Classification of General Data Flow Actors into Known Models of Computation., MEMOCODE 2008: 119-128
Christianne Dalforno, Diego Mostaccio, Remo Suppi, Emilio Luque, Increasing the Scalability and the Speedup of a Fish School Simulator., ICCSA (2) 2008: 936-949
Christine Nardini, Lei Wang, Hesen Peng, Luca Benini, Michael D. Kuo, MM-Correction: Meta-analysis-Based Multiple Hypotheses Correction in Omic Studies., BIOSTEC (Selected Papers) 2008: 242-255
Christine Nardini, Luca Benini, Michael D. Kuo, Statistical Significance in Omic Data Analyses - Alternative/Complementary Method for Efficient Automatic Identification of Statistically Significant Tests in High Throughput Biological Studies., BIOSIGNALS (1) 2008: 56-63
Christoph Anthes, Thomas Fahringer, Dieter Kranzlmüller, Real-Time Online Interactive Applications on the Grid (ROIA 2008)., Euro-Par Workshops 2008: 327-328
Christoph W. Kessler, Jörg Keller, Optimized on-chip pipelining of memory-intensive computations on the cell BE., SIGARCH Computer Architecture News 36(5): 36-45 (2008)
Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle, Exploring and predicting the architecture/optimising compiler co-design space., CASES 2008: 31-40
Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle, Exploring and Predicting the Architecture/Optimising Compiler Co-Design Space, International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig, Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig, Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures., FPL 2008: 391-396
Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich, A comparison of embedded reconfigurable video-processing architectures., FPL 2008: 587-590
Christos Kotselidis, Mohammad Ansari, Kim Jarvis, Mikel Luján, Chris C. Kirkham, Ian Watson, Investigating software Transactional Memory on clusters., IPDPS 2008: 1-6
Christos Kotselidis, Mohammad Ansari, Kim Jarvis, Mikel Luján, Chris C. Kirkham, Ian Watson, DiSTM: A Software Transactional Memory Framework for Clusters., ICPP 2008: 51-58
Christos Strydis, Suitable cache organizations for a novel biomedical implant processor., ICCD 2008: 591-598
Christos Strydis, Christoforos Kachris, Georgi Gaydadjiev, ImpBench: A novel benchmark suite for biomedical microelectronic implants., ICSAMOS 2008: 82-91
Christos Strydis, Di Zhu, Georgi Gaydadjiev, Profiling of symmetric-encryption algorithms for a novel biomedical-implant architecture., Conf. Computing Frontiers 2008: 231-240
Christos Strydis, Georgi Gaydadjiev, Profiling of lossless-compression algorithms for a novel biomedical-implant architecture., CODES+ISSS 2008: 109-114
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Rapid estimation of power consumption for hybrid FPGAs., FPL 2008: 227-232
Chunyang Gou, Georgi K. Kuzmanov, Georgi N. Gaydadjiev, Sams: single-affiliation multiple-stride parallel memory scheme, MAW '08: Proceedings of the 2008 workshop on Memory access on future processors: a solved problem?, ACM, May 2008
Clément Ballabriga, Hugues Cassé, Pascal Sainrat, An improved approach for set-associative instruction cache partial analysis., SAC 2008: 360-367
Claudia Canali, José Daniel García, Riccardo Lancellotti, Impact of Social Networking Services on the Performance and Scalability of Web Server Infrastructures., NCA 2008: 160-167
Claudio Brunelli, Fabio Campi, Claudio Mucci, Davide Rossi, Tapani Ahonen, Juha Kylliäinen, Fabio Garzia, Jari Nurmi, Design space exploration of an open-source IP-reusable scalable floating-point engine for embedded applications., Journal of Systems Architecture - Embedded Systems Design 54(12): 1143-1154 (2008)
Claudio Brunelli, Fabio Garzia, Carmelo Giliberto, Jari Nurmi, A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck., FPL 2008: 487-490
Claudio Brunelli, Fabio Garzia, Jari Nurmi, A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities., J. Real-Time Image Processing 3(1-2): 21-32 (2008)
Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard, Reconfigurable hardware: The holy grail of matching performance with programming productivity., FPL 2008: 409-414
Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini, Robust and Low Complexity Rate Control for Solar Powered Sensors., DATE 2008: 230-235
Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini, Approximate Control Design for Solar Driven Sensor Nodes., HSCC 2008: 634-637
Colin F. Snook, Michael Poppleton, Ian Johnson, Rigorous engineering of product-line requirements: A case study in failure management., Information & Software Technology 50(1-2): 112-129 (2008)
Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Combining system scenarios and configurable memories to tolerate unpredictability., ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
Cor Meenderinck, Ben H. H. Juurlink, (When) Will CMPs Hit the Power Wall?., Euro-Par Workshops 2008: 184-193
Cosmin E. Oancea, Alan Mycroft, Software thread-level speculation: an optimistic library implementation, IWMSE '08: Proceedings of the 1st international workshop on Multicore software engineering, ACM, May 2008
Cosmin E. Oancea, Alan Mycroft, Set-Congruence Dynamic Analysis for Thread-Level Speculation (TLS)., LCPC 2008: 156-171
Craig Moore, Harald Devos, Dirk Stroobandt, Optimizing the FPGA Memory Design for a Sobel Edge Detector, Engineering of Reconfigurable Systems and Algorithms (ERSA)
Crispín Gómez Requena, Francisco Gilabert Villamón, María Engracia Gómez, Pedro Juan López Rodríguez, José Duato, RUFT: Simplifying the Fat-Tree Topology., ICPADS 2008: 153-160
Crispín Gómez Requena, María Engracia Gómez, Pedro López, José Duato, Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity., PDP 2008: 20-29
Crispín Gómez Requena, María Engracia Gómez, Pedro López, José Duato, Reducing Packet Dropping in a Bufferless NoC., Euro-Par 2008: 899-909
Crispin Gomez Requena, Francisco Gilabert Villamon, Maria Gomez, Pedro Lopez, Jose Duato, Beyond Fat--tree: Unidirectional Load--Balanced Multistage Interconnection Network, IEEE Computer Architecture Letters , Volume 7 Issue 2, IEEE Computer Society, July 2008
Cristian Perfumo, Nehir Sönmez, Srdjan Stipic, Osman S. Unsal, Adrián Cristal, Tim Harris, Mateo Valero, The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment., Conf. Computing Frontiers 2008: 67-78
Cristiana Bolchini, Antonio Miele, Design Space Exploration for the Design of Reliable., DFT 2008: 332-340
Cristiana Bolchini, Antonio Miele, Donatella Sciuto, Fault Models and Injection Strategies in SystemC Specifications, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Cristiana Bolchini, Yong-Bin Kim, Dimitris Gizopoulos, Mohammad Tehranipoor, 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008) 1-3 October 2008 Boston MA USA, IEEE Computer Society 2008
D. Bautista, Julio Sahuquillo, H. Hassan, Salvador Petit, José Duato, A simple power-aware scheduling for multicore systems when running real-time applications., IPDPS 2008: 1-7
D. R. Lester, M. Rudman, G. Metcalfe, H. M. Blackburn, Global parametric solutions of scalar transport, Journal of Computational Physics , Volume 227 Issue 6, Academic Press Professional, Inc., March 2008
D. Sánchez, M. J. Martín-Bautista, I. Blanco, C. Justicia de la Torre, Text Knowledge Mining: An Alternative to Text Data Mining, ICDMW '08: Proceedings of the 2008 IEEE International Conference on Data Mining Workshops - Volume 00 , Volume 00, IEEE Computer Society, December 2008
Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors, Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach., ISQED 2008: 663-669
Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson, Noise Interaction Between Power Distribution Grids and Substrate., ISQED 2008: 84-89
Daniel Díaz, Xoán C. Pardo, María J. Martín, Patricia González, Application-Level Fault-Tolerance Solutions for Grid Computing., CCGRID 2008: 554-559
Daniel Iancu, Mayan Moudgill, John Glossner, Jarmo Takala, Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set., SAMOS 2008: 126-135
Daniel Jones, AtomSwarm: A Framework for Swarm Improvisation., EvoWorkshops 2008: 423-432
Daniel Jones, Nigel Topham, High Speed CPU Simulation Using LTU Dynamic Binary Translation, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Daniel Sánchez, José María Serrano, Ignacio Blanco, Maria Jose Martín-Bautista, María-Amparo Vila, Using association rules to mine for strong approximate dependencies, Data Mining and Knowledge Discovery , Volume 16 Issue 3, Kluwer Academic Publishers, June 2008
Daniel Ziener, Jürgen Teich, Concepts for Autonomous Control Flow Checking for Embedded CPUs., ATC 2008: 234-248
Daniel Ziener, Jürgen Teich, Power Signature Watermarking of IP Cores for FPGAs., Signal Processing Systems 51(1): 123-136 (2008)
Daniele Masotti, Christine Nardini, Simona Rossi, Elena Bonora, Giovanni Romeo, Stefano Volinia, Luca Benini, TOM: enhancement and extension of a tool suite for in silico approaches to multigenic hereditary disorders., Bioinformatics 24(3): 428-429 (2008)
Daniele Masotti, Christine Nardini, Simona Rossi, Elena Bonora, Giovanni Romeo, Stefano Volinia, Luca Benini, TOM, Bioinformatics , Volume 24 Issue 3, Oxford University Press, February 2008
Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania, Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli, Network-on-Chip design and synthesis outlook., Integration 41(3): 340-359 (2008)
David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo Garcia Del Valle, Michael DeBole, Vijay Narayanan, Reliability-aware design for nanometer-scale devices., ASP-DAC 2008: 549-554
David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo, Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures., Integration 41(1): 38-48 (2008)
David B. Thomas, Wayne Luk, Resource efficient generators for the floating-point uniform and exponential distributions., ASAP 2008: 102-107
David B. Thomas, Wayne Luk, Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation., FCCM 2008: 229-238
David B. Thomas, Wayne Luk, Sampling from the exponential distribution using independent Bernoulli variates., FPL 2008: 239-244
David B. Thomas, Wayne Luk, FPGA-optimised high-quality uniform random number generators., FPGA 2008: 235-244
David B. Thomas, Wayne Luk, Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware., TRETS 1(2): (2008)
David Bernstein, John McDowall, Krishna Sankar, Stanley Poon, Message Streaming Network Components Architecture and In-Network Programming Model., SERA 2008: 11-18
David Carrera, Malgorzata Steinder, Ian Whalley, Jordi Torres, Eduard Ayguadé, Utility-based placement of dynamic Web applications with fairness goals., NOMS 2008: 9-16
David Carrera, Malgorzata Steinder, Ian Whalley, Jordi Torres, Eduard Ayguadé, Enabling Resource Sharing between Transactional and Batch Workloads Using Dynamic Application Placement., Middleware 2008: 203-222
David Carrera, Malgorzata Steinder, Ian Whalley, Jordi Torres, Eduard Ayguadé, Managing SLAs of heterogeneous workloads using dynamic application placement., HPDC 2008: 217-218
David Carrera, Vicenç Beltran, Jordi Torres, Eduard Ayguadé, A hybrid connector for efficient web servers., IJHPCN 5(5/6): 323-330 (2008)
David Gregg, Vikram S. Adve, Brian N. Bershad, Proceedings of the 4th International Conference on Virtual Execution Environments VEE 2008 Seattle WA USA March 5-7 2008, ACM 2008
David Llorens, Federico Prat, Andrés Marzal, Juan Miguel Vilar, M. J. Castro, Juan-Carlos Amengual, Sergio Barrachina, Antonio Castellanos, Salvador España Boquera, J. A. Gómez, J, The UJIpenchars Database: a Pen-Based Database of Isolated Handwritten Characters., LREC 2008
David R Lester, Real Number Calculations and Theorem Proving, TPHOLs '08: Proceedings of the 21st International Conference on Theorem Proving in Higher Order Logics, Springer-Verlag, August 2008
David Ramada, Carlos Domínguez, Houcine Hassan, Alfons Crespo, Real-time Embedded Architecture for Advanced Service Robots., ESA 2008: 81-87
Davide Brunelli, Luca Benini, Clemens Moser, Lothar Thiele, An Efficient Solar Energy Harvester for Wireless Sensor Nodes., DATE 2008: 104-109
Davide Brunelli, Massimo Maggiorotti, Luca Benini, Fabio Luigi Bellifemine, Analysis of Audio Streaming Capability of Zigbee Networks., EWSN 2008: 189-204
Davy Genbrugge, Lieven Eeckhout, Memory Data Flow Modeling in Statistical Simulation for the Efficient Exploration of Microprocessor Design Spaces., IEEE Trans. Computers 57(1): 41-54 (2008)
Diana Bautista, Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Duato, A simple power-aware scheduling for multicore systems when running real-time applications., IPDPS 2008: 1-7
Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Power-efficient Instruction Encoding Optimization for Various Architecture Classes., JCP 3(3): 25-38 (2008)
Diego R. Llanos Ferraris, David Orden, Belén Palop, Just-In-Time Scheduling for Loop-based Speculative Parallelization., PDP 2008: 334-342
Dieter Kranzlmüller, Uwe Schwiegelshohn, Yves Robert, Francisco F. Rivera, Topic 3: Scheduling and Load Balancing., Euro-Par 2008: 222
Dietmar Ebner, Florian Brandner, Bernhard Scholz, Andreas Krall, Peter Wiedermann, Albrecht Kadlec, Generalized instruction selection using SSA-graphs., LCTES 2008: 31-40
Dimitri Komatitsch, Jesús Labarta, David Michéa, A Simulation of Seismic Wave Propagation at High Resolution in the Inner Core of the Earth on 2166 Processors of MareNostrum., VECPAR 2008: 364-377
Dimitrios S. Nikolopoulos, Set-Top Supercomputing: Scalable Software for Scientific Simulations on GameConsoles., ERCIM News 2008(74): (2008)
Dimitrios S. Nikolopoulos, Godmar Back, Jyotirmaya Tripathi, Matthew Curtis-Maury, VT-ASOS: Holistic system software customization for many cores., IPDPS 2008: 1-5
Dimitrios Simos, Ioannis Papaefstathiou, Manolis G. H Katevenis, Building an FoC Using Large, Buffered Crossbar Cores, IEEE Design & Test , Volume 25 Issue 6, IEEE Computer Society Press, November 2008
Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Mihalis Maniatakos, Antonis Paschalis, Anand Raghunathan, Srivaths Ravi, Systematic Software-Based Self-Test for Pipelined Processors, IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 11, pp. 1441-1453, November 2008.
Dirk Koch, Christian Beckhoff, Jürgen Teich, ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS., FPL 2008: 119-124
Dirk Koch, Christian Haubelt, Jürgen Teich, Efficient Reconfigurable On-Chip Buses for FPGAs., FCCM 2008: 287-290
Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich, Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures., PATMOS 2008: 307-317
Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor, Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations., IEEE Trans. Computers 57(5): 686-701 (2008)
Dorit Nuzman, Ayal Zaks, Outer-loop vectorization: revisited for short SIMD architectures., PACT 2008: 2-11
Dorit Nuzman, Mircea Namolaru, Ayal Zaks, Jeff H. Derby, Compiling for an indirect vector register architecture., Conf. Computing Frontiers 2008: 199-208
Dragan Stojanovic, Apostolos N. Papadopoulos, Bratislav Predic, Slobodanka Djordjevic-Kajan, Alexandros Nanopoulos, Continuous range monitoring of mobile objects in road networks, Data & Knowledge Engineering , Volume 64 Issue 1, Elsevier Science Publishers B. V., January 2008
Dror G. Feitelson, Looking at data., IPDPS 2008: 1-9
Duncan A. Buell, Wayne Luk, Introduction., TRETS 1(1): (2008)
E. Pamba Capo-Chichi, Hervé Guyennet, Jean-Michel Friedt, Ian Johnson, Craig Duffy, Design and implementation of a generic hybrid wireless sensor network platform., LCN 2008: 836-840
Edward Stott, N. Pete Sedcole, Peter Y. K. Cheung, Fault tolerant methods for reliability in FPGAs., FPL 2008: 415-420
Eelco Dolstra, Jurriaan Hage, Bastiaan Heeren, Stefan Holdermans, Johan Jeuring, Andres Löh, Clara Löh, Arie Middelkoop, Alexey Rodriguez, John van Schie, Report on the tenth ICFP programming contest., ICFP 2008: 397-408
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Configurable Data Memory for Multimedia Processing., Signal Processing Systems 50(2): 231-249 (2008)
Eero Wallenius, Timo Hämäläinen, Kari Halttunen, XML Based 3G/LTE Network and Service Management Concept., ICN 2008: 308-317
Eladio Gutiérrez, Oscar G. Plata, Emilio L. Zapata, An analytical model of locality-based parallel irregular reductions., Parallel Computing 34(3): 133-157 (2008)
Eladio Gutiérrez, Sergio Romero, María A. Trenas, Emilio L. Zapata, Memory Locality Exploitation Strategies for FFT on the CUDA Architecture., VECPAR 2008: 430-443
Eladio Gutiérrez, Sergio Romero, María A. Trenas, Emilio L. Zapata, Parallel Quantum Computer Simulation on the CUDA Architecture., ICCS (1) 2008: 700-709
Elias Athanasopoulos, A. Makridakis, Spyros Antonatos, Demetres Antoniades, Sotiris Ioannidis, Kostas G. Anagnostakis, Evangelos P. Markatos, Antisocial Networks: Turning a Social Network into a Botnet., ISC 2008: 146-160
Elisa Ficarra, Giovanni De Micheli, Sungroh Yoon, Luca Benini, Enrico Macii, Joint co-clustering: Co-clustering of genomic and clinical bioimaging data, Computers & Mathematics with Applications , Volume 55 Issue 5, Pergamon Press, Inc., March 2008
Elisabetta Farella, Augusto Pieracci, Luca Benini, Laura Rocchi, Andrea Acquaviva, Interfacing human and computer with wireless body area sensor networks: the WiMoCA solution., Multimedia Tools Appl. 38(3): 337-363 (2008)
Elisabetta Farella, Omar Cafini, Luca Benini, Bruno Riccò, A smart wireless glove for gesture interaction., SIGGRAPH Posters 2008: 44
Elisardo Antelo, Julio Villalba, Emilio L. Zapata, A Low-Latency Pipelined 2D and 3D CORDIC Processors., IEEE Trans. Computers 57(3): 404-417 (2008)
Emeric Kwemou, Lizhe Wang, Jie Tao, Marcel Kunze, David Kramer, Wolfgang Karl, Grid Virtualization Engine: Providing Virtual Resources for Grid Infrastructure., PASA 2008: 27-36
Emiliano Betti, Daniel P. Bovet, Marco Cesati, Roberto Gioiosa, Hard Real-Time Performances in Multiprocessor-Embedded Systems Using ASMP-Linux., EURASIP J. Emb. Sys. 2008: (2008)
Emilio Luque, Tomàs Margalef, Domingo Benitez, Euro-Par 2008 - Parallel Processing 14th International Euro-Par Conference Las Palmas de Gran Canaria Spain August 26-29 2008 Proceedings, Springer 2008
Emre Özer, Andy Nisbet, David Gregg, A stochastic bitwidth estimation technique for compact and low-power custom processors., ACM Trans. Embedded Comput. Syst. 7(3): (2008)
Emre Özer, Ronald G. Dreslinski, Trevor N. Mudge, Stuart Biles, Krisztián Flautner, Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor., SAMOS 2008: 12-22
Enno Lübbers, Marco Platzner, Communication and Synchronization in Multithreaded Reconfigurable Computing Systems., ERSA 2008: 83-89
Enno Lübbers, Marco Platzner, A portable abstraction layer for hardware threads., FPL 2008: 17-22
Enric Tejedor, Rosa M. Badia, COMP Superscalar: Bringing GRID Superscalar and GCM Together., CCGRID 2008: 185-193
Enrique Asensio, Juan M. Orduña, Pedro Morillo, Analyzing the Network Traffic Requirements of Multiplayer Online Games, ADVCOMP '08: Proceedings of the 2008 The Second International Conference on Advanced Engineering Computing and Applications in Sciences - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Enrique S. Quintana-Ortí, Robert A. van de Geijn, Updating an LU Factorization with Pivoting., ACM Trans. Math. Softw. 35(2): (2008)
Eric A. Antonelo, Benjamin Schrauwen, Dirk Stroobandt, Event detection and localization for small mobile robots using reservoir computing., Neural Networks 21(6): 862-871 (2008)
Eric A. Antonelo, Benjamin Schrauwen, Dirk Stroobandt, Imitation Learning of an Intelligent Navigation System for Mobile Robots Using Reservoir Computing., SBRN 2008: 93-98
Eric A. Antonelo, Benjamin Schrauwen, Dirk Stroobandt, Mobile robot control in the road sign problem using Reservoir Computing networks., ICRA 2008: 911-916
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai, A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs., FPGA 2008: 77-86
Ernie Chan, Field G. Van Zee, Paolo Bientinesi, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn, SuperMatrix: a multithreaded runtime scheduling system for algorithms-by-blocks., PPOPP 2008: 123-132
Ernst Gunnar Gran, Sven-Arne Reinemo, Dragon kill points: loot distribution in MMORPGs, NetGames '08: Proceedings of the 7th ACM SIGCOMM Workshop on Network and System Support for Games, ACM, October 2008
Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis, Nectarios Koziris, Exploring the performance limits of simultaneous multithreading for memory intensive applications., The Journal of Supercomputing 44(1): 64-97 (2008)
Evangelos Koukis, Anastassios Nanos, Nectarios Koziris, Synchronized send operations for efficient streaming block I/O over Myrinet., IPDPS 2008: 1-8
Ezequiel Herruzo, Oscar G. Plata, Emilio L. Zapata, Using Padding to Optimize Locality in Scientific Applications., ICCS (1) 2008: 863-872
F. Redaelli, M. D. Santambrogio, S. Ogrenci Memik, An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures, RECONFIG '08: Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs - Volume 00 , Volume 00, IEEE Computer Society, December 2008
Fabian Diet, Erik H. D'Hollander, Kristof Beyls, Harald Devos, Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler., DELTA 2008: 142-147
Fabian Nowak, Rainer Buchty, Wolfgang Karl, Adaptive Cache Infrastructure: Supporting Dynamic Program Changes following Dynamic Program Behavior., PASA 2008: 59-68
Fabiano Hessel, Kenneth B. Kent, Dionisios N. Pnevmatikatos, Editorial: Embedded systems - new challenges and future directions., ACM Trans. Embedded Comput. Syst. 7(4): (2008)
Fabio Cancare, Marco D. Santambrogio, Donatella Sciuto, A design flow tailored for self dynamic reconfigurable architecture., IPDPS 2008: 1-8
Fabio Garzia, Claudio Brunelli, Davide Rossi, Jari Nurmi, Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture., IPDPS 2008: 1-6
Fabrizio Ferrandi, Pier Luca Lanzi, Daniele Loiacono, Christian Pilato, Donatella Sciuto, A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis., ISVLSI 2008: 417-422
Fabrizio Iacopetti, Luca Fanucci, Roberto Roncella, David Giusti, Andrea Scebba, Game Console Controller Interface for People with Disability., CISIS 2008: 757-762
Fabrizio Mulas, Michele Pittau, Marco Buttu, Salvatore Carta, Andrea Acquaviva, Luca Benini, David Atienza, Giovanni De Micheli, Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures., DATE 2008: 734-739
Faith Ellen, Panagiota Fatourou, Eric Ruppert, The space complexity of unbounded timestamps., Distributed Computing 21(2): 103-115 (2008)
Farrukh Nadeem, Radu Prodan, Thomas Fahringer, Characterizing Modeling and Predicting Dynamic Resource Availability in a Large Scale Multi-purpose Grid., CCGRID 2008: 348-357
Faruk Bagci, Theo Ungerer, Nader Bagherzadeh, ESTR - Energy Saving Token Ring Protocol for Wireless Sensor Networks., ICWN 2008: 3-9
Felix Reimann, Michael Glabeta, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich, Symbolic voter placement for dependability-aware system synthesis., CODES+ISSS 2008: 237-242
Ferad Zyulkyarov, Adrian Cristal, Sanja Cvijic, Eduard Ayguade, Mateo Valero, Osman Unsal, Tim Harris, WormBench: a configurable workload for evaluating transactional memory systems, MEDEA '08: Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, October 2008
Filip Blagojevic, Matthew Curtis-Maury, Jae-Seung Yeom, Scott Schneider, Dimitrios S. Nikolopoulos, Scheduling Asymmetric Parallelism on a PlayStation3 Cluster., CCGRID 2008: 146-153
Filip Blagojevic, Xizhou Feng, Kirk W. Cameron, Dimitrios S. Nikolopoulos, Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE., HiPEAC 2008: 38-52
Florent Bouchez, Alain Darte, Fabrice Rastello, Advanced conservative and optimistic register coalescing., CASES 2008: 147-156
Florian Kluge, Jörg Mische, Sascha Uhrig, Theo Ungerer, An Operating System Architecture for Organic Computing in Embedded Real-Time Systems., ATC 2008: 343-357
Florian Kluge, Sascha Uhrig, Jörg Mische, Theo Ungerer, A Two-Layered Management Architecture for Building Adaptive Real-Time Systems., SEUS 2008: 126-137
Florin Isaila, Javier Javier García Blas, Jesús Carretero, Wei-keng Liao, Alok N. Choudhary, AHPIOS: An MPI-Based Ad Hoc Parallel I/O System., ICPADS 2008: 253-260
Florin Isaila, Walter F. Tichy, Mapping functions and data redistribution for parallel files., The Journal of Supercomputing 46(3): 213-236 (2008)
Fotis Kerasiotis, Tsenka Stoyanova, Aggeliki Prayati, George Papadopoulos, A Topology-Oriented Solution Providing Accuracy for Outdoors RSS-Based Tracking in WSNs, SENSORCOMM '08: Proceedings of the 2008 Second International Conference on Sensor Technologies and Applications - Volume 00 , Volume 00, IEEE Computer Society, August 2008
Francesco Bruschi, Vincenzo Rana, Donatella Sciuto, An architecture for dynamically reconfigurable real time audio processing systems., ESTImedia 2008: 81-86
Francesco D'Ascoli, L. Bacciarelli, Massimiliano Melani, Luca Fanucci, G. Ricotti, E. Pardi, F. Vincis, Massimiliano Forliti, Marco De Marinis, A Programmable and Low-EMI Integrated Half-Bridge Driver in BCD Technology., DATE 2008: 879-884
Francesco Redaelli, Marco D. Santambrogio, Donatella Sciuto, Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems., DATE 2008: 519-522
Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, Israel Koren, Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?., DFT 2008: 202-210
Francesco Sechi, Luca Fanucci, Stefano Luschi, Simone Perini, Matteo Madesani, Design of a Distributed Embedded System for Domotic Applications, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Francesco Vitullo, Nicola E. L'Insalata, Esa Petri, Sergio Saponara, Luca Fanucci, Michele Casula, Riccardo Locatelli, Marcello Coppola, Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip, IEEE Transactions on Computers , Volume 57 Issue 9, IEEE Computer Society, September 2008
Francis Wyffels, Benjamin Schrauwen, David Verstraeten, Dirk Stroobandt, Band-pass Reservoir Computing., IJCNN 2008: 3204-3209
Francis Wyffels, Benjamin Schrauwen, Dirk Stroobandt, Stable Output Feedback in Reservoir Computing Using Ridge Regression., ICANN (1) 2008: 808-817
Francisco A. Pujol, Rafael Espí, Higinio Mora, José Luis Sánchez, A Fuzzy Approach to Skin Color Detection, MICAI '08: Proceedings of the 7th Mexican International Conference on Artificial Intelligence: Advances in Artificial Intelligence, Springer-Verlag, October 2008
Francisco D. Igual, Rafael Mayo, Enrique S. Quintana-Ortí, Attaining High Performance in General-Purpose Computations on Current Graphics Processors., VECPAR 2008: 406-419
Francisco Gilabert, Simone Medardoni, Davide Bertozzi, Luca Benini, María Engracia Gómez, Pedro López, José Duato, Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework., NOCS 2008: 107-116
Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata, New SIMD instructions set for image processing applications enhancement., ICIP 2008: 1396-1399
Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata, SIMD Enhancements for a Hough Transform Implementation, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata, Pipelined Architecture for Additive Range Reduction., Signal Processing Systems 53(1-2): 103-112 (2008)
Francisco J. Rincon, Michele Paselli, Joaquin Recas, Qin Zhao, Marcos Sanchez-Elez, David Atienza, Julien Penders, Giovanni De Micheli, OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks., DATE 2008: 1027-1032
Francisco Javier García Blas, Florin Isaila, David E. Singh, Jesús Carretero, View-Based Collective I/O for MPI-IO., CCGRID 2008: 409-416
Francisco Javier García Blas, Florin Isaila, Jesús Carretero, Thomas Großmann, Implementation and Evaluation of an MPI-IO Interface for GPFS in ROMIO., PVM/MPI 2008: 159-166
Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev, Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array., HiPEAC 2008: 66-81
Frank E. B. Ophelders, Samarjit Chakraborty, Henk Corporaal, Intra- and inter-processor hybrid performance modeling for MPSoC architectures., CODES+ISSS 2008: 91-96
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich, PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications., ARC 2008: 284-289
Frank Kienle, Norbert Wehn, Macro Interleaver Design for Bit Interleaved Coded Modulation with Low-Density Parity-Check Codes., VTC Spring 2008: 763-766
Frank Olaf Sem-Jacobsen, Olav Lysne, Fault tolerance with shortest paths in regular and irregular networks., IPDPS 2008: 1-11
Frank Olaf Sem-Jacobsen, Tor Skeie, Maintaining Quality of Service with Dynamic Fault Tolerance in Fat-Trees., HiPC 2008: 451-464
Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras, Low power microarchitecture with instruction reuse., Conf. Computing Frontiers 2008: 149-158
Frederik Naessens, Bruno Bougard, Siebert Bressinck, Lieven Hollevoet, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor, A unified instruction set programmable architecture for multi-standard advanced forward error correction., SiPS 2008: 31-36
Frederik Vandeputte, Lieven Eeckhout, Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior., HiPEAC 2008: 320-334
Frederik Vandeputte, Lieven Eeckhout, Finding Stress Patterns in Microprocessor Workloads, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Fredrik Warg, Per Stenström, Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor., International Journal of Parallel Programming 36(2): 166-183 (2008)
G. Vigueras, M. Lozano, J. M. Orduña, F. Grimaldo, Improving the Performance of Partitioning Methods for Crowd Simulations, HIS '08: Proceedings of the 2008 8th International Conference on Hybrid Intelligent Systems, IEEE Computer Society, September 2008
Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva, Massive parallel LDPC decoding on GPU., PPOPP 2008: 83-90
Gabriel Falcão Paiva Fernandes, Vítor Manuel Mendes da Silva, Marco Alexandre Cravo Gomes, Leonel Augusto Sousa, Edge Stream Oriented LDPC Decoding., PDP 2008: 237-244
Gala Yadgar, Michael Factor, Kai Li, Assaf Schuster, MC2: Multiple Clients on a Multilevel Cache., ICDCS 2008: 722-730
Genaro Costa, Josep Jorba, Anna Morajko, Tomàs Margalef, Emilio Luque, Performance models for dynamic tuning of parallel applications on Computational Grids., CLUSTER 2008: 376-385
George Papadopoulos, Elaine Pearson, Steve Green, Effective simulations to support academics in inclusive online learning design., ASSETS 2008: 275-276
George Papadopoulos, Martin Brown, Minimum entropy parameter estimation: Application to the RKIP regulated ERK signaling pathway., IJCNN 2008: 1864-1871
George Russell, Alastair F. Donaldson, Paul Sheppard, Tackling online game development problems with a novel network scripting language., NETGAMES 2008: 85-90
Georgios I. Goumas, Kornilios Kourtis, Nikos Anastopoulos, Vasileios Karakasis, Nectarios Koziris, Understanding the Performance of Sparse Matrix-Vector Multiplication., PDP 2008: 283-292
Gerard K. Rauwerda, Paul M. Heysters, Gerard J. M. Smit, Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware., IEEE Trans. VLSI Syst. 16(1): 3-13 (2008)
Gerard París, Marcel Arrufat, Pedro García López, Marc Sánchez-Artigas, An Application Layer Multicast for Collaborative Scenarios: The OMCAST Protocol, ICN '08: Proceedings of the Seventh International Conference on Networking (icn 2008) - Volume 00 , Volume 00, IEEE Computer Society, April 2008
Gerardo Fernández-Escribano, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, Antonio Garrido, A Fast MB Mode Decision Algorithm for MPEG-2 to H.264 P-Frame Transcoding., IEEE Trans. Circuits Syst. Video Techn. 18(2): 172-185 (2008)
Gerardo Fernández-Escribano, Jens Bialkowski, José A. Gámez, Hari Kalva, Pedro Cuenca, Luis Orozco-Barbosa, André Kaup, Low-Complexity Heterogeneous Video Transcoding Using Data Mining., IEEE Transactions on Multimedia 10(2): 286-299 (2008)
Gerardo Fernández-Escribano, Pedro Cuenca, Luis Orozco-Barbosa, Antonio Jose Garrido del Solo, Hari Kalva, Simple intra prediction algorithms for heterogeneous MPEG-2/H.264 video transcoders., Multimedia Tools Appl. 38(1): 1-25 (2008)
German Rodriguez, Rosa M. Badia, Jesus Labarta, An Evaluation of Marenostrum Performance, International Journal of High Performance Computing Applications , Volume 22 Issue 1, Sage Publications, Inc., February 2008
Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, Robust optimization of SoC architectures: A multi-scenario approach., ESTImedia 2008: 7-12
Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints., SASP 2008: 75-82
Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Giorgos Dimitrakopoulos, Costas Galanopoulos, Christos Mavrokefalidis, Dimitris Nikolos, Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units., IEEE Trans. VLSI Syst. 16(7): 837-850 (2008)
Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos, Fast arbiters for on-chip network switches., ICCD 2008: 664-670
Giorgos Vasiliadis, Spyros Antonatos, Michalis Polychronakis, Evangelos P. Markatos, Sotiris Ioannidis, Gnort: High Performance Network Intrusion Detection Using Graphics Processors., RAID 2008: 116-134
Giovanni Agosta, Francesco Bruschi, Donatella Sciuto, Static Analysis of Transaction-Level Communication Models., IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1412-1424 (2008)
Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto, ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration., ASP-DAC 2008: 673-678
Giovanni Beltrame, Luca Fossati, Donatella Sciuto, Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design., CODES+ISSS 2008: 7-12
Giovanni Beltrame, Luca Fossati, Donatella Sciuto, High-Level Modeling and Exploration of Reconfigurable MPSoCs, AHS '08: Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems - Volume 00 , Volume 00, IEEE Computer Society, June 2008
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti, Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip, IEEE Transactions on Computers
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti, Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip., IEEE Trans. Computers 57(6): 809-820 (2008)
Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Alfredo Remón, Robert A. van de Geijn, An Algorithm-by-Blocks for SuperMatrix Band Cholesky Factorization., VECPAR 2008: 228-239
Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Ernie Chan, Robert A. van de Geijn, Field G. Van Zee, Scheduling of QR Factorization Algorithms on SMP and Multi-Core Architectures., PDP 2008: 301-310
Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Ernie Chan, Robert A. van de Geijn, Field G. Van Zee, Design of scalable dense linear algebra libraries for multithreaded architectures: the LU factorization., IPDPS 2008: 1-8
Grigori Fursin, Olivier Temam, Collective Optimization, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Grzegorz Danilewicz, Wojciech Kabacinski, Marek Michalski, Mariusz Zal, A New Control Algorithm for Wide-Sense Nonblocking Multiplane Photonic Banyan-Type Switching Fabrics with Zero Crosstalk., IEEE Journal on Selected Areas in Communications 26(S-3): 54-64 (2008)
Guang R. Gao, Mitsuhisa Sato, Eduard Ayguadé, Guest Editors Introduction: Special Issue on OpenMP., International Journal of Parallel Programming 36(3): 287-288 (2008)
Guillermo L. Taboada, Juan Touriño, Ramon Doallo, Java Fast Sockets: Enabling high-speed Java communications on high performance clusters., Computer Communications 31(17): 4049-4059 (2008)
Guillermo Vigueras, Miguel Lozano, Carlos Perez, Juan M. Orduña, A Scalable Architecture for Crowd Simulation: Implementing a Parallel Action Server., ICPP 2008: 430-437
Guna Santos, Angelo Duarte, Dolores Rexachs, Emilio Luque, Providing Non-stop Service for Message-Passing Based Parallel Applications with RADIC., Euro-Par 2008: 58-67
Guna Santos, Angelo Duarte, Dolores Rexachs, Emilio Luque, Increasing the Performability of Computer Clusters Using RADIC II., ARES 2008: 653-658
Gustavo M.Callico, Sebastian Lopez , Karlos Tarajano Beracoechea, Jose Lopez , Roberto Sarmiento , Impact of Fast Motion Estimation Algorithms on Super-Resolved Video Sequences, International Conference on Consumer Electronics (ICCE)
Håkan Lundvall, Kristian Stavåker, Peter Fritzson, Christoph W. Kessler, Automatic parallelization of simulation code for equation-based models with software pipelining and measurements on three platforms., SIGARCH Computer Architecture News 36(5): 46-55 (2008)
Håkon Kvale Stensland, Olav Lysne, Roy Nordstrøm, Hugo Kohmann, Making an SCI fabric dynamically fault tolerant., IPDPS 2008: 1-8
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne, Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming., DATE 2008: 1256-1261
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne, Efficient synthesis of compressor trees on FPGAs., ASP-DAC 2008: 138-143
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne, A novel FPGA logic block for improved arithmetic performance., FPGA 2008: 171-180
Hai Ngoc Pham, Jie Xiang, Yan Zhang, Tor Skeie, QoS-Aware Channel Selection in Cognitive Radio Networks: A Game-Theoretic Approach., GLOBECOM 2008: 4877-4883
Hans Eberle, Pedro Javier García, Jose Flich, José Duato, Robert Drost, Nils Gura, David Hopkins, Wladek Olesinski, High-radix crossbar switches enabled by proximity communication., SC 2008: 32
Hans Vandierendonck, André Seznec, Speculative return address stack management revisited., TACO 5(3): (2008)
Hans Vandierendonck, Koen De Bosschere, Constructing Optimal XOR-Functions to Minimize Cache Conflict Misses., ARCS 2008: 261-272
Hans Vandierendonck, Sean Rul, Michiel Questier, Koen De Bosschere, Experiences with Parallelizing a Bio-informatics Program on the Cell BE., HiPEAC 2008: 161-175
Hans Vandierendonck, Veerle Desmet, Koen De Bosschere, Behavior-Based Branch Prediction by Dynamically Clustering Branch Instructions., J. Inf. Sci. Eng. 24(3): 919-931 (2008)
Hans-Joachim Bungartz, Javier D. Bruguera, Peter Arbenz, Bruce Hendrickson, Topic 10: Parallel Numerical Algorithms., Euro-Par 2008: 778-779
Harald Servat, Cecilia González-Alvarez, Xavier Aguilar, Daniel Cabrera-Benitez, Daniel Jiménez-González, Drug Design Issues on the Cell BE., HiPEAC 2008: 176-190
Hector Montaner, Federico Silla, Vicente Santonja, José Duato, Network Reconfiguration Suitability for Scientific Applications., ICPP 2008: 312-319
Hector Pettenghi, Maria Jose Avedillo, Jose Maria Quintana, A novel contribution to the RTD-Based Threshold Logic Family, IEEE Int. Symp. on Circuits and Syst., pp. 2350-2353
Hector Pettenghi, Maria Jose Avedillo, Jose Maria Quintana, Using multi-threshold threshold gates in RTD-based logic design: A case study, Microelectron. J., vol. 39, pp. 241-247
Hector Pettenghi, Maria Jose Avedillo, Jose Maria Quintana, RTD based Logic Circuits Using Generalized Threshold Gates, Proc. on Design of Circuits and Integrated Syst. Conf.
Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll, Application-specific reconfigurable processors., FPL 2008: 350
Heiner Giefers, Reconfigurable many-cores with lean interconnect., FPL 2008: 707-708
Heiner Giefers, Marco Platzner, Realizing reconfigurable mesh algorithms on softcore arrays., ICSAMOS 2008: 41-48
Herbert Bos, Evangelos P. Markatos, Proceedings of the First European Workshop on System Security EUROSEC 2008 Glasgow Scotland UK March 31 2008, ACM 2008
Hristo Nikolov, Mark Thompson, Todor Stefanov, Andy D. Pimentel, Simon Polstra, R. Bose, Claudiu Zissulescu, Ed F. Deprettere, Daedalus: toward composable multimedia MP-SoC design., DAC 2008: 574-579
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere, Automated Integration of Dedicated Hardwired IP Cores in Heterogeneous MPSoCs Designed with ESPAM., EURASIP J. Emb. Sys. 2008: (2008)
Huan Fang, Mats Brorsson, Scalable directory architecture for distributed shared memory chip multiprocessors, ACM SIGARCH Computer Architecture News
Huazhu Song, Bin Zhao, You Zhou, Yi Lu, Wang Meng, Fast Design and Construction for Network Application Solution Based on .Net 3.5 Framework., CSSE (2) 2008: 420-423
I. Salawdeh, Eduardo César, Anna Morajko, Tomàs Margalef, Emilio Luque, Performance Model for Parallel Mathematical Libraries Based on Historical Knowledgebase., Euro-Par 2008: 110-119
Ian Rogers, Jisheng Zhao, Chris C. Kirkham, Ian Watson, Constraint based optimization of stationary fields., PPPJ 2008: 95-104
Ian Watson, Hisham El-Shishiny, Proceedings of the 1st international forum on Next-generation multicore/manycore technologies IFMT 2008 Cairo Egypt November 24-25 2008, ACM 2008
Ian Watson, Jonathan Rubin, CASPER: A Case-Based Poker-Bot., Australasian Conference on Artificial Intelligence 2008: 594-600
Igor Loi, Federico Angiolini, Luca Benini, Developing Mesochronous Synchronizers to Enable 3D NoCs., DATE 2008: 1414-1419
Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini, A low-overhead fault tolerance scheme for TSV-based 3D network on chip links., ICCAD 2008: 598-602
Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser, Using an MDE Approach for Modeling of Interconnection Networks., ISPAN 2008: 289-294
Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser, MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs., ESTImedia 2008: 47-52
Ioana Burcea, Stephen Somogyi, Andreas Moshovos, Babak Falsafi, Predictor virtualization., ASPLOS 2008: 157-167
Ioannis Konstantinou, Dimitrios Tsoumakos, Nectarios Koziris, PASS It ON (PASSION): An Adaptive Online Load-Balancing Algorithm for Distributed Range-Query Specialized Systems., OTM Workshops 2008: 3-5
Ioannis Riakiotakis, Georgios I. Goumas, Nectarios Koziris, Fiori-Anastasia Metallinou, Ioannis A. Daglis, Evaluation of dynamic scheduling methods in simulations of storm-time ion acceleration., IPDPS 2008: 1-8
Ioannis Sarkas, Dimitrios Mavridis, Michail Papamichail, George Papadopoulos, Large and small signal distortion analysis using modified Volterra series, Analog Integrated Circuits and Signal Processing , Volume 54 Issue 2, Kluwer Academic Publishers, February 2008
Ioannis Sourdis, Dionisios N. Pnevmatikatos, Stamatis Vassiliadis, Scalable Multigigabit Pattern Matching for Packet Inspection., IEEE Trans. VLSI Syst. 16(2): 156-166 (2008)
Ioannis Sourdis, João Bispo, João M. P. Cardoso, Stamatis Vassiliadis, Regular Expression Matching in Reconfigurable Hardware., Signal Processing Systems 51(1): 99-121 (2008)
Ioannis Voyiatzis, Antonis Paschalis, Dimitris Gizopoulos, Costas Halatsis, E.Makri, Miltiadis Hatzimihail, An Input Vector Monitoring Concurrent BIST Architecture Based on a Pre-computed Test Set, IEEE Transactions on Computers, vol. 57, no. 8, pp. 1012-1022, August 2008.
Iouliia Skliarova, Valery Sklyarov, Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware., VLSI Design 2008: 255-260
Isaac Gelado, John H. Kelm, Shane Ryoo, Steven S. Lumetta, Nacho Navarro, Wen-mei W. Hwu, CUBA: an architecture for efficient CPU/co-processor data communication., ICS 2008: 299-308
Isaac Keslassy, The Load-Balanced Router: How to Design a Scalable Packet Switch withoutScheduling and Reconfiguring It, The Load-Balanced Router: How to Design a Scalable Packet Switch withoutScheduling and Reconfiguring It, VDM Verlag, August 2008
Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos, An instruction set extension for java bytecodes translation acceleration., ICSAMOS 2008: 116-123
Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos, A predecoding technique for ILP exploitation in Java processors., Journal of Systems Architecture - Embedded Systems Design 54(7): 707-728 (2008)
Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco A. Ramírez, Adrián Cristal, Mateo Valero, A distributed processor state management architecture for large-window processors., MICRO 2008: 11-22
Ismo Hänninen, Jarmo Takala, Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology., SAMOS 2008: 43-52
Ismo Hänninen, Jarmo Takala, Reliability of n-Bit Nanotechnology Adder., ISVLSI 2008: 34-39
Itamar Cohen, Ori Rottenstreich, Isaac Keslassy, Statistical Approach to NoC Design., NOCS 2008: 171-180
Iván Díaz, G. Fernandez, María J. Martín, Patricia González, Juan Touriño, Integrating the common information model with MDS4., GRID 2008: 298-303
Ivano Bonesana, Marco Paolieri, Marco D. Santambrogio, An adaptable FPGA-based System for Regular Expression Matching., DATE 2008: 1262-1267
Ivona Brandic, Sabri Pllana, Siegfried Benkner, Specification planning and execution of QoS-aware Grid workflows within the Amadeus environment., Concurrency and Computation: Practice and Experience 20(4): 331-345 (2008)
Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev, A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration., ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
Izchak Sharfman, Assaf Schuster, Daniel Keren, Shape sensitive geometric monitoring., PODS 2008: 301-310
Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer, IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer, Exploiting spare resources of in-order SMT processors executing hard real-time threads., ICCD 2008: 371-376
Jörn Altmann, Dirk Neumann, Thomas Fahringer, Grid Economics and Business Models 5th International Workshop GECON 2008 Las Palmas de Gran Canaria Spain August 26 2008. Proceedings, Springer 2008
Jürgen Hofer, Thomas Fahringer, A Multi-Perspective Taxonomy for Systematic Classification of Grid Faults., PDP 2008: 126-130
Jürgen Hofer, Thomas Fahringer, Supporting Parameter Sweep Applications with Synthesized Grid Services., Euro-Par 2008: 26-36
Jürgen Hofer, Thomas Fahringer, Synthesizing Byzantine Fault-Tolerant Grid Application Wrapper Services., CCGRID 2008: 467-474
Jürgen Hofer, Thomas Fahringer, Grid Application Fault Diagnosis Using Wrapper Services and Machine Learning., Int. J. Cooperative Inf. Syst. 17(3): 283-299 (2008)
Jürgen Teich, Invasive Algorithms and Architectures (Invasive Algorithmen und Architekturen)., it - Information Technology 50(5): 300-310 (2008)
J. A. Riveiro, M. F. Marey, J. L. Marco, C. J. Alvarez, Procedure for the classification and characterization of farms for agricultural production planning: Application in the Northwest of Spain, Computers and Electronics in Agriculture , Volume 61 Issue 2, Elsevier Science Publishers B. V., May 2008
J. Carlos Saez, José Ignacio Gómez, Manuel Prieto, Improving Priority Enforcement via Non-Work-Conserving Scheduling., ICPP 2008: 99-106
J. L. Aragón, Gerardo G. Naumis, M. Bai, M. Torres, P. K. Maini, Turbulent Luminance in Impassioned van Gogh Paintings, Journal of Mathematical Imaging and Vision , Volume 30 Issue 3, Kluwer Academic Publishers, March 2008
J. L. Martínez, W. A. Rajitha Jayaruwan Weerakkody, Pedro Cuenca, Francisco J. Quiles, Warnakulasuriya Anil Chandana Fernando, Transform Domain Wyner-Ziv Codec Based on Turbo Trellis Codes Modulation., MMM 2008: 413-424
J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Directory-Based Conflict Detection in Hardware Transactional Memory., HiPC 2008: 541-554
J. Rubén Titos Gil, Manuel E. Acacio, José M. García Carrasco, Characterization of Conflicts in Log-Based Transactional Memory (LogTM)., PDP 2008: 30-37
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, Bill S. H. Kwan, Chris C. C. Cheung, Anthony P. C. Chan, Philip Heng Wai Leong, Map-reduce as a Programming Model for Custom Computing Machines., FCCM 2008: 149-159
Jacob Jan-David Mol, Johan A. Pouwelse, Dick H. J. Epema, Henk J. Sips, Free-Riding Fairness and Firewalls in P2P File-Sharing., Peer-to-Peer Computing 2008: 301-310
Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis, Comparative evaluation of memory models for chip multiprocessors., TACO 5(3): (2008)
JaeWoong Chung, Jiwon Seo, Woongki Baek, Chi Cao Minh, Austen McDonald, Christos Kozyrakis, Kunle Olukotun, Improving software concurrency with hardware-assisted memory snapshot., SPAA 2008: 363
JaeWoong Chung, Michael Dalton, Hari Kannan, Christos Kozyrakis, Thread-safe dynamic binary translation using transactional memory., HPCA 2008: 279-289
JaeWoong Chung, Woongki Baek, Nathan Grasso Bronson, Jiwon Seo, Christos Kozyrakis, Kunle Olukotun, Ased: availability security and debugging support usingtransactional memory., SPAA 2008: 366
Jakub Kurzak, Hatem Ltaief, Jack J. Dongarra, Rosa M. Badia, Scheduling for Numerical Linear Algebra Library at Scale., High Performance Computing Workshop 2008: 3-26
James C. Brodman, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Design Issues in Parallel Array Languages for Shared Memory., SAMOS 2008: 208-217
James R. Larus, Christos Kozyrakis, Transactional memory., Commun. ACM 51(7): 80-88 (2008)
Jan Cappaert, Bart Preneel, Bertrand Anckaert, Matias Madou, Koen De Bosschere, Towards Tamper Resistant Code Encryption: Practice and Experience., ISPEC 2008: 86-100
Jan Gustafsson, Björn Lisper, Markus Schordan, Christian Ferdinand, Peter Gliwa, Marek Jersak, Guillem Bernat, ALL-TIMES - A European Project on Integrating Timing Technology., ISoLA 2008: 445-459
Janne Rintanen, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen, Application Server for Wireless Sensor Networks., SAMOS 2008: 248-257
Jarno Vanne, Eero Aho, Timo D. Hämäläinen, Kimmo Kuusilinna, A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms., IEEE Trans. Circuits Syst. Video Techn. 18(4): 538-543 (2008)
Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, James W. Tschanz, Refueling: Preventing Wire Degradation due to Electromigration, IEEE Micro , Volume 28 Issue 6, IEEE Computer Society Press, November 2008
Javier García Blas, Florin Isaila, David E. Singh, Jesús Carretero, View-Based Collective I/O for MPI-IO., CCGRID 2008: 409-416
Javier Merino, Valentín Puente, Pablo Prieto, José Ángel Gregorio, SP-NUCA: a cost effective dynamic non-uniform cache architecture, SIGARCH Computer Architecture News , Volume 36 Issue 2, ACM, May 2008
Javier Navaridas, José Miguel-Alonso, Francisco Javier Ridruejo Perez, On synthesizing workloads emulating MPI applications., IPDPS 2008: 1-8
Javier Setoain, Manuel Prieto, Christian Tenllado, Francisco Tirado, GPU for Parallel On-Board Hyperspectral Image Processing, International Journal of High Performance Computing Applications , Volume 22 Issue 4, Sage Publications, Inc., November 2008
Javier Verdú, Mario Nemirovsky, Mateo Valero, MultiLayer processing - an execution model for parallel stateful packet processing., ANCS 2008: 79-88
Jean Christophe Beyler, Michael Klemm, Michael Philippsen, Philippe Clauss, Automatic Prefetching with Binary Code Rewriting in Object-Based DSMs., Euro-Par 2008: 643-653
Jehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser, An MPSoC architecture for the Multiple Target Tracking application in driver assistant system., ASAP 2008: 126-131
Jens Gladigau, Christian Haubelt, Jürgen Teich, Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models., FDL 2008: 1-6
Jesús Alastruey, Teresa Monreal, Francisco Cazorla, Víctor Viñals, Mateo Valero, Selection of the Register File Size and the Resource Allocation Policy on SMT Processors, SBAC-PAD '08: Proceedings of the 2008 20th International Symposium on Computer Architecture and High Performance Computing - Volume 00 , Volume 00, IEEE Computer Society, October 2008
Jesús Delicado, Francisco Delicado, Luis Orozco-Barbosa, Study of the IEEE 802.16 contention-based request mechanism., Telecommunication Systems 38(1-2): 19-27 (2008)
Jesús Delicado, Francisco Delicado, Luis Orozco-Barbosa, Request Mechanisms to Reduce the Contention Period in 802.16: A Comparison., MWCN/PWC 2008: 135-147
Jesús Escudero-Sahuquillo, Pedro García, Francisco J. Quiles, Jose Flich, José Duato, FBICM: Efficient Congestion Management for High-Performance Networks Using Distributed Deterministic Routing., HiPC 2008: 503-517
Jesus Luna, Manolis Marazakis, Marios D. Dikaiakos, Using Desktop Grids to Securely Store e-Health Data., ERCIM News 2008(74): (2008)
Jesus Luna, Michail Flouris, Manolis Marazakis, Angelos Bilas, Providing security to the Desktop Data Grid., IPDPS 2008: 1-8
Jia Guo, Ganesh Bikshandi, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Programming with tiles., PPOPP 2008: 111-122
Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda, MAPS: an integrated framework for MPSoC application parallelization., DAC 2008: 754-759
Jie Tao, Asadollah Shahbahrami, Data Locality Optimization Based on Comprehensive Knowledge of the Cache Miss Reason: A Case Study with DWT., HPCC 2008: 304-311
Jie Tao, Georges Kneip, Wolfgang Karl, Guided Prefetching Based on Runtime Access Patterns., ICCS (3) 2008: 268-275
Jie Tao, Marcel Kunze, Fabian Nowak, Rainer Buchty, Wolfgang Karl, Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems., International Journal of Parallel Programming 36(3): 347-360 (2008)
Jie Tao, Marcel Kunze, Wolfgang Karl, Evaluating the Cache Architecture of Multicore Processors., PDP 2008: 12-19
Jin Li, Jarmo Takala, Moncef Gabbouj, Hexin Chen, A detection algorithm for zero-quantized DCT coefficients in JPEG., ICASSP 2008: 1189-1192
Jin Li, Moncef Gabbouj, Jarmo Takala, Hexin Chen, Laplacian modeling of DCT coefficients for real-time encoding., ICME 2008: 797-800
Jisheng Zhao, Matthew Horsnell, Mikel Luján, Ian Rogers, Chris C. Kirkham, Ian Watson, Adaptive Loop Tiling for a Multi-cluster CMP., ICA3PP 2008: 220-232
João B. Cardoso, João R. de Almeida, José M. Dias, Pedro G. Coelho, Structural reliability analysis using Monte Carlo simulation and neural networks, Advances in Engineering Software , Volume 39 Issue 6, Elsevier Science Ltd., June 2008
Joachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya, A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications., EMSOFT 2008: 189-198
Joachim Keinert, Christian Haubelt, Jürgen Teich, Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication., ARCS 2008: 130-143
Joan-Lluís Ferrer, Elvira Baydal, Antonio Robles, Pedro López, José Duato, On the Influence of the Packet Marking and Injection Control Schemes in Congestion Management for MINs., Euro-Par 2008: 930-939
Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael De Nil, Jef L. van Meerbergen, Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP., HiPEAC 2008: 82-96
Johan A. Pouwelse, Pawel Garbacki, Dick Epema, Henk Sips, Pirates and Samaritans: A decade of measurements on peer production and their implications for net neutrality and copyright, Telecommunications Policy , Volume 32 Issue 11, Pergamon Press, Inc., December 2008
Johan A. Pouwelse, Pawel Garbacki, Jun Wang, A. Bakker, J. Yang, Alexandru Iosup, Dick H. J. Epema, Marcel J. T. Reinders, M. R. van Steen, Henk J. Sips, TRIBLER: a social-based peer-to-peer system., Concurrency and Computation: Practice and Experience 20(2): 127-138 (2008)
Johan Jeuring, Sean Leather, José Pedro Magalhães, Alexey Rodriguez Yakushev, Libraries for Generic Programming in Haskell., Advanced Functional Programming 2008: 165-229
John Cavazos, Intelligent compilers., CLUSTER 2008: 360-368
John Glossner, Daniel Iancu, Mayan Moudgill, Sanjay Jinturkar, Gary Nacer, Stuart Stanley, Andrei Iancu, Hua Ye, Michael J. Schulte, Mihai Sima, Tomas Palenik, Peter Farkas, Jarmo Takala, Implementing communications systems on an SDR SoC., ICASSP 2008: 5380-5383
Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith, Glitch-aware output switching activity from word-level statistics., ISCAS 2008: 1792-1795
Jonathan Barre, Christine Rochange, Pascal Sainrat, An architecture for the simultaneous execution of hard real-time threads., ICSAMOS 2008: 18-24
Jonathan Barre, Christine Rochange, Pascal Sainrat, A Predictable Simultaneous Multithreading Scheme for Hard Real-Time., ARCS 2008: 161-172
Jonathan Frye, Björn Franke, PDP: pen driven programming, BCS-HCI '08: Proceedings of the 22nd British CHI Group Annual Conference on HCI 2008: People and Computers XXII: Culture, Creativity, Interaction - Volume 2 , Volume 2, British Computer Society, September 2008
Jonathan J. Davies, Alastair R. Beresford, Alan Mycroft, Language-Based Optimisation of Sensor-Driven Distributed Computing Applications., FASE 2008: 407-422
Jordi Guitart, David Carrera, Vicenç Beltran, Jordi Torres, Eduard Ayguadé, Dynamic CPU provisioning for self-managed secure web applications in SMP hosting platforms., Computer Networks 52(7): 1390-1409 (2008)
Jordi Pujol Ahulló, Pedro García López, PlanetSim: an extensible framework for overlay network and services simulations, Simutools '08: Proceedings of the 1st international conference on Simulation tools and techniques for communications, networks and systems & workshops, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), March 2008
Jordi Pujol Ahulló, Pedro García López, Antonio F. Gómez Skarmeta, LightPS: Lightweight Content-Based Publish/Subscribe for Peer-to-Peer Systems, CISIS '08: Proceedings of the 2008 International Conference on Complex, Intelligent and Software Intensive Systems - Volume 00 , Volume 00, IEEE Computer Society, March 2008
Jordi Torres, David Carrera, Kevin Hogan, Ricard Gavaldà, Vicenç Beltran, Nicolas Poggi, Reducing wasted resources to help achieve green data centers., IPDPS 2008: 1-8
Jordi Torres, David Carrera, Vicenç Beltran, Nicolás Poggi, Kevin Hogan, Josep Ll. Berral, Ricard Gavaldà, Eduard Ayguadé, Toni Moreno, Jordi Guitart, Tailoring Resources: The Energy Efficient Consolidation Strategy Goes Beyond Virtualization, ICAC '08: Proceedings of the 2008 International Conference on Autonomic Computing - Volume 00 , Volume 00, IEEE Computer Society, June 2008
Jorge Ejarque, Marc de Palol, Inigo Goiri, Ferran Julià, Jordi Guitart, Jordi Torres, Rosa M. Badia, Using Semantics for Resource Allocation in Computing Service Providers., IEEE SCC (2) 2008: 583-587
Jorge Sales, Reinel Beltran, Pedro J. Sanz, Raúl Marín, Raul Wirz, German Leon, José M. Claver, Jaime Alemany, The UJI industrial robotics telelaboratory: Real-time vision and networking., IROS 2008: 4136
José L. Abellán, Juan Fernández, Manuel E. Acacio, Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades, ICCS '08: Proceedings of the 8th international conference on Computational Science, Part I, Springer-Verlag, June 2008
José L. Risco-Martín, David Atienza, J. Ignacio Hidalgo, Juan Lanchares, Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
José L. Risco-Martín, Saurabh Mittal, David Atienza, J. Ignacio Hidalgo, Juan Lanchares, Optimization of dynamic data types in embedded systems using DEVS/SOA-based modeling and simulation, InfoScale '08: Proceedings of the 3rd international conference on Scalable information systems, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), June 2008
José Daniel García, Laura Prada, Javier Fernández, Alberto Nuñez, Jesús Carretero, Using Black-Box Modeling Techniques for Modern Disk Drives Service Time Simulation., Annual Simulation Symposium 2008: 139-145
José Ignacio Aliaga, Matthias Bollhöfer, Alberto F. Martín, Enrique S. Quintana-Ortí, Design Tuning and Evaluation of Parallel Multilevel ILU Preconditioners., VECPAR 2008: 314-327
José Ignacio Hidalgo, José L. Risco-Martín, David Atienza, Juan Lanchares, Analysis of multi-objective evolutionary algorithms to optimize dynamic data types in embedded systems., GECCO 2008: 1515-1522
José L. Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares, A parallel evolutionary algorithm to optimize dynamic data types in embedded systems., Soft Comput. 12(12): 1157-1167 (2008)
José Luis Martínez, Christopher Holder, Gerardo Fernández-Escribano, Hari Kalva, Francisco José Quiles Flor, DVC using a half-feedback based approach., ICME 2008: 1125-1128
José Miguel Montañana, Jose Flich, José Duato, Epoch-based reconfiguration: Fast simple and effective dynamic network reconfiguration., IPDPS 2008: 1-12
José Miguel-Alonso, Cruz Izu, José-Ángel Gregorio, Improving the performance of large interconnection networks using congestion-control mechanisms., Perform. Eval. 65(3-4): 203-211 (2008)
José Villalón, Pedro Cuenca, Luis Orozco-Barbosa, Efficient Joint Unicast/Multicast Transmission over IEEE 802.11e WLANs., MWCN/PWC 2008: 109-121
José Villalón, Pedro Cuenca, Luis Orozco-Barbosa, Antonio Garrido, B-EDCA: A QoS mechanism for multimedia communications over heterogeneous 802.11/802.11e WLANs., Computer Communications 31(17): 3905-3921 (2008)
Jose Flich, Jose Duato, Logic-Based Distributed Routing for NoCs, IEEE Computer Architecture Letters , Volume 7 Issue 1, IEEE Computer Society, January 2008
Jose Flich, Samuel Rodrigo, José Duato, An Efficient Implementation of Distributed Routing Algorithms for NoCs., NOCS 2008: 87-96
Jose Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne, On the Potential of NoC Virtualization for Multicore Chips., CISIS 2008: 801-807
Jose L. Abellan, Juan Fernandez, Manuel E. Acacio, CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE, PDP '08: Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008) - Volume 00 , Volume 00, IEEE Computer Society, February 2008
Josef Angermeier, Jürgen Teich, Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads., IPDPS 2008: 1-8
Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, T. Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, E. Lubbers, Marco Platzner, Christopher Claus, Walter Stechele, Andre, Fine grain reconfigurable architectures., FPL 2008: 348
Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele, Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System., ARC 2008: 148-158
Josep Aguilar-Saborit, Pedro Trancoso, Victor Muntés-Mulero, Josep-Lluis Larriba-Pey, Dynamic adaptive data structures for monitoring data streams., Data Knowl. Eng. 66(1): 92-115 (2008)
Josep M. Pérez, Rosa M. Badia, Jesús Labarta, A dependency-aware task-based programming environment for multi-core architectures., CLUSTER 2008: 142-151
Juan Antonio Castillo, Antonio Manuel Ortiz, Vicente López, Teresa Olivares, Luis Orozco-Barbosa, WiseObserver: a real experience with wireless sensor networks., PM2HW2N 2008: 23-26
Juan Carlos Pichel, David E. Singh, Jesús Carretero, Reordering Algorithms for Increasing Locality on Multicore Processors., HPCC 2008: 123-130
Juan Echagüe, Jesús E. Villadangos, Vicent Cholvi, Manuel Prieto, Transforming general networks into feed-forward by using turn-prohibition., Computer Communications 31(9): 1824-1831 (2008)
Juan Fernández, Manuel E. Acacio, Gregorio Bernabé, José L. Abellán, Joaquín Franco, Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla., CSC 2008: 167-173
Juan Hamers, Lieven Eeckhout, Automated hardware-independent scenario identification., DAC 2008: 954-959
Juan L. Aragón, Alexander V. Veidenbaum, Optimizing CAM-based instruction cache designs for low-power embedded systems., Journal of Systems Architecture - Embedded Systems Design 54(12): 1155-1163 (2008)
Jude Angelo Ambrose, Naeill Aldon, Aleksandar Ignjatovic, Sri Parameswaran, Anatomy of Differential Power Analysis for AES., SYNASC 2008: 459-466
Jude Angelo Ambrose, Sri Parameswaran, Aleksandar Ignjatovic, MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm., ICCAD 2008: 678-684
Juho Antikainen, Perttu Salmela, Olli Silvén, Markku J. Juntti, Jarmo Takala, Markus Myllylä, Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm., ICSAMOS 2008: 108-115
Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen, Embedded Software Architecture for Diagnosing Network and Node Failures in Wireless Sensor Networks., SAMOS 2008: 258-267
Julien Taillard, Frédéric Guyomarc'h, Jean-Luc Dekeyser, A Graphical Framework for High Performance Computing Using An MDE Approach., PDP 2008: 165-173
Jun Qin, Thomas Fahringer, A novel domain oriented approach for scientific grid workflow composition., SC 2008: 21
Justin Ferris, Mike Surridge, E. Rowland Watkins, Thomas Fahringer, Radu Prodan, Frank Glinka, Sergei Gorlatch, Christoph Anthes, Alexis Arragon, Christopher J. Rawlings, Arton Lipaj, Edutain@Grid: A Business Grid Infrastructure for Real-Time On-Line Interactive Applications., GECON 2008: 152-162
Justin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole, Combating process variation on FPGAS with a precise at-speed delay measurement method., FPL 2008: 703-704
K. E. Moselund, D. Bouvet, M. H. Ben Jamaa, D. Atienza, Y. Leblebici, G. De Micheli, A. M. Ionescu, Prospects for logic-on-a-wire, Microelectronic Engineering , Volume 85 Issue 5-6, Elsevier Science Ltd., May 2008
Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao Lu, Xiaoxiang Shi, Wayne Luk, Reconfigurable acceleration of microphone array algorithms for speech enhancement., ASAP 2008: 203-208
Ka-Fai Cedric Yiu, Yao Lu, Xiaoxiang Shi, Wayne Luk, FPGA Acceleration of a Subband Beamforming Algorithm for Speech Enhancement, CISP '08: Proceedings of the 2008 Congress on Image and Signal Processing, Vol. 5 - Volume 05 , Volume 05, IEEE Computer Society, May 2008
Kalle Holma, Mikko Setälä, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Evaluating the model accuracy in automated design space exploration., Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 321-329 (2008)
Kamana Sigdel, Mark Thompson, Andy D. Pimentel, Todor Stefanov, Koen Bertels, System-Level Design Space Exploration of Dynamic Reconfigurable Architectures., SAMOS 2008: 279-288
Karel Bruneel, Dirk Stroobandt, Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs, RECONFIG '08: Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs - Volume 00 , Volume 00, IEEE Computer Society, December 2008
Karel Bruneel, Dirk Stroobandt, Automatic generation of run-time parameterizable configurations., FPL 2008: 361-366
Karine Deschinkel, Sid Ahmed Ali Touati, Efficient Method for Periodic Task Scheduling with Storage Requirement Minimization., COCOA 2008: 438-447
Karthik Baddam, Mark Zwolinski, Divided Backend Duplication Methodology for Balanced Dual Rail Routing., CHES 2008: 396-410
Katerina Doka, Athanasia Asiki, Dimitrios Tsoumakos, Nectarios Koziris, Online Querying of Concept Hierarchies in P2P Systems., OTM Conferences (1) 2008: 212-230
Katerina Doka, Dimitrios Tsoumakos, Nectarios Koziris, HiPPIS: an online P2P system for efficient lookups on d-dimensional hierarchies., WIDM 2008: 63-70
Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah, Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects., NOCS 2008: 45-54
Kenneth Hoste, Lieven Eeckhout, Characterizing the Unique and Diverse Behaviors in Existing and Emerging General-Purpose and Domain-Specific Benchmark Suites., ISPASS 2008: 157-168
Kenneth Hoste, Lieven Eeckhout, Cole: compiler optimization level exploration., CGO 2008: 165-174
Kenzo Craeynest, Stijn Eyerman, Lieven Eeckhout, MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Kevin Lee, Norman W. Paton, Rizos Sakellariou, Ewa Deelman, Alvaro A. A. Fernandes, Gaurang Mehta, Adaptive Workflow Processing and Execution in Pegasus., GPC Workshops 2008: 99-106
Kevin Williams, Albert Noll, Andreas Gal, David Gregg, Optimization strategies for a java virtual machine interpreter on the cell broadband engine., Conf. Computing Frontiers 2008: 189-198
Kevin Williams, Samir Chatterjee, Matti Rossi, Design of emerging digital services: a taxonomy., EJIS 17(5): 505-517 (2008)
Kfir Karmon, Liran Liss, Assaf Schuster, GWiQ-P: an efficient decentralized grid-wide quota enforcement protocol., Operating Systems Review 42(1): 111-118 (2008)
Khaled Z. Ibrahim, François Bodin, Implementing Wilson-Dirac operator on the cell broadband engine., ICS 2008: 4-14
Khaled Z. Ibrahim, François Bodin, Olivier Pène, Fine-grained parallelization of lattice QCD kernel routine on GPUs., J. Parallel Distrib. Comput. 68(10): 1350-1359 (2008)
Kiamal Z. Pekmestzi, Nicholas Axelos, Isidoros Sideris, Nikos K. Moshopoulos, A BISR Architecture for Embedded Memories., IOLTS 2008: 149-154
Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung, Outer Loop Pipelining for Application Specific Datapaths in FPGAs., IEEE Trans. VLSI Syst. 16(10): 1268-1280 (2008)
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid, A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors., IEEE Trans. VLSI Syst. 16(10): 1281-1294 (2008)
Koen De Bosschere, Upcoming Computing System Challenges - The HiPEAC Vision (Anstehende Herausforderungen der Computer Industrie - Die HiPEAC Vision)., it - Information Technology 50(5): 285-292 (2008)
Koen De Bosschere, Memory footprint reduction for embedded systems., SCOPES 2008: 31
Koen De Bosschere, Ayal Zaks, Michael C. Huang, Luis Piñuel, Topic 4: High Performance Architectures and Compilers., Euro-Par 2008: 315-316
Konstantinos Kakousis, Nearchos Paspallis, George A. Papadopoulos, Optimizing the Utility Function-Based Self-adaptive Behavior of Context-Aware Systems Using User Feedback, OTM '08: Proceedings of the OTM 2008 Confederated International Conferences, CoopIS, DOA, GADA, IS, and ODBASE 2008. Part I on On the Move to Meaningful Internet Systems:, Springer-Verlag, November 2008
Konstantinos Tatas, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Stephan Wong, Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs., Parallel Processing Letters 18(2): 291-306 (2008)
Kornilios Kourtis, Georgios I. Goumas, Nectarios Koziris, Optimizing sparse matrix-vector multiplication using index and value compression., Conf. Computing Frontiers 2008: 87-96
Kostas Papadopoulos, Kyriakos Stavrou, Pedro Trancoso, HelperCoreDB: Exploiting multicore technology to improve database performance., IPDPS 2008: 1-11
Kostas Siozios, Dimitrios Soudris, An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs., PATMOS 2008: 439-448
Kostas Siozios, Dimitrios Soudris, A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs., J. Low Power Electronics 4(3): 275-289 (2008)
Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis, Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays., J. Low Power Electronics 4(1): 34-47 (2008)
Krisztián Flautner, The Wall Ahead is Made of Rubber., DDECS 2008: 2
Krisztián Flautner, John Regehr, Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages Compilers and Tools for Embedded Systems (LCTES'08) Tucson AZ USA June 12-13 2008, ACM 2008
Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk, CHIPS: Custom Hardware Instruction Processor Synthesis., IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 528-541 (2008)
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar, Fast custom instruction identification by convex subgraph enumeration., ASAP 2008: 1-6
Kyle J. Nesbit, Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo Valero, James E. Smith, Multicore Resource Management, IEEE Micro , Volume 28 Issue 3, IEEE Computer Society Press, May 2008
Kyriakos Stavrou, Marios Nikolaides, Demos Pavlou, Samer Arandi, Paraskevas Evripidou, Pedro Trancoso, TFlux: A Portable Platform for Data-Driven Multithreading on Commodity Multicore Systems., ICPP 2008: 25-34
Kyrre Glette, Jim Torresen, Paul Kaufmann, Marco Platzner, A Comparison of Evolvable Hardware Architectures for Classification Tasks., ICES 2008: 22-33
Kyrre Glette, Thiemo Gruber, Paul Kaufmann, Jim Torresen, Bernhard Sick, Marco Platzner, Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control, AHS '08: Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems - Volume 00 , Volume 00, IEEE Computer Society, June 2008
Lazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris, Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms., Journal of Systems Architecture - Embedded Systems Design 54(11): 1030-1038 (2008)
Leandro Fiorin, Gianluca Palermo, Cristina Silvano, A security monitoring service for NoCs., CODES+ISSS 2008: 197-202
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Valerio Catalano, Cristina Silvano, Secure Memory Accesses on Networks-on-Chip, IEEE Transactions on Computers , Volume 57 Issue 9, IEEE Computer Society, September 2008
Leandro Fiorin, Slobodan Lukovic, Gianluca Palermo, Implementation of a reconfigurable data protection module for NoC-based MPSoCs., IPDPS 2008: 1-8
Lee W. Howes, Anton Lokhmotov, Alastair F. Donaldson, Paul H. Kelly, Deriving Efficient Data Movement from Decoupled Access/Execute Specifications, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Lei Gao, Chao Li, Ting Fang, Zhang Xiong, Vehicle Detection Based on Color and Edge Information., ICIAR 2008: 142-150
Lei Gao, Chao Li, Yi Guo, Zhang Xiong, Automatic Learning of Semantic Region Models for Event Recognition., ISDA (2) 2008: 40-44
Lei Gao, Guangzhou Zeng, Dynamic Testing Algorithm Based on Rough Sets for Multiple Fault Diagnosis., FSKD (3) 2008: 157-163
Lei Gao, Guangzhou Zeng, S^2AN-WBN: An Innovative Hybrid P2P Location Network., ISCSCT (1) 2008: 529-535
Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Multiprocessor performance estimation using hybrid simulation., DAC 2008: 325-330
Lei Gao, Ming-che Lai, Zhenghu Gong, Exploiting the Thread-Level Parallelism for BGP on Multi-core., CNSR 2008: 510-516
Lei Gao, Zhenghu Gong, Yaping Liu, Ming-che Lai, Wei Peng, A TLP approach for BGP based on local speculation., Science in China Series F: Information Sciences 51(11): 1772-1784 (2008)
Leif Uhsadel, Andy Georges, Ingrid Verbauwhede, Exploiting Hardware Performance Counters, FDTC '08: Proceedings of the 2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography - Volume 00 , Volume 00, IEEE Computer Society, August 2008
Li Su, Howard Bowman, Philip Barnard, Performance of Reactive Interfaces in Stimulus Rich Environments Applying Formal Methods and Cognitive Frameworks., Electr. Notes Theor. Comput. Sci. 208: 95-111 (2008)
Lieven Eeckhout, Sampled Processor Simulation- A Survey., Advances in Computers 72: 173-224 (2008)
Liliana Cucu, Nicolas Pernet, Yves Sorel, Periodic real-time scheduling: from deadline-based model to latency-based model., Annals OR 159(1): 41-51 (2008)
Lionel Lacassagne, Antoine Manzanera, Julien Denoulet, Alain Merigot, High Performance Motion Detection: Some trends toward new embedded architectures for vision systems, Journal of Real-Time Image Processing
Lizhe Wang, Emeric Kwemou, Jie Tao, Marcel Kunze, David Kramer, Wolfgang Karl, On-Demand Build a Virtual e-Science Workflow, GPC-WORKSHOPS '08: Proceedings of the 2008 The 3rd International Conference on Grid and Pervasive Computing - Workshops - Volume 00 , Volume 00, IEEE Computer Society, May 2008
Lizhe Wang, Jie Tao, Marcel Kunze, Alvaro Canales Castellanos, David Kramer, Wolfgang Karl, Scientific Cloud Computing: Early Definition and Experience., HPCC 2008: 825-830
Lorenzo Leonini, Etienne Riviere, Pascal Felber, P2P Experimentations with Splay: From Idea to Deployment Results in 30 min., Peer-to-Peer Computing 2008: 189-190
Lotfi Mhamdi, A Partially Buffered Crossbar packet switching architecture and its scheduling., ISCC 2008: 942-948
Louis-Noël Pouchet, Cédric Bastoul, Albert Cohen, John Cavazos, Iterative optimization in the polyhedral model: part ii multidimensional time., PLDI 2008: 90-100
Luca Benini, Davide Bertozzi, Michela Milano, Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming., ICLP 2008: 470-484
Luca Benini, Michele Lombardi, Marco Mantovani, Michela Milano, Martino Ruggiero, Multi-stage Benders Decomposition for Optimizing Multicore Architectures., CPAIOR 2008: 36-50
Luca Benini, Michele Lombardi, Michela Milano, Martino Ruggiero, A Constraint Programming Approach for Allocation and Scheduling on the CELL Broadband Engine., CP 2008: 21-35
Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi, A simplified executable model to evaluate latency and throughput of networks-on-chip., SBCCI 2008: 170-175
Luigi Palopoli, Luca Abeni, Tommaso Cucinotta, Giuseppe Lipari, Sanjoy K. Baruah, Weighted feedback reclaiming for multimedia applications., ESTImedia 2008: 121-126
Luis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu, An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator, NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008) - Volume 00 , Volume 00, IEEE Computer Society, April 2008
Luis F. Romero, Siham Tabik, Jesús M. Vías, Emilio L. Zapata, Fast clear-sky solar irradiation computation for very large digital elevation models., Computer Physics Communications 178(11): 800-808 (2008)
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals, Low-Cost Adaptive Data Prefetching, Euro-Par '08: Proceedings of the 14th international Euro-Par conference on Parallel Processing, Springer-Verlag, August 2008
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals, Low-Cost Adaptive Data Prefetching., Euro-Par 2008: 327-336
Luk Van Ertvelde, Filip Hellebaut, Lieven Eeckhout, Accurate and Efficient Cache Warmup for Sampled Processor Simulation Through NSL-BLRL., Comput. J. 51(2): 192-206 (2008)
Luk Van Ertvelde, Lieven Eeckhout, Dispersing proprietary applications as benchmarks through code mutation., ASPLOS 2008: 201-210
Lukas Kuhn, Bob Price, Johan De Kleer, Minh Do, Rong Zhou, Pervasive diagnosis: the integration of diagnostic goals into production plans, AAAI'08: Proceedings of the 23rd national conference on Artificial intelligence - Volume 3 , Volume 3, AAAI Press, July 2008
Mónica Denham, Ana Cortés, Tomàs Margalef, Emilio Luque, Applying a Dynamic Data Driven Genetic Algorithm to Improve Forest Fire Spread Prediction., ICCS (3) 2008: 36-45
M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli, Programmable logic circuits based on ambipolar CNFET., DAC 2008: 339-340
M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli, Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories., IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2053-2067 (2008)
M. M. Waliullah, Per Stenström, Intermediate checkpointing with conflicting access prediction in transactional memory systems., IPDPS 2008: 1-11
M. M. Waliullah, Per Stenström, Efficient management of speculative data in hardware transactional memory systems., ICSAMOS 2008: 158-164
M. Mustafa Rafique, Ali Raza Butt, Dimitrios S. Nikolopoulos, DMA-based prefetching for i/o-intensive workloads on the cell architecture., Conf. Computing Frontiers 2008: 23-32
Mafijul Md. Islam, Per Stenstrom, Zero loads: canceling load requests by tracking zero values, MEDEA '08: Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, October 2008
Magnus Själander, Andrei Terechko, Marc Duranton, A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Mahmood Ahmadi, Stephan Wong, An Approach for Optimal Bandwidth Allocation in Packet Processing Systems., CNSR 2008: 208-214
Mahmood Ahmadi, Stephan Wong, A Paradigm for Reconfigurable Processing on Grid., GridNets 2008: 259-262
Mahmood Ahmadi, Stephan Wong, A Memory-Optimized Bloom Filter Using an Additional Hashing Function., GLOBECOM 2008: 2479-2483
Mahmut T. Kandemir, Ozcan Ozturk, Software-directed combined cpu/link voltage scaling fornoc-based cmps., SIGMETRICS 2008: 359-370
Manolis Katevenis, Towards unified mechanisms for inter-processor communication., ICSAMOS 2008
Manuel Arenaz, Juan Touriño, Ramon Doallo, XARK: An extensible framework for automatic recognition of computational kernels., ACM Trans. Program. Lang. Syst. 30(6): (2008)
Manuel Arenaz, Pedro Amoedo, Juan Touriño, Efficiently Building the Gated Single Assignment Form in Codes with Pointers in Modern Optimizing Compilers., Euro-Par 2008: 360-369
Manuel E. Prieto, Víctor H. Menéndez, Alejandra A. Segura, Christian L. Vidal, A Recommender System Architecture for Instructional Engineering, WSKS '08: Proceedings of the 1st world summit on The Knowledge Society: Emerging Technologies and Information Systems for the Knowledge Society, Springer-Verlag, September 2008
Manuel Hohenauer, F. Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh, Retargetable Code Optimization for Predicated Execution., DATE 2008: 1492-1497
Manuel Nickschas, Uwe Brinkschulte, Guiding Organic Management in a Service-Oriented Real-Time Middleware Architecture., SEUS 2008: 90-101
Manuel V. Hermenegildo, Francisco Bueno, Manuel Carro, Pedro López, José F. Morales, Germán Puebla, An Overview of the Ciao Multiparadigm Language and Program Development Environment and Its Design Philosophy., Concurrency Graphs and Models 2008: 209-237
Marc Casas, Rosa M. Badia, Jesús Labarta, Automatic analysis of speedup of MPI applications., ICS 2008: 349-358
Marc Casas, Rosa M. Badia, Jesús Labarta, Prediction of behavior of MPI applications., CLUSTER 2008: 242-251
Marc González, Nikola Vujic, Xavier Martorell, Eduard Ayguadé, Alexandre E. Eichenberger, Tong Chen, Zehra Sura, Tao Zhang, Kevin O'Brien, Kathryn M. O'Brien, Hybrid access-specific software cache techniques for the cell BE architecture., PACT 2008: 292-302
Marcel Arrufat, Gerard París, Pedro García López, AGORA: an integrated approach for collaboration in MANETs, MOBILWARE '08: Proceedings of the 1st international conference on MOBILe Wireless MiddleWARE, Operating Systems, and Applications, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), February 2008
Marcela Zuluaga, Nigel P. Topham, Resource Sharing in Custom Instruction Set Extensions., SASP 2008: 7-13
Marcelo Cintra, An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs, IEEE
Marco Aldinucci, Anne Benoit, Automatic Mapping of Assist Applications Using Process Algebra., Parallel Processing Letters 18(1): 175-188 (2008)
Marco Aldinucci, Marco Danelutto, Securing skeletal systems with limited performance penalty: The muskel., Journal of Systems Architecture - Embedded Systems Design 54(9): 868-876 (2008)
Marco Aldinucci, Marco Danelutto, Peter Kilpatrick, Semi-formal Models to Support Program Development: Autonomic Management within Component Based Parallel and Distributed Programming., FMCO 2008: 204-225
Marco Aldinucci, Marco Danelutto, Peter Kilpatrick, Co-design of Distributed Systems Using Skeleton and Autonomic Management Abstractions., Euro-Par Workshops 2008: 403-414
Marco Aldinucci, Massimo Torquati, Marco Vanneschi, Pierfrancesco Zuccato, The VirtuaLinux Storage Abstraction Layer for Ef?cient Virtual Clustering., PDP 2008: 619-627
Marco Aldinucci, Sonia Campa, Marco Danelutto, Marco Vanneschi, Peter Kilpatrick, Patrizio Dazzi, Domenico Laforenza, Nicola Tonellotto, Behavioural Skeletons in GCM: Autonomic Management of Grid Components., PDP 2008: 54-63
Marco Cornero, Roberto Costa, Ricardo Fernández Pascual, Andrea C. Ornstein, Erven Rohou, An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems., HiPEAC 2008: 130-144
Marco D. Santambrogio, Donatella Sciuto, Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign., IPDPS 2008: 1-8
Marco D. Santambrogio, Vincenzo Rana, Donatella Sciuto, Operating system support for online partial dynamic reconfiguration management., FPL 2008: 455-458
Marco Danelutto, Juan Touriño, Mark Baker, Rajkumar Buyya, Paraskevi Fragopoulou, Christian Perez, Erich Schikuta, Topic 6: Grid and Cluster Computing., Euro-Par 2008: 444
Marco Platzner, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz, Tobias Schumacher, Andre Send, Alexander Warkentin, The GOmputer: Accelerating GO with FPGAs., ERSA 2008: 35-45
Marek Wieczorek, Stefan Podlipnig, Radu Prodan, Thomas Fahringer, Bi-criteria Scheduling of Scientific Workflows for the Grid., CCGRID 2008: 9-16
Margarita Amor, Montserrat Bóo, A new architecture for efficient hybrid representation of terrains., Journal of Systems Architecture - Embedded Systems Design 54(1-2): 145-160 (2008)
Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, Video enhancement on an adaptive image sensor., ICIP 2008: 681-684
Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides, FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor., ARC 2008: 124-135
Maria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos, Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs., Signal Processing Systems 51(1): 3-21 (2008)
Marianne de Michiel, Armelle Bonenfant, Hugues Cassé, Pascal Sainrat, Static Loop Bound Analysis of C Programs Based on Flow Analysis and Abstract Interpretation, RTCSA '08: Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications - Volume 00 , Volume 00, IEEE Computer Society, August 2008
Marina Biberstein, Uzi Shvadron, J. Turek, Bilha Mendelson, Moon S. Chang, Trace-based Performance Analysis on Cell BE., ISPASS 2008: 213-222
Marina Biberstein, Yuval Harel, Andre Heilper, Clock Synchronization in Cell BE Traces., Euro-Par 2008: 3-12
Mario Leandro Bertogna, Eduardo Grosclaude, Marcelo R. Naiouf, Armando De Giusti, Emilio Luque, Dynamic on Demand Virtual Clusters in Grid., Euro-Par Workshops 2008: 13-22
Marios Kleanthous, Yiannakis Sazeides, CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches., DATE 2008: 1426-1431
Marios Papas, Josep-Lluis Larriba-Pey, Pedro Trancoso, Categorized Sliding Window in Streaming Data Management Systems., DEXA 2008: 625-634
Marios Tziakouris, Paraskevas Evripidou, HTTPStream Platform - Low Latency Data for the Web., OTM Workshops 2008: 873-882
Marius Grannæs, Magnus Jahre, Lasse Natvig, Low-cost open-page prefetch scheduling in chip multiprocessors., ICCD 2008: 390-396
Mark Shifrin, Isaac Keslassy, Modeling TCP in Small-Buffer Networks., Networking 2008: 667-678
Mark Silberstein, Assaf Schuster, Dan Geiger, Anjul Patney, John D. Owens, Efficient computation of sum-products on GPUs through software-managed cache., ICS 2008: 309-318
Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid, Mladen Wilder, Krisztián Flautner, From SODA to scotch: The evolution of a wireless baseband processor., MICRO 2008: 152-163
Markus Koester, Wayne Luk, Geoffrey Brown, A hardware compilation flow for instance-specific VLIW cores., FPL 2008: 619-622
Martín Abadi, Andrew Birrell, Tim Harris, Michael Isard, Semantics of transactional memory and automatic mutual exclusion., POPL 2008: 63-74
Martín Abadi, Tim Harris, Katherine F. Moore, A Model of Dynamic Separation for Transactional Memory., CONCUR 2008: 6-20
Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, A feasibility-preserving local search operator for constrained discrete optimization problems., IEEE Congress on Evolutionary Computation 2008: 1968-1975
Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Efficient symbolic multi-objective design space exploration., ASP-DAC 2008: 691-696
Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Richard Regler, Bardo Lang, Concurrent topology and routing optimization in automotive network integration., DAC 2008: 626-629
Martin Lukasiewycz, Michael Glaß, Jürgen Teich, A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems., PPSN 2008: 919-928
Martin Schindewolf, Jie Tao, Wolfgang Karl, Marcelo Cintra, A Generic Tool Supporting Cache Designs and Optimisation on Shared Memory Systems., PASA 2008: 69-
Martin Thuresson, Lawrence Spracklen, Per Stenström, Memory-Link Compression Schemes: A Value Locality Perspective., IEEE Trans. Computers 57(7): 916-927 (2008)
Martin Thuresson, Magnus Själander, Per Stenstrom, A Flexible Code Compression Scheme Using Partitioned Look-Up Tables, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Martin Thuresson, Per Stenström, Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression., ICPP 2008: 478-486
Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Michela Milano, Luca Benini, A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness., International Journal of Parallel Programming 36(1): 3-36 (2008)
Martino Ruggiero, Andrea Bartolini, Luca Benini, DBS4video: dynamic luminance backlight scaling based on multi-histogram frame characterization for video streaming application., EMSOFT 2008: 109-118
Martino Ruggiero, Michele Lombardi, Michela Milano, Luca Benini, Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE Processor, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Martino Sykora, Giovanni Agosta, Cristina Silvano, Dynamic configuration of application-specific implicit instructions for embedded pipelined processors., SAC 2008: 1509-1516
Massimiliano Melani, Lorenzo Bertini, Marco De Marinis, Peter Lange, Francesco D'Ascoli, Luca Fanucci, Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring., DATE 2008: 342-347
Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto, Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture., ISVLSI 2008: 286-291
Massimo Rovini, Fabio Principe, Luca Fanucci, Marco Luise, Implementation of message-passing algorithms for the acquisition of spreading codes., ICASSP 2008: 1441-1444
Mateo Valero, Jesús Labarta, Supercomputing for the Future Supercomputing from the Past (Keynote)., HiPEAC 2008: 3-5
Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jürgen Teich, Co-design Architecture and Implementation for Point-Based Rendering on FPGAs., IEEE International Workshop on Rapid System Prototyping 2008: 142-148
Mathias Funk, Piet van der Putten, Henk Corporaal, UML Profile for Modeling Product Observation., FDL 2008: 185-190
Mathias Funk, Piet van der Putten, Henk Corporaal, Model Interpretation for Executable Observation Specifications., SEKE 2008: 785-790
Mathias Funk, Piet van der Putten, Henk Corporaal, Specification for User Modeling with Self-Observing Systems., ACHI 2008: 243-248
Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa, A Modular Approach to Model Heterogeneous MPSoC at Cycle Level, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Matthew Curtis-Maury, Ankur Shah, Filip Blagojevic, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz, Prediction models for multi-dimensional power-performance optimization on many cores., PACT 2008: 250-259
Matthew Curtis-Maury, Filip Blagojevic, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Prediction-Based Power-Performance Adaptation of Multithreaded Scientific Codes, IEEE Transactions on Parallel and Distributed Systems , Volume 19 Issue 10, IEEE Press, October 2008
Matthew Sheehan, Ian Watson, On the Usefulness of Interactive Computer Game Logs for Agent Modelling., PRICAI 2008: 1059-1064
Matthias Hauswirth, Dmitrijs Zaparanuks, Amirhossein Malekpour, Mostafa Keikha, The JavaFest: a collaborative learning technique for Java programming courses., PPPJ 2008: 3-12
Matthias May, Matthias Alles, Norbert Wehn, A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder., DATE 2008: 456-461
Matthias Woehrle, Christian Plessl, Roman Lim, Jan Beutel, Lothar Thiele, EvAnT: Analysis and Checking of Event Traces for Wireless Sensor Networks., SUTC 2008: 201-208
Mauri Kuorilehto, Marko Hännikäinen, Timo D. Hämäläinen, Rapid design and evaluation framework for wireless sensor networks., Ad Hoc Networks 6(6): 909-935 (2008)
Mauricio Alvarez, Neil D. Lawrence, Sparse Convolved Gaussian Processes for Multi-output Regression., NIPS 2008: 57-64
Maurizio Palesi, Giuseppe Longo, Salvatore Signorino, Rickard Holsmark, Shashi Kumar, Vincenzo Catania, Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms., NOCS 2008: 97-106
Maurizio Skerlj, Paolo Ienne, Error Protected Data Bus Inversion Using Standard DRAM Components., ISQED 2008: 35-42
Md. Mafijul Islam, Magnus Själander, Per Stenström, Early detection and bypassing of trivial operations to improve energy efficiency of processors., Microprocessors and Microsystems - Embedded Hardware Design 32(4): 183-196 (2008)
Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar, Multi-granularity sampling for simulating concurrent heterogeneous applications., CASES 2008: 217-226
Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang, The potential of computation reuse in high-level optimization of a signal recognition system., IPDPS 2008: 1-5
Michael Dalton, Hari Kannan, Christos Kozyrakis, Real-World Buffer Overflow Protection for Userspace and Kernelspace., USENIX Security Symposium 2008: 395-410
Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos, Temporal instruction fetch streaming., MICRO 2008: 1-10
Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich, Symbolic Reliability Analysis of Self-healing Networked Embedded Systems., SAFECOMP 2008: 139-152
Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich, Symbolic Reliability Analysis and Optimization of ECU Networks., DATE 2008: 158-163
Michael Glaß, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich, Multi-objective routing and topology optimization in networked embedded systems., ICSAMOS 2008: 74-81
Michael J. Wirthlin, Daniel S. Poznanovic, P. Sundararajan, Alan J. Coppola, D. Pellerin, Walid A. Najjar, R. Bruce, M. Babst, O. Pritchard, Paolo Palazzari, Georgi Kuzmanov, OpenFPGA CoreLib core library interoperability effort., Parallel Computing 34(4-5): 231-244 (2008)
Michael Koch, Zoran Zivkovic, Richard P. Kleihorst, Henk Corporaal, Distributed Smart Camera Calibration Using Blinking LED., ACIVS 2008: 242-253
Michael Smit, Andrew Nisbet, Eleni Stroulia, Andrew Edgar, Gabriel Iszlai, Marin Litoiu, Capacity planning for service-oriented architectures., CASCON 2008: 11
Michail Flouris, Renaud Lachaize, Angelos Bilas, Orchestra: Extensible Block-Level Support for Resource and Data Sharing in Networked Storage Systems., ICPADS 2008: 237-244
Michalis Polychronakis, Kostas G. Anagnostakis, Evangelos P. Markatos, Real-world polymorphic attack detection using network-level emulation, CSIIRW '08: Proceedings of the 4th annual workshop on Cyber security and information intelligence research: developing strategies to meet the cyber security and information intelligence challenges ahead, ACM, May 2008
Michel Meulpolder, Dick H. J. Epema, Henk J. Sips, Replication in bandwidth-symmetric BitTorrent networks., IPDPS 2008: 1-8
Michele Magno, Davide Brunelli, Piero Zappi, Luca Benini, A Solar-powered Video Sensor Node for Energy Efficient Multimodal Surveillance, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, IEEE Computer Society, September 2008
Michele Paselli, Frederik Petré, Olivier Rousseaux, Guy Meynants, Bert Gyselinckx, Marc Engels, Luca Benini, A High-Performance Wireless Sensor Node for Industrial Control Applications., ICONS 2008: 235-240
Mikael Collin, Mats Brorsson, Improving code density of embedded software using a 2-level dictionary code compression architecture, Proceedings of 13th Asia-Pacific Computer Systems Architecture Conference, 2008. ACSAC 2008.
Mikko Kohvakka, Jukka Suhonen, Mauri Kuorilehto, Marko Hännikäinen, Timo D. Hämäläinen, Network Signaling Channel for Improving ZigBee Performance in Dynamic Cluster-Tree Networks., EURASIP J. Wireless Comm. and Networking 2008: (2008)
Milan Jovic, Matthias Hauswirth, Measuring the performance of interactive applications with listener latency profiling., PPPJ 2008: 137-146
Milos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Nebelung: Execution Environment for Transactional OpenMP., International Journal of Parallel Programming 36(3): 326-346 (2008)
Min Cheol Park, Moon Kyu Kwak, Hye Sung Cho, Kahp Y. Suh, Jae Young Hur, Sang-Hyun Park, Yeast on a Chip - Single-cell Analyses of MAPK Signaling Pathways in Saccharomyces Cerevisiae using Cell Chips., BIODEVICES (2) 2008: 268-271
Ming-che Lai, Lei Gao, Wei Shi, Zhiying Wang, Escaping from Blocking: A Dynamic Virtual Channel for Pipelined Routers., CISIS 2008: 795-800
Ming-che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai, A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers., DAC 2008: 630-633
Minh B. Do, Wheeler Ruml, Rong Zhou, On-line planning and scheduling: an application to controlling modular printers, AAAI'08: Proceedings of the 23rd national conference on Artificial intelligence - Volume 3 , Volume 3, AAAI Press, July 2008
Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, MLP-Aware Dynamic Cache Partitioning., HiPEAC 2008: 337-352
Miquel Pericàs, Adrian Cristal, Francisco J. Cazorla, Ruben González, Alex Veidenbaum, Daniel A. Jiménez, Mateo Valero, A Two-Level Load/Store Queue Based on Execution Locality, ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, ACM, June 2008
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero, Power-efficient VLIW design using clustering and widening., IJES 3(3): 141-149 (2008)
Miquel Pericàs, Ricardo Chaves, Georgi Gaydadjiev, Stamatis Vassiliadis, Mateo Valero, Vectorized AES Core for High-throughput Secure Environments., VECPAR 2008: 83-94
Miron Abramovici, Kees Goossens, Bart Vermeulen, Jack Greenbaum, Neal Stollon, Adam Donlin, You can catch more bugs with transaction level honey., CODES+ISSS 2008: 121-124
Mladen Berekovic, Andy D. Pimentel, Timo D. Hämäläinen, Editorial., Journal of Systems Architecture - Embedded Systems Design 54(11): 1017-1018 (2008)
Mladen Berekovic, Christian Hochberger, Andreas Koch, Rekonfigurierbare Architekturen., Informatik Spektrum 31(4): 344-347 (2008)
Mladen Berekovic, Frank Bouwens, Tom Vander Aa, Diederik Verkest, Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor., PATMOS 2008: 449-457
Mladen Berekovic, Mladen Berekovic, Tim Niggemeier, A Distributed Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance., Signal Processing Systems 50(2): 201-229 (2008)
Mladen Berekovic, Nikitas J. Dimopoulos, Stephan Wong, Embedded Computer Systems: Architectures Modeling and Simulation 8th International Workshop SAMOS 2008 Samos Greece July 21-24 2008. Proceedings, Springer 2008
Mladen Nikitovic, Thomas de Schampeleire, Mats Brorsson, A study on periodic shutdown for adaptive CMPs in handheld devices, Proceedings of 13th Asia-Pacific Computer Systems Architecture Conference, 2008. ACSAC 2008.
Mohammad Ansari, Christos Kotselidis, Ian Watson, Chris C. Kirkham, Mikel Luján, Kim Jarvis, Lee-TM: A Non-trivial Benchmark Suite for Transactional Memory., ICA3PP 2008: 196-207
Mohammad Ansari, Christos Kotselidis, Kim Jarvis, Mikel Luján, Chris C. Kirkham, Ian Watson, Experiences using adaptive concurrency in transactional memory with Lee's routing algorithm., PPOPP 2008: 261-262
Mohammad Ansari, Christos Kotselidis, Kim Jarvis, Mikel Luján, Chris C. Kirkham, Ian Watson, Advanced Concurrency Control for Transactional Memory Using Transaction Commit Rate., Euro-Par 2008: 719-728
Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris Kirkham, Ian Watson, Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan, De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs., DATE 2008: 1370-1373
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi, Graph based test case generation for TLM functional verification., Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 288-295 (2008)
Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi, Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions., ISQED 2008: 230-235
Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi, Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification., DSD 2008: 714-720
Mohammed Fellahi, Albert Cohen, Software Pipelining in Nested Loops with Prolog-Epilog Merging, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Morten S. Rasmussen, Matthias B. Stuart, Sven Karlsson, Parallelism and Scalability in an Image Processing Application., IWOMP 2008: 158-169
Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen, Post-pass periodic register allocation to minimise loop unrolling degree., LCTES 2008: 141-150
Muhammad Anis, Reinhard Tielert, Norbert Wehn, 3.1-to-7GHz UWB impulse radio transceiver front-end based on statistical correlation technique., ISCAS 2008: 664-667
N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung, Characterisation of FPGA Clock Variability., ISVLSI 2008: 322-328
N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung, Measuring and modeling FPGA clock variability., FPGA 2008: 258
N. Pete Sedcole, Peter Y. K. Cheung, Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations., TRETS 1(2): (2008)
N. Venkateswaran, Vinoth Krishnan Elangovan, Karthik Ganesan, T. R. S. Sagar, S. Aananthakrishanan, S. Ramalingam, Shyamsundar Gopalakrishnan, Madhavan Manivannan, Deepak Srinivasan, Viswanath Krishna, On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system., IPDPS 2008: 1-8
Nastaran Baradaran, Pedro C. Diniz, A compiler approach to managing storage and memory bandwidth in configurable architectures., ACM Trans. Design Autom. Electr. Syst. 13(4): (2008)
Nathan Chong, Samin Ishtiaq, Reasoning about the ARM weakly consistent memory model., MSPC 2008: 16-19
Nearchos Paspallis, George A. Papadopoulos, An Optimization of Context Sharing for Self-adaptive Mobile Applications, ICA3PP '08: Proceedings of the 8th international conference on Algorithms and Architectures for Parallel Processing, Springer-Verlag, June 2008
Nearchos Paspallis, Romain Rouvoy, Paolo Barone, George A. Papadopoulos, Frank Eliassen, Alessandro Mamelli, A Pluggable and Reconfigurable Architecture for a Context-Aware Enabling Middleware System, OTM '08: Proceedings of the OTM 2008 Confederated International Conferences, CoopIS, DOA, GADA, IS, and ODBASE 2008. Part I on On the Move to Meaningful Internet Systems:, Springer-Verlag, November 2008
Neeraj Suri, Christof Fetzer, Jacob Abraham, Stefan Poledna, Avi Mendelson, Subhasish Mitra, Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems., DATE 2008: 1394-1395
Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis Paschalis, Dimitris Gizopoulos, Hybrid Software-Based Self-Test (H-SBST): Methodology and Application on a Modern Processor Core, IEEE Design and Test of Computers, vol. 25, no. 1, pp. 64-75, January-February 2008.
Nicholas Nash, David Gregg, Comparing Integer Data Structures for 32 and 64 Bit Keys., WEA 2008: 28-42
Nicholas Nash, Sylvain Lelait, David Gregg, Efficiently implementing maximum independent set algorithms on circle graphs, Journal of Experimental Algorithmics (JEA) , Volume 13, ACM, December 2008
Nickolai Zeldovich, Hari Kannan, Michael Dalton, Christos Kozyrakis, Hardware Enforcement of Application Security Policies Using Tagged Memory., OSDI 2008: 225-240
Nicola E. L'Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni, Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems., IEICE Transactions 91-C(4): 487-496 (2008)
Niklas Holsti, Jan Gustafsson, Guillem Bernat, Clément Ballabriga, Armelle Bonenfant, Roman Bourgade, Hugues Cassé, Daniel Cordes, Albrecht Kadlec, Raimund Kirner, Jens Knoop, Paul Lokuc, WCET 2008 - Report from the Tool Challenge 2008 -- 8th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis., WCET 2008
Nikola Vujic, Marc González, Xavier Martorell, Eduard Ayguadé, Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture., LCPC 2008: 31-46
Nikos Anastopoulos, Nectarios Koziris, Facilitating efficient synchronization of asymmetric threads on hyper-threaded processors., IPDPS 2008: 1-8
Nikos Chrysos, Giorgos Dimitrakopoulos, Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation., Hot Interconnects 2008: 67-74
Noel Tomás, Julio Sahuquillo, Salvador Petit, Pedro López, Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot., Euro-Par 2008: 317-326
Nuno Sebastião, Tiago Dias, Nuno Roma, Paulo Flores, Leonel Sousa, Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Olav Lysne, José Miguel Montañana, Jose Flich, José Duato, Timothy Mark Pinkston, Tor Skeie, An Efficient and Deadlock-Free Network Reconfiguration Protocol., IEEE Trans. Computers 57(6): 762-779 (2008)
Olav Lysne, Sven-Arne Reinemo, Tor Skeie, Ashild Gronstad Solheim, Thomas Sodring, Lars Paul Huse, Bjorn Dag Johnsen, Interconnection Networks: Architectural Challenges for Utility Computing Data Centers, Computer , Volume 41 Issue 9, IEEE Computer Society Press, September 2008
Oleg Morajko, Anna Morajko, Tomàs Margalef, Emilio Luque, On-Line Performance Modeling for MPI Applications., Euro-Par 2008: 68-77
Olivier Certner, Zheng Li, Pierre Palatin, Olivier Temam, Frederic Arzel, Nathalie Drach, A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs., DATE 2008: 740-745
Oreste Villa, Gianluca Palermo, Cristina Silvano, Efficiency and scalability of barrier synchronization on NoC based many-core architectures., CASES 2008: 81-90
Ozana Silvia Dragomir, Elena Moscu Panainte, Koen Bertels, Stephan Wong, Optimal Unroll Factor for Reconfigurable Architectures., ARC 2008: 4-14
Ozana Silvia Dragomir, Todor Stefanov, Koen Bertels, Loop unrolling and shifting for reconfigurable architectures., FPL 2008: 167-172
Ozcan Ozturk, Mahmut T. Kandemir, ILP-Based energy minimization techniques for banked memories., ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
Ozcan Ozturk, Mahmut T. Kandemir, Guangyu Chen, Access pattern-based code compression for memory-constrained systems., ACM Trans. Design Autom. Electr. Syst. 13(4): (2008)
Ozcan Ozturk, Mahmut T. Kandemir, Sri Hari Krishna Narayanan, A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm., ISQED 2008: 738-743
Ozcan Ozturk, Seung Woo Son, Mahmut T. Kandemir, Mustafa Karaköy, Prefetch throttling and data pinning for improving performance of shared caches., SC 2008: 59
Ozcan Ozturk, Vinay Chande, Haitong Sun, Mehmet Yavuz, Bibhu Mohanty, Mario Scipione, Performance of VoIP services over 3GPP WCDMA networks., PIMRC 2008: 1-6
P. Fritzsche, Dolores Rexachs, Emilio Luque, A General Approach to Predict the Performance Order of TSP Family Problems., ICA3PP 2008: 97-108
Pablo Abad, Valentin Puente, José-Ángel Gregorio, Reducing the Interconnection Network Cost of Chip Multiprocessors., NOCS 2008: 183-192
Pablo Cortés, José M. García, Jesús Muñuzuri, Luis Onieva, Viral systems: A new bio-inspired optimisation approach., Computers & OR 35(9): 2840-2860 (2008)
Pablo Cortés, José M. García, Luis Onieva, Jesús Muñuzuri, José Guadix, Viral System to Solve Optimization Problems: An Immune-Inspired Computational Intelligence Approach., ICARIS 2008: 83-94
Panagiota Fatourou, Schedulers for Optimistic Rate Based Flow Control., Encyclopedia of Algorithms 2008
Panagiotis Afratis, Euripides Sotiriades, Grigorios Chrysos, Sotiria Fytraki, Dionisios N. Pnevmatikatos, A rate-based prefiltering approach to blast acceleration., FPL 2008: 631-634
Paolo Ienne, P. Petrov, Guest Editorial Special Section on Application Specific Processors., IEEE Trans. VLSI Syst. 16(10): 1257-1258 (2008)
Pascal Felber, Christof Fetzer, Rachid Guerraoui, Tim Harris, Transactions are back---but are they the same?: "Le Retour de Martin Guerre" (Sommersby)., SIGACT News 39(1): 47-58 (2008)
Pascal Felber, Christof Fetzer, Torvald Riegel, Dynamic performance tuning of word-based software transactional memory., PPOPP 2008: 237-246
Pascal Felber, Toan Luu, Martin Rajman, Etienne Riviere, Managing collaborative feedback information for distributed retrieval., LSDS-IR 2008: 27-34
Paul Biggar, Nicholas Nash, Kevin Williams, David Gregg, An experimental study of sorting and branch prediction., ACM Journal of Experimental Algorithmics 12: (2008)
Paul Kaufmann, Marco Platzner, Advanced techniques for the creation and propagation of modules in cartesian genetic programming., GECCO 2008: 1219-1226
Paul Lokuciejewski, Heiko Falk, Peter Marwedel, WCET-driven Cache-based Procedure Positioning Optimizations., ECRTS 2008: 321-330
Paul Lokuciejewski, Heiko Falk, Peter Marwedel, Henrik Theiling, WCET-driven code-size critical procedure cloning., SCOPES 2008: 21-30
Pedro A. Castillo Valdivieso, Juan Julián Merelo Guervós, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luís Jiménez Laredo, Sally A. , Evolutionary system for prediction and optimization of hardware architecture performance., IEEE Congress on Evolutionary Computation 2008: 1941-1948
Pedro A. Castillo, Antonio Miguel Mora, Juan Julián Merelo Guervós, Juan Luís Jiménez Laredo, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Sally A. McKee, Architecture Performance Prediction Using Evolutionary Artificial Neural Networks., EvoWorkshops 2008: 175-183
Pedro C. Diniz, Diogo R. Ferreira, Automatic Extraction of Process Control Flow from I/O Operations., BPM 2008: 342-357
Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk, An FPGA run-time parameterisable Log-Normal Random Number Generator., ARC 2008: 219-230
Pedro Miguens Matutino, Leonel Sousa, An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Pedro Tomás, João Martins, Leonel Sousa, Towards a Unified Model for the Retina - Static vs Dynamic Integrate and Fire Models., BIOSIGNALS (2) 2008: 528-533
Pedro Trancoso, Artemakis Artemiou, Exploiting the GPU to accelerate DSS query execution., Conf. Computing Frontiers 2008: 109-110
Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi, Stall Power Reduction in Pipelined Architecture Processors., VLSI Design 2008: 541-546
Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, Zainalabedin Navabi, BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs., DATE 2008: 1408-1413
Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi, Enhanced TED: A New Data Structure for RTL Verification., VLSI Design 2008: 481-486
Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala, Heikki Kultala, Mikael Lepistö, Reducing Context Switch Overhead with Compiler-Assisted Threading, EUC '08: Proceedings of the 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing - Volume 02 , Volume 02, IEEE Computer Society, December 2008
Pepijn J. de Langen, Ben H. H. Juurlink, Memory copies in multi-level memory systems., ASAP 2008: 281-286
Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer, High Performance Embedded Architectures and Compilers Third International Conference HiPEAC 2008 Göteborg Sweden January 27-29 2008 Proceedings, Springer 2008
Perttu Salmela, Adrian Burian, Harri Sorokin, Jarmo Takala, Complex-valued QR decomposition implementation for MIMO receivers., ICASSP 2008: 1433-1436
Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero, Measuring Operating System Overhead on CMT Processors, SBAC-PAD '08: Proceedings of the 2008 20th International Symposium on Computer Architecture and High Performance Computing - Volume 00 , Volume 00, IEEE Computer Society, October 2008
Pete Räsänen, Simo Lintunen, Riku Kuismanen, Jyrki Joutsensalo, Timo Hämäläinen, Gradient scheduling algorithm for fair delay guarantee in logarithmic pricing scenario, Simutools '08: Proceedings of the 1st international conference on Simulation tools and techniques for communications, networks and systems & workshops, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), March 2008
Peter Benner, Enrique S. Quintana-Orti, Gregorio Quintana-Orti, Solving linear-quadratic optimal control problems on parallel computers, Optimization Methods & Software , Volume 23 Issue 6, Taylor & Francis, Inc., December 2008
Peter Bertels, Dirk Stroobandt, Java and the Power of Multi-Core Processing., CISIS 2008: 627-631
Peter Bertels, Wim Heirman, Dirk Stroobandt, Efficient measurement of data flow enabling communication-aware parallelisation., IFMT 2008: 6
Peter Y. K. Cheung, Alexandre Yakovlev, Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber., Comput. J. 51(6): 741-742 (2008)
Petru Eles, Andy D. Pimentel, Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia ESTIMedia 2008 Atlanta Georgia USA 23-24 October 2008, IEEE 2008
Philippe Bonnot, Fabrice Lemonnier, Gilbert Edelin, Gerard Gaillat, Olivier Ruch, Pascal Gauget, Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA., DATE 2008: 610-615
Pierluigi Nuzzo, Claudio Nani, Sergio Saponara, Luca Fanucci, Geert Van der Plas, Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications., DATE 2008: 1390-1393
Piero Zappi, Clemens Lombriser, Thomas Stiefmeier, Elisabetta Farella, Daniel Roggen, Luca Benini, Gerhard Tröster, Activity Recognition from On-Body Sensors: Accuracy-Power Trade-Off by Dynamic Sensor Selection., EWSN 2008: 17-33
Piia Saastamoinen, Ilkka Saastamoinen, Jari Nurmi, Code compression in DSP processor systems., IJES 3(4): 256-262 (2008)
Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest, Coffee: COmpiler Framework for Energy-Aware Exploration., HiPEAC 2008: 193-208
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung, Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework., FPL 2008: 179-184
Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope, Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models., ARC 2008: 243-253
Quan Le Trung, Paal E. Engelstad, Tor Skeie, Amirhosein Taherkordi, Load-balance of intra/inter-MANET traffic over multiple internet gateways., MoMM 2008: 50-57
R. Arteaga, Félix Tobajas, Roberto Esper-Chaín, V. de Armas, Roberto Sarmiento, GMDS: Hardware implementation of novel real output queuing architecture., DATE 2008: 1450-1455
R. Caballero, Y. García-Ruiz, F. Sáenz-Pérez, A New Proposal for Debugging Datalog Programs, Electronic Notes in Theoretical Computer Science (ENTCS) , Volume 216, Elsevier Science Publishers B. V., July 2008
Raúl Martínez, Francisco J. Alfaro, José L. Sánchez, A Framework to Provide Quality of Service over Advanced Switching, IEEE Transactions on Parallel and Distributed Systems , Volume 19 Issue 8, IEEE Press, August 2008
Radu Prodan, Thomas Fahringer, Overhead Analysis of Scientific Workflows in Grid Environments., IEEE Trans. Parallel Distrib. Syst. 19(3): 378-393 (2008)
Radu Stefan, Sorin Dan Cotofana, Bitstream compression techniques for Virtex 4 FPGAs., FPL 2008: 323-328
Radu, M., Rusu, A., Berry, F, Mats Brorsson, Work in progress - graduate exchange program in microelectronics system engineering, Proceedings of 38th Annual Frontiers in Education Conference, 2008. FIE 2008.
Rafael Asenjo, Rosa Castillo, Francisco Corbera, Angeles G. Navarro, Adrian Tineo, Emilio L. Zapata, Parallelizing irregular C codes assisted by interprocedural shape analysis., IPDPS 2008: 1-12
Rafael Tornero, Juan M. Orduña, Maurizio Palesi, José Duato, A Communication-Aware Topological Mapping Technique for NoCs., Euro-Par 2008: 910-919
Rafael Tornero, Juan Manuel Orduña, Andrés Mejía, José Flich, José Duato, CART: Communication-Aware Routing Technique for Application-Specific NoCs, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato, The impact of out-of-order commit in coarse-grain fine-grain and simultaneous multithreaded architectures., IPDPS 2008: 1-11
Raimund Kirner, Albrecht Kadlec, Adrian Prantl, Markus Schordan, Jens Knoop, Towards a Common WCET Annotation Language: Essential Ingredients., WCET 2008
Rainer Buchty, Oliver Mattes, Wolfgang Karl, Self-aware Memory: Managing Distributed Memory in an Autonomous Multi-master Environment., ARCS 2008: 98-113
Rainer Buchty, Wolfgang Karl, Design Aspects of Self-Organizing Heterogeneous Multi-Core Architectures (Entwurfsaspekte selbstorganisierender heterogener Multicore-Architekturen)., it - Information Technology 50(5): 293-299 (2008)
Rainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle, System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures., DATE 2008
Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich, Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Raphaël Chand, Pascal Felber, Scalable Distribution of XML Content with XNet., IEEE Trans. Parallel Distrib. Syst. 19(4): 447-461 (2008)
Raphaël Kummer, Peter G. Kropf, Pascal Felber, Building multicast trees in ad-hoc networks., Autonomics 2008: 26
Raul Wirz, Manuel Ferre, Raúl Marín, Jorge Barrio, José M. Claver, Javier Ortego, Efficient Transport Protocol for Networked Haptics Applications., EuroHaptics 2008: 3-12
Raul Wirz, Raúl Marín, José M. Claver, Manuel Ferre, Rafael Aracil, Josep Fernández, End-to-end congestion control protocols for remote programming of robots using heterogeneous networks: A comparative analysis., Robotics and Autonomous Systems 56(10): 865-874 (2008)
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Corporaal, DC-SIMD : Dynamic communication for SIMD processors., IPDPS 2008: 1-10
Reinaldo Bergamaschi, Luca Benini, Krisztian Flautner, Wido Kruijtzer, Alberto Sangiovanni-Vincentelli, Kazutoshi Wakabayashi, The State of ESL Design, IEEE Design & Test , Volume 25 Issue 6, IEEE Computer Society Press, November 2008
Reinhard Wilhelm, Jakob Engblom, Andreas Ermedahl, Niklas Holsti, Stephan Thesing, David B. Whalley, Guillem Bernat, Christian Ferdinand, Reinhold Heckmann, Tulika Mitra, Frank Mueller, Isabelle Puaut, The worst-case execution-time problem - overview of methods and survey of tools., ACM Trans. Embedded Comput. Syst. 7(3): (2008)
Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis, BRAM-LUT Tradeoff on a Polymorphic DES Design., HiPEAC 2008: 55-65
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, On-the-fly attestation of reconfigurable hardware., FPL 2008: 71-76
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis, Cost-Efficient SHA Hardware Accelerators., IEEE Trans. VLSI Syst. 16(8): 999-1008 (2008)
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis, Merged Computation for Whirlpool Hashing., DATE 2008: 272-275
Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato, Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs., HiPC 2008: 555-568
Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato, A fault-tolerant directory-based cache coherence protocol for CMP architectures., DSN 2008: 267-276
Ricardo Fernandez-Pascual, José M. García, Manuel E. Acacio, José Duato, Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures, IEEE Transactions on Parallel and Distributed Systems , Volume 19 Issue 8, IEEE Press, August 2008
Ricardo Quislant, Ezequiel Herruzo, Oscar G. Plata, José Ignacio Benavides, Emilio L. Zapata, Teaching the Cache Memory System Using a Reconfigurable Approach., IEEE Trans. Education 51(3): 336-341 (2008)
Rickard Holsmark, Maurizio Palesi, Shashi Kumar, Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions, Journal of Systems Architecture
Rickard Holsmark, Maurizio Palesi, Shashi Kumar, Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions., Journal of Systems Architecture - Embedded Systems Design 54(3-4): 427-440 (2008)
Robert Brendle, Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich, Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks., ARCS 2008: 117-129
Roberto Giorgi, Paolo Bennati, Reducing Leakage through Filter Cache, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Roberto Giorgi, Paolo Bennati, Filtering drowsy instruction cache to achieve better efficiency., SAC 2008: 1554-1555
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Arnaldo Azevedo, Ben Juurlink, Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Roberto R. Osorio, Javier D. Bruguera, An FPGA architecture for CABAC decoding in manycore systems., ASAP 2008: 293-298
Roberto R. Osorio, Javier D. Bruguera, An FPGA Architecture for CABAC Decoding in Many-core Systems, IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP)
Robin Message, Alan Mycroft, Controlling Control Flow in Web Applications., Electr. Notes Theor. Comput. Sci. 200(3): 119-131 (2008)
Roger F. Woods, Katherine Compton, Christos-Savvas Bouganis, Pedro C. Diniz, Reconfigurable Computing: Architectures Tools and Applications 4th International Workshop ARC 2008 London UK March 26-28 2008. Proceedings, Springer 2008
Roger Ferrer, Marc González, Federico Silla, Xavier Martorell, Eduard Ayguadé, Evaluation of memory performance on the cell BE with the SARC programming model, MEDEA '08: Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, October 2008
Roger Kahn, Shlomo Weiss, Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers., Microprocessors and Microsystems - Embedded Hardware Design 32(8): 425-436 (2008)
Roland Reichle, Michael Wagner, Mohammad Ullah Khan, Kurt Geihs, Massimo Valla, Cristina Fra, Nearchos Paspallis, George A. Papadopoulos, A Context Query Language for Pervasive Computing Environments, PERCOM '08: Proceedings of the 2008 Sixth Annual IEEE International Conference on Pervasive Computing and Communications - Volume 00 , Volume 00, IEEE Computer Society, March 2008
Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David Blaauw, Dennis Sylvester, Krisztián Flautner, Reconfigurable energy efficient near threshold cache architectures., MICRO 2008: 459-470
Roque Rodriguez, Ana Cortés, Tomàs Margalef, Emilio Luque, An Adaptive System for Forest Fire Behavior Prediction., CSE 2008: 275-282
Rosa Castillo, Francisco Corbera, Angeles G. Navarro, Rafael Asenjo, Emilio L. Zapata, Complete Def-Use Analysis in Recursive Programs with Dynamic Data Structures., Euro-Par Workshops 2008: 273-282
Rosa Filgueira, David E. Singh, Juan Carlos Pichel, Florin Isaila, Jesús Carretero, Data Locality Aware Strategy for Two-Phase Collective I/O., VECPAR 2008: 137-149
Rosa Filgueira, David E. Singh, Juan Carlos Pichel, Jesús Carretero, Exploiting data compression in collective I/O techniques., CLUSTER 2008: 479-485
Rosa M. Badia, D. Du, Eduardo Huedo, A. Kokossis, Ignacio Martín Llorente, Rubén S. Montero, Marc de Palol, Raúl Sirvent, Constantino Vázquez, Integration of GRID Superscalar and GridWay Metascheduler with the DRMAA OGF Standard., Euro-Par 2008: 445-455
Rosa M. Badia, Dennis Gannon, Craig Lee, Special section: Selected papers from the 7th IEEE/ACM international conference on grid computing (Grid2006)., Future Generation Comp. Syst. 24(5): 402-403 (2008)
Rosemary M. Francis, Simon W. Moore, Robert D. Mullins, A Network of Time-Division Multiplexed Wiring for FPGAs., NOCS 2008: 35-44
Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar, Parallel vs. serial on-chip communication., SLIP 2008: 43-50
Rostislav (Reuven) Dobkin, Ran Ginosar, Fast Universal Synchronizers., PATMOS 2008: 199-208
Roya Choupani, Stephan Wong, Mehmet R. Tolun, Weighted Embedded Zero Tree for Scalable Video Compression., IPCV 2008: 681-684
Rudy Sicard, Thierry Artières, Eric Petit, Learning iteratively a classifier with the Bayesian Model Averaging Principle., Pattern Recognition 41(3): 930-938 (2008)
Rui Marcelino, Horácio C. Neto, João M. P. Cardoso, Sorting Units for FPGA-Based Embedded Systems., DIPES 2008: 11-22
Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich, Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device., IEEE Trans. VLSI Syst. 16(9): 1210-1219 (2008)
Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich, No-break dynamic defragmentation of reconfigurable devices., FPL 2008: 113-118
Sébastien Collette, Liliana Cucu, Joël Goossens, Integrating job parallelism in real-time scheduling theory., Inf. Process. Lett. 106(5): 180-187 (2008)
S. Antonatos, M. Athanatos, G. Kondaxis, J. Velegrakis, N. Hatzibodozis, S. Ioannidis, E. P. Markatos, Honey@home: A New Approach to Large-Scale Threat Monitoring, WISTDCS '08: Proceedings of the 2008 WOMBAT Workshop on Information Security Threats Data Collection and Sharing - Volume 00 , Volume 00, IEEE Computer Society, April 2008
S. Masoud Sadjadi, Liana Fong, Rosa M. Badia, Javier Figueroa, Javier Delgado, Xabriel J. Collazo-Mojica, Khalid Saleem, Raju Rangaswami, Shu Shimizu, Hector A. Duran Limon, Pat Welsh, Sandeep Pattnai, Transparent grid enablement of weather research and forecasting, MG '08: Proceedings of the 15th ACM Mardi Gras conference: From lightweight mash-ups to lambda grids: Understanding the spectrum of distributed computing requirements, applications, tools, infrastructures, interoperability, and the incremental adoption of key capabilities, ACM, January 2008
S. Shervin Ostadzadeh, Jafar Habibi, S. Arash Ostadzadeh, A Framework for Decision Support Systems Based on Zachman Framework., SCSS (2) 2008: 497-502
Sabri Pllana, Siegfried Benkner, Eduard Mehofer, Lasse Natvig, Fatos Xhafa, Towards an Intelligent Environment for Programming Multi-core Computing Systems., Euro-Par Workshops 2008: 141-151
Sabri Pllana, Siegfried Benkner, Fatos Xhafa, Leonard Barolli, Hybrid Performance Modeling and Prediction of Large-Scale Computing Systems., CISIS 2008: 132-138
Sacha Loitz, Markus Wedler, Christian Brehm, Timo Vogt, Norbert Wehn, Wolfgang Kunz, Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking., SASP 2008: 48-54
Salman A. Khan, Andries P. Engelbrecht, Fuzzy hybrid simulated annealing algorithms for topology design of switched local area networks, Soft Computing - A Fusion of Foundations, Methodologies and Applications , Volume 13 Issue 1, Springer-Verlag, August 2008
Samuel Rodrigo, José Flich, José Duato, Mark Hummel, Efficient unicast and multicast support for CMPs., MICRO 2008: 364-375
Samuel Rodrigo, Jose Flich, José Duato, Mark Hummel, Efficient unicast and multicast support for CMPs., MICRO 2008: 364-375
Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli, Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2/sup m/)., IEEE Trans. Computers 57(5): 672-685 (2008)
Sascha Uhrig, A Flexible Java-on-Chip Solution (Eine flexible Java-on-Chip Lösung)., it - Information Technology 50(5): 317-323 (2008)
Sean Rul, Hans Vandierendonck, Koen De Bosschere, Extracting coarse-grain parallelism in general-purpose programs., PPOPP 2008: 281-282
Sebastian Hack, Gerhard Goos, Copy coalescing by graph recoloring., PLDI 2008: 227-237
Sebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero, Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications., SAMOS 2008: 53-64
Sebastien Revol, Safouan Taha, François Terrier, Alain Clouard, Sébastien Gérard, Ansgar Radermacher, Jean-Luc Dekeyser, Unifying HW Analysis and SoC Design Flows by Bridging Two Key Standards: UML and IP-XACT., DIPES 2008: 69-78
Serafeim Zanikolas, Rizos Sakellariou, An Importance-Aware Architecture for Large-Scale Grid Information Services., Parallel Processing Letters 18(3): 347-370 (2008)
Sergei Gorlatch, Frank Glinka, Alexander Ploss, Jens Müller-Iden, Radu Prodan, Vlad Nae, Thomas Fahringer, Enhancing Grids for Massively Multiplayer Online Computer Games., Euro-Par 2008: 466-477
Sergio Barrachina, Maribel Castillo, Francisco D. Igual, Rafael Mayo, Enrique S. Quintana-Ortí, Evaluation and tuning of the Level 3 CUBLAS for graphics processors., IPDPS 2008: 1-8
Sergio Barrachina, Maribel Castillo, Francisco D. Igual, Rafael Mayo, Enrique S. Quintana-Ortí, Solving Dense Linear Systems on Graphics Processors., Euro-Par 2008: 739-748
Sergio Saponara, Francesco Vitullo, Riccardo Locatelli, Philippe Teninge, Marcello Coppola, Luca Fanucci, LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Sergio Saponara, Michele Casula, Luca Fanucci, ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing., J. Real-Time Image Processing 3(3): 201-216 (2008)
Sergio Saponara, Nicola E. L'Insalata, Tony Bacchillone, Esa Petri, Iacopo Del Corona, Luca Fanucci, Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Seung Woo Son, Sai Prashanth Muralidhara, Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu, Mustafa Karaköy, Profiler and compiler assisted adaptive I/O prefetching for shared storage caches., PACT 2008: 112-121
Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne, Design space exploration for field programmable compressor trees., CASES 2008: 207-216
Seyed Masoud Sadjadi, Liana Fong, Rosa M. Badia, Javier Figueroa, Javier Delgado, Xabriel J. Collazo-Mojica, Khalid Saleem, Raju Rangaswami, Shu Shimizu, Hector A. Duran-Limon, Pat Welsh, Sandeep Patt, Transparent grid enablement of weather research and forecasting., Mardi Gras Conference 2008: 39
Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen, A Reactive and Cycle-True IP Emulator for MPSoC Exploration., IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 109-122 (2008)
Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker Dulay, Emil C. Lupu, Geoffrey Brown, Reconfigurable Architecture for Network Flow Analysis., IEEE Trans. VLSI Syst. 16(1): 57-65 (2008)
Shimin Chen, Michael Kozuch, Theodoros Strigkos, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael Ryan, Evangelos Vlachos, Flexible Hardware Acceleration for Instruction-Grain Program Monitoring, ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, ACM, June 2008
Shinichi Yamagiwa, Koichi Wada, Leonel Sousa, Heuristic Optimization Methods for Improving Performance of Recursive General Purpose Applications on GPUs., ISPDC 2008: 325-332
Shinichi Yamagiwa, Leonel Sousa, Design and implementation of a tool for modeling and programming deadlock free meta-pipeline applications., IPDPS 2008: 1-8
Shuvra S. Bhattacharyya, Jarmo Takala, Georgi Gaydadjiev, Introduction to the Special Issue on Embedded Computing Systems for DSP., Signal Processing Systems 50(2): 97-98 (2008)
Silvia Rueda, Pedro Morillo, Juan M. Orduña, A comparative study of awareness methods for peer-to-peer distributed virtual environments., Journal of Visualization and Computer Animation 19(5): 537-552 (2008)
Simon Marlow, Tim Harris, Roshan P. James, Simon L. Peyton Jones, Parallel generational-copying garbage collection with a block-structured heap., ISMM 2008: 11-20
Simon Ogg, Enrico Valli, Bashir M. Al-Hashimi, Alexandre Yakovlev, Crescenzo D'Alessandro, Luca Benini, Serialized Asynchronous Links for NoC., DATE 2008: 1003-1008
Simon Polstra, Tessa E. Pronk, Andy D. Pimentel, Timo M. Breit, Towards Design Space Exploration for Biological Systems., JCP 3(2): 1-9 (2008)
Simone Campanoni, William Fornaciari, Models and Tradeoffs in WSN System-Level Design., DSD 2008: 676-684
Simone Corbetta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, A light-weight Network-on-Chip architecture for dynamically reconfigurable systems., ICSAMOS 2008: 49-56
Simone Medardoni, Marcello Lajolo, Davide Bertozzi, Variation tolerant NoC design by means of self-calibrating links., DATE 2008: 1402-1407
Slobodan Lukovic, Leandro Fiorin, An Automated Design Flow for NoC-based MPSoCs on FPGA., IEEE International Workshop on Rapid System Prototyping 2008: 58-64
Slobodan Lukovic, Leandro Fiorin, An Automated Design Flow for NoC-based MPSoCs on FPGA, RSP '08: Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Volume 00 , Volume 00, IEEE Computer Society, June 2008
Soledad Escolar, Jesús Carretero, Florin Isaila, Stefano Lama, A lightweight storage system for sensor nodes., PDPTA 2008: 638-644
Sonia Estévez-Martín, Antonio J. Fernández, Teresa Hortalá-González, Mario Rodríguez-Artalejo, Fernando Sáenz-Pérez, Rafael del Vado Vírseda, Cooperation of constraint domains in the TOY system, PPDP '08: Proceedings of the 10th international ACM SIGPLAN conference on Principles and practice of declarative programming, ACM, July 2008
Soonhoi Ha, Kiyoung Choi, Taewhan Kim, Krisztián Flautner, Sang Lyul Min, Wang Yi, Introduction to embedded systems week 2006 special issue., ACM Trans. Embedded Comput. Syst. 7(2): (2008)
Sotiris Xydis, George Economakos, Dimitrios Soudris, Kiamal Pekmestzi, Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility, AHS '08: Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems - Volume 00 , Volume 00, IEEE Computer Society, June 2008
Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen Boyd, Luca Benini, Giovanni De Micheli, Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization., DATE 2008: 110-115
Sriram Srinivasan, Alan Mycroft, Kilim: Isolation-Typed Actors for Java., ECOOP 2008: 104-128
Stanley Jaddoe, Andy D. Pimentel, Signature-Based Calibration of Analytical System-Level Performance Models., SAMOS 2008: 268-278
Stavros Passas, George Kotsis, Sven Karlsson, Angelos Bilas, Exploiting spatial parallelism in Ethernet-based cluster interconnects., IPDPS 2008: 1-8
Stefan Metzlaff, Sascha Uhrig, Jörg Mische, Theo Ungerer, Predictable dynamic instruction scratchpad for simultaneous multithreaded processors, MEDEA '08: Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, October 2008
Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal, Scenario Selection and Prediction for DVS-Aware Scheduling of Multimedia Applications., Signal Processing Systems 50(2): 137-161 (2008)
Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal, Application Scenarios in Streaming-Oriented Embedded-System Design, IEEE Design & Test , Volume 25 Issue 6, IEEE Computer Society Press, November 2008
Stefan Wildermann, Jürgen Teich, 3D Person Tracking with a Color-Based Particle Filter., RobVis 2008: 327-340
Stefan Wildermann, Jürgen Teich, A Sequential Learning Resource Allocation Network for Image Processing Applications., HIS 2008: 132-137
Stefano Baraldi, Luca Benini, Omar Cafini, Alberto Del Bimbo, Elisabetta Farella, Giulia Gelmini, Lea Landucci, Augusto Pieracci, Nicola Torpei, Evolving tuis with smart objects for multi-context interaction., CHI Extended Abstracts 2008: 2955-2960
Stefanos Kaxiras, Computer Architecture Techniques for Power-Efficiency, 1st edition, Computer Architecture Techniques for Power-Efficiency, 1st edition, Morgan and Claypool Publishers, June 2008
Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk, A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications., TRETS 1(1): (2008)
Stijn Eyerman, Lieven Eeckhout, System-Level Performance Metrics for Multiprogram Workloads, IEEE Micro , Volume 28 Issue 3, IEEE Computer Society Press, May 2008
Stijn Eyerman, Lieven Eeckhout, James E. Smith, Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis., HiPEAC 2008: 114-129
Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung, Custom parallel caching schemes for hardware-accelerated image compression., J. Real-Time Image Processing 3(4): 289-302 (2008)
Suzanne Rivoire, Parthasarathy Ranganathan, Christos Kozyrakis, A Comparison of High-Level Full-System Power Models., HotPower 2008
Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich,, Coarse-grained reconfiguration., FPL 2008: 349
Svetislav Momcilovic, Leonel Sousa, A Parallel Algorithm for Advanced Video Motion Estimation on Multicore Architectures., CISIS 2008: 831-836
Taeho Kgil, Ali G. Saidi, Nathan L. Binkert, Steven K. Reinhardt, Krisztián Flautner, Trevor N. Mudge, PicoServer: Using 3D stacking technology to build energy efficient servers., JETC 4(4): (2008)
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero, Runahead Threads to improve SMT performance., HPCA 2008: 149-158
Tarik Saidani, Joel Falcou, Lionel Lacassagne, Samir Bouaziz, Altivec Vector Unit Customization for Embedded Systems., IJCSA 5(3a): 20-32 (2008)
Tarik Saidani, Lionel Lacassagne, Joel Falcou, Claude Tadonki, Parallelization Scheles for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector, HiPEAC
Tariq Abdullah, Vassiliy Sokolov, Behnaz Pourebrahimi, Koen Bertels, Self-Organizing Dynamic Ad Hoc Grids, SASOW '08: Proceedings of the 2008 Second IEEE International Conference on Self-Adaptive and Self-Organizing Systems Workshops - Volume 00 , Volume 00, IEEE Computer Society, October 2008
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Ozcan Ozturk, SPM management using Markov chain based data access prediction., ICCAD 2008: 565-569
Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk, Global interconnections in FPGAs: modeling and performance analysis., SLIP 2008: 51-58
Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk, Implementation of Wave-Pipelined Interconnects in FPGAs., NOCS 2008: 213-214
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Interconnection lengths and delays estimation for communication links in FPGAs., SLIP 2008: 1-10
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, High-throughput interconnect wave-pipelining for global communication in FPGAs., FPGA 2008: 258
Tewolde S. Tewolde, Weihua Sheng, Robot Path Integration in Manufacturing Processes: Genetic Algorithm Versus Ant Colony Optimization., IEEE Transactions on Systems Man and Cybernetics Part A 38(2): 278-287 (2008)
Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne, MPSoC Design Using Application-Specific Architecturally Visible Communication, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon, Speculative DMA for architecturally visible storage in instruction set extensions., CODES+ISSS 2008: 243-248
Theo Ungerer, Keynote: Grand Challenges of Computer Engineering., ARCS 2008: 3
Theo Ungerer, Computer Architecture Challenges (Rechnerarchitektur - Herausforderungen der nächsten Jahre)., it - Information Technology 50(5): 283-284 (2008)
Theocharis Theocharides, Maria K. Michael, Marios Polycarpou, Ajit Dingankar, A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures, ISVLSI '08: Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI - Volume 00 , Volume 00, IEEE Computer Society, April 2008
Thilo Streichert, Michael Glaß, Rolf Wanka, Christian Haubelt, Jürgen Teich, Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks., ARCS 2008: 23-37
Thomas A. M. Bernard, Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp, Michiel W. van Tol, Li Zhang, A general model of concurrency and its implementation as many-core dynamic RISC processors., ICSAMOS 2008: 1-9
Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos, Temporal streams in commercial server applications., IISWC 2008: 99-108
Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev, Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems., DATE 2008: 1346-1351
Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev, Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices., ARC 2008: 302-307
Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Sven-Arne Reinemo, An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Thomas van Noort, Alexey Rodriguez, Stefan Holdermans, Johan Jeuring, Bastiaan Heeren, A lightweight approach to datatype-generic rewriting., ICFP-WGP 2008: 13-24
Thuy Duong Vu, Li Zhang, Chris R. Jesshope, The Verification of the On-Chip COMA Cache Coherence Protocol., AMAST 2008: 413-429
Tim Harris, Simon Marlow, Simon L. Peyton Jones, Maurice Herlihy, Composable memory transactions., Commun. ACM 51(8): 91-100 (2008)
Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr, Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips., IJES 3(3): 150-159 (2008)
Tim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk, Smart Enumeration: A Systematic Approach to Exhaustive Search., PATMOS 2008: 429-438
Timo Vanhatupa, Marko Hännikäinen, Timo D. Hämäläinen, Performance model for IEEE 802.11s wireless mesh network deployment design., J. Parallel Distrib. Comput. 68(3): 291-305 (2008)
Timo Vogt, Norbert Wehn, A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment., IEEE Trans. VLSI Syst. 16(10): 1309-1320 (2008)
Timo Vogt, Norbert Wehn, A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment., DATE 2008: 38-43
Timothy D. R. Hartley, Ümit V. Çatalyürek, Antonio Ruiz, Francisco D. Igual, Rafael Mayo, Manuel Ujaldon, Biomedical image analysis on a cooperative cluster of GPUs and multicores., ICS 2008: 15-25
Timothy M. Jones, Michael F. P. O'Boyle, Oguz Ergin, Evaluating the Effects of Compiler Optimsations on AVF, Workshop on the Interaction between Compilers and Computer Architecture (INTERACT)
Timothy M. Jones, Sandro Bartolini, Bruno De Bus, John Cavazos, Michael F. P. O'Boyle, Instruction Cache Energy Saving Through Compiler Way-Placement., DATE 2008: 1196-1201
Tobias Becker, Peter Jamieson, Wayne Luk, Peter Cheung, Tero Rissa, Towards benchmarking energy efficiency of reconfigurable architectures., FPL 2008: 691-694
Tobias Schumacher, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, Marco Platzner, A Hardware Accelerator for k-th Nearest Neighbor Thinning., ERSA 2008: 245-251
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney, We have it easy but do we have it right?, IPDPS 2008: 1-7
Tom Degryse, Karel Bruneel, Harald Devos, Dirk Stroobandt, Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead, RECONFIG '08: Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs - Volume 00 , Volume 00, IEEE Computer Society, December 2008
Tommaso Cecchini, Francesco Sechi, Luca Bacciarelli, Luca Mostardini, Francesco Battini, Luca Fanucci, Marco De Marinis, Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Tommaso Cucinotta, Access Control for Adaptive Reservations on Multi-User Systems., IEEE Real-Time and Embedded Technology and Applications Symposium 2008: 387-396
Toomas P. Plaks, Marco D. Santambrogio, Donatella Sciuto, Editorial: reconfigurable computing and hardware/software codesign, EURASIP Journal on Embedded Systems , Volume 2008, Hindawi Publishing Corp., January 2008
Toomas P. Plaks, Marco D. Santambrogio, Donatella Sciuto, Editorial: reconfigurable computing and hardware/software codesign, EURASIP Journal on Embedded Systems , Volume 8 Issue 3, Hindawi Publishing Corp., April 2008
Tor Skeie, Daniel Ortega, Jose Flich, Raimir Holanda, Topic 13: High-Performance Networks., Euro-Par 2008: 898
Torsten Kempf, Kingshuk Karuri, Lei Gao, Software Instrumentation., Wiley Encyclopedia of Computer Science and Engineering 2008
Torvald Riegel, Christof Fetzer, Pascal Felber, Automatic data partitioning in software transactional memories., SPAA 2008: 152-159
Tsenka Stoyanova, Fotis Kerasiotis, Aggeliki Prayati, George Papadopoulos, Communication-Aware Deployment for Wireless Sensor Networks, SENSORCOMM '08: Proceedings of the 2008 Second International Conference on Sensor Technologies and Applications - Volume 00 , Volume 00, IEEE Computer Society, August 2008
Uwe Brinkschulte, Alexander von Renteln, Mathias Pacher, Measuring the quality of an artificial hormone system based task mapping., Autonomics 2008: 32
Uwe Brinkschulte, Mathias Pacher, A Control Theory Approach to Improve the Real-Time Capability of Multi-Threaded Microprocessors., ISORC 2008: 399-404
Uwe Brinkschulte, Theo Ungerer, Christian Hochberger, Rainer G. Spallek, Architecture of Computing Systems - ARCS 2008 21st International Conference Dresden Germany February 25-28 2008 Proceedings, Springer 2008
Uwe Brinkschulte, Tony Givargis, Stefano Russo, Software Technologies for Embedded and Ubiquitous Systems 6th IFIP WG 10.2 International Workshop SEUS 2008 Anacarpi Capri Island Italy October 1-3 2008 Proceedings, Springer 2008
Víctor J. Jiménez, Lluís Vilanova, Isaac Gelado, Marisa Gil, Grigori Fursin, Nacho Navarro, Predictive Runtime Code Scheduling for Heterogeneous Architectures, HiPEAC '09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, Springer-Verlag, December 2008
Vaibhav Saxena, Prashant Agrawal, Yogish Sabharwal, Vijay K. Garg, Vimitha A. Kuruvilla, John A. Gunnels, Optimization of BLAS on the Cell Processor., HiPC 2008: 18-29
Valentin Kravtsov, David Carmeli, Werner Dubitzky, Ariel Orda, Assaf Schuster, Mark Silberstein, Benny Yoshpa, Quasi-opportunistic Supercomputing in Grid Environments., ICA3PP 2008: 233-244
Valentin Kravtsov, David Carmeli, Werner Dubitzky, Krzysztof Kurowski, Assaf Schuster, Grid-enabling complex system applications with QosCosGrid: An architectural perspective., GCA 2008: 168-174
Valentin Kravtsov, Martin Swain, Uri Dubin, Werner Dubitzky, Assaf Schuster, A Fast and Efficient Algorithm for Topology-Aware Coallocation., ICCS (1) 2008: 274-283
Valentin Puente, José Angel Gregorio, Fernando Vallejo, Ramoón Beivide, Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology, IEEE Transactions on Computers , Volume 57 Issue 12, IEEE Computer Society, December 2008
Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel, Manuel Almeida, Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable Systems., VLSI Design 2008: 85-90
Vasilis F. Pavlidis, Eby G. Friedman, Timing-driven via placement heuristics for three-dimensional ICs., Integration 41(4): 489-508 (2008)
Vasilis Pappas, Elias Athanasopoulos, Sotiris Ioannidis, Evangelos P. Markatos, Compromising Anonymity Using Packet Spinning., ISC 2008: 161-174
Vicenç Beltran, Jordi Torres, Eduard Ayguadé, Improving Web Server Performance Through Main Memory Compression., ICPADS 2008: 303-310
Vicenç Beltran, Jordi Torres, Eduard Ayguadé, Understanding tuning complexity in multithreaded and hybrid web servers., IPDPS 2008: 1-12
Vicent Cholvi, Juan Segarra, Analysis and placement of storage capacity in large distributed video servers., Computer Communications 31(15): 3604-3612 (2008)
Ville Kaseva, Mikko Kohvakka, Mauri Kuorilehto, Marko Hännikäinen, Timo D. Hämäläinen, A Wireless Sensor Network for RF-Based Indoor Localization., EURASIP J. Adv. Sig. Proc. 2008: (2008)
Vincent Gramoli, Derin Harmanci, Pascal Felber, Toward a Theory of Input Acceptance for Transactional Memories., OPODIS 2008: 527-533
Vincent Nollet, Prabhat Avasare, Hendrik Eeckhaut, Diederik Verkest, Henk Corporaal, Run-Time Management of a MPSoC Containing FPGA Fabric Tiles., IEEE Trans. VLSI Syst. 16(1): 24-33 (2008)
Vincenzo Catania, Gianmarco De Francisci Morales, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, High Performance Computing for Embedded System Design: A Case Study, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008
Vincenzo Catania, Maurizio Palesi, Davide Patti, Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems., TACO 5(2): (2008)
Vincenzo Rana, Matteo Matteucci, Daniele Caltabiano, Roberto Sannino, Andrea Bonarini, Low cost smartcams design., ESTImedia 2008: 27-32
Vlad Mihai Sima, Elena Moscu Panainte, Koen Bertels, Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform., FPL 2008: 651-654
Vlad Nae, Alexandru Iosup, Stefan Podlipnig, Radu Prodan, Dick H. J. Epema, Thomas Fahringer, Efficient management of data center resources for massively multiplayer online games., SC 2008: 10
Vlad Nae, Jordan Herbert, Radu Prodan, Thomas Fahringer, An Information System for Real-Time Online Interactive Applications., Euro-Par Workshops 2008: 361-370
Vlad Nae, Radu Prodan, Thomas Fahringer, Neural Network-Based Load Prediction for Highly Dynamic Distributed Online Games., Euro-Par 2008: 202-211
Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala, Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic., SAMOS 2008: 23-32
Vlado Stankovski, Martin Swain, Valentin Kravtsov, Thomas Niessen, Dennis Wegener, M. Rohm, Jernej Trnkoczy, Michael May, Jürgen Franke, Assaf Schuster, Werner Dubitzky, Digging Deep into the Data Mine with DataMiningGrid., IEEE Internet Computing 12(6): 69-76 (2008)
Wayne Luk, Yvon Savaria, Oskar Mencer, Guest Editorial: 20 Years of ASAP., Signal Processing Systems 53(1-2): 1-2 (2008)
Werner Grass, Bernhard Sick, Theo Ungerer, Klaus Waldschmidt, Selected papers of the ARCS06 conference: an introduction., Personal and Ubiquitous Computing 12(2): 95-96 (2008)
William G. Osborne, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer, Power-Aware and Branch-Aware Word-Length Optimization., FCCM 2008: 129-138
William G. Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer, Reconfigurable design with clock gating., ICSAMOS 2008: 187-194
Wim Heirman, Joni Dambre, Dirk Stroobandt, Jan M. Van Campenhout, Rent's rule and parallel programs: characterizing network traffic behavior., SLIP 2008: 87-94
Wolfgang Trumler, Mike Gerdes, Towards an automated detection of self-organizing behavior., GI Jahrestagung (2) 2008: 739-746
Xavier Dutoit, Benjamin Schrauwen, Jan M. Van Campenhout, Dirk Stroobandt, Hendrik Van Brussel, Marnix Nuttin, Pruning and Regularisation in Reservoir Computing: a First Insight., ESANN 2008: 1-6
Xavier Joglar, Judit Planas, Marisa Gil, OS Paradigms Adaptation to Fit New Architectures, WIOSCA 2.008
Xavier Teruel, Priya Unnikrishnan, Xavier Martorell, Eduard Ayguadé, Raúl Silvera, Guansong Zhang, Ettore Tiotto, OpenMP tasks in IBM XL compilers., CASCON 2008: 16
Yang Qu, Juha-Pekka Soininen, Jari Nurmi, Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking., DATE 2008: 264-267
Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi, Design Flow Instantiation for Run-Time Reconfigurable Systems: A Case Study., EURASIP J. Emb. Sys. 2008: (2008)
Yaser Pourmohammadi Fallah, Hassan Mansour, Salman Khan, Panos Nasiopoulos, Hussein M. Alnuweiri, A Link Adaptation Scheme for Efficient Transmission of H.264 Scalable Video Over Multirate WLANs., IEEE Trans. Circuits Syst. Video Techn. 18(7): 875-887 (2008)
Yaser Pourmohammadi Fallah, Hassan Mansour, Salman Khan, Panos Nasiopoulos, Hussein M. Alnuweiri, An optimized link adaptation scheme for efficient delivery of scalable H.264 Video over IEEE 802.11n., ISCAS 2008: 2058-2061
Yaser Pourmohammadi Fallah, Salman Khan, Panos Nasiopoulos, Hussein M. Alnuweiri, Hybrid OFDMA/CSMA Based Medium Access Control for Next-Generation Wireless LANs., ICC 2008: 2762-2768
Yevgeny Perelman, Ran Ginosar, The NeuroProcessor: An Integrated Interface to Biological Neural Networks, 1 edition, The NeuroProcessor: An Integrated Interface to Biological Neural Networks, 1 edition, Springer Publishing Company, Incorporated, October 2008
Yi Lu, Andrea Montanari, Balaji Prabhakar, Sarang Dharmapurikar, Abdul Kabbani, Counter braids: a novel counter architecture for per-flow measurement., SIGMETRICS 2008: 121-132
Yi Lu, Huaxiong Wang, San Ling, Cryptanalysis of Rabbit., ISC 2008: 204-214
Yi Lu, Lily R. Liang, Hierarchical Clustering of Features on Categorical Data of Biomedical Applications., CAINE 2008: 26-31
Yi Lu, Thomas Marconi, Georgi Gaydadjiev, Koen Bertels, An efficient algorithm for free resources management on the FPGA., DATE 2008: 1095-1098
Yi Lu, Thomas Marconi, Georgi Gaydadjiev, Koen Bertels, Roel Meeuws, A self-adaptive on-line task placement algorithm for partially reconfigurable systems., IPDPS 2008: 1-8
Yi Lu, Yan Shi, Bo Hu, Kinematic analysis of two novel 3UPU I and 3UPU II PKMs., Robotics and Autonomous Systems 56(4): 296-305 (2008)
Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous, The Significance of Affectors and Affectees Correlations for Branch Prediction., HiPEAC 2008: 243-257
Yifan He, Zoran Zivkovic, Richard P. Kleihorst, Alexander Danilin, Henk Corporaal, Bart Mesman, Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration., ACIVS 2008: 254-265
Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha, Statistical noise margin estimation for sub-threshold combinational circuits., ASP-DAC 2008: 176-179
Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong, Mapping and scheduling with task clustering for heterogeneous computing systems., FPL 2008: 275-280
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai, Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling., IEICE Transactions 91-A(2): 604-612 (2008)
Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai, Operation shuffling over cycle boundaries for low energy L0 clustering., ASAP 2008: 150-155
Yunhe Shi, Kevin Casey, M. Anton Ertl, David Gregg, Virtual machine showdown: Stack versus registers., TACO 4(4): (2008)
Z. Jian Jia, Tomás Bautista, Antonio Núnez, Cayetano Guerra, Mario Hernández, Design Space Exploration and Performance Analysis for the Modular Design of CVS in a Heterogeneous MPSoC, RECONFIG '08: Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs - Volume 00 , Volume 00, IEEE Computer Society, December 2008
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis, Test Set Development for Cache Memory in Modern Microprocessors., IEEE Trans. VLSI Syst. 16(6): 725-732 (2008)
Zhijiang Chang, Georgi Gaydadjiev, Cross-Layer Designs Architecture for LEO Satellite Ad Hoc Network., WWIC 2008: 164-176
Zoe Sebepou, Kostas Magoutis, Manolis Marazakis, Angelos Bilas, A Comparative Experimental Study of Parallel File Systems for Large-Scale Data Processing., LASCO 2008
Zubair Nawaz, Mudassir Shabbir, Zaid Al-Ars, Koen Bertels, Acceleration of Smith-Waterman using Recursive Variable Expansion, DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Volume 00 , Volume 00, IEEE Computer Society, September 2008

2009

Åke Walldius, Yngve Sundblad, Lars Bengtsson, Bengt L. Sandblad, Jan Gulliksen, User certification of workplace software: assessing both artefact and usage., Behaviour & IT 28(2): 101-120 (2009)
Åshild Grønstad Solheim, Olav Lysne, Aurelio Bermúdez, Rafael Casado, Thomas Sødring, Tor Skeie, Antonio Robles-Gómez, Efficient and deadlock-free reconfiguration for source routed networks., IPDPS 2009: 1-8
Åshild Grønstad Solheim, Olav Lysne, Tor Skeie, RecTOR: A New and Efficient Method for Dynamic Network Reconfiguration., Euro-Par 2009: 1052-1064
A. Moreno, Eduardo César, Joan Sorribes, Tomàs Margalef, Emilio Luque, Task distribution using factoring load balancing in Master-Worker applications., Inf. Process. Lett. 109(16): 902-906 (2009)
Adolf Abdallah, Abdoulayé Gamatie, Jean-Luc Dekeyser, Model-Driven Design of Embedded Multimedia Applications on SoCs., DSD 2009: 207-210
Ahmed Mohamed AbdelHamid, Ankur Anchlia, Stylianos Mamagkakis, Miguel Corbalan Miranda, Bart Dierickx, Maarten Kuijk, A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning., DSD 2009: 401-408
Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne, Arithmetic optimization for custom instruction set synthesis., SASP 2009: 54-57
Alberto Ros, Manuel E. Acacio, José M. García, Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs., APPT 2009: 11-27
Alejandra Rodríguez, Jesús Carretero, Borja Bergua, Félix García Carballeira, Resource selection for fast large-scale Virtual Appliances Propagation., ISCC 2009: 824-829
Alejandro Duran, Roger Ferrer, Eduard Ayguadé, Rosa M. Badia, Jesús Labarta, A Proposal to Extend the OpenMP Tasking Model with Dependent Tasks., International Journal of Parallel Programming 37(3): 292-305 (2009)
Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, A power-efficient migration mechanism for D-NUCA caches., DATE 2009: 598-601
Alessandro Donati, Space missions & sensor networking: challenging scenarios., KDD Workshop on Knowledge Discovery from Sensor Data 2009: 10
Alexander S. Szalay, Djoerd Hiemstra, Alfons Kemper, Manuel Prieto, Introduction., Euro-Par 2009: 347-348
Alexandra Fedorova, Juan Carlos Saez, Daniel Shelepov, Manuel Prieto, Maximizing power efficiency with asymmetric multicore systems., Commun. ACM 52(12): 48-57 (2009)
Alireza A. Nezhad, Ali Miri, Dimitrios Makrakis, Luis Orozco-Barbosa, Privacy within pervasive communications., Telecommunication Systems 40(3-4): 101-116 (2009)
Amit Golander, Shlomo Weiss, Checkpoint allocation and release., TACO 6(3): (2009)
Ana Lucia Varbanescu, Alexander S. van Amesfoort, Tim Cornwell, Ger van Diepen, Rob van Nieuwpoort, Bruce G. Elmegreen, Henk J. Sips, Building high-resolution sky images using the Cell/B.E., Scientific Programming 17(1-2): 113-134 (2009)
Anca Mariana Molnos, Kees Goossens, Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors., DSD 2009: 409-418
Anca Mariana Molnos, Sorin Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven, Compositional Dynamic Cache Management for Embedded Chip Multiprocessors., Signal Processing Systems 57(2): 155-172 (2009)
Andrea Bartolini, Martino Ruggiero, Luca Benini, Visual quality analysis for dynamic backlight scaling in LCD systems., DATE 2009: 1428-1433
Andrea Bartolini, Martino Ruggiero, Luca Benini, HVS-DBS: human visual system-aware dynamic luminance backlight scaling for video streaming applications., EMSOFT 2009: 21-28
Andrea Di Biagio, Alessandro Barenghi, Giovanni Agosta, Gerardo Pelosi, Design of a parallel AES for graphics hardware using the CUDA framework., IPDPS 2009: 1-8
Andrea Marongiu, Andrea Acquaviva, Luca Benini, OpenMP Support for NBTI-Induced Aging Tolerance in MPSoCs., SSS 2009: 547-562
Andrea Marongiu, Luca Benini, Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy., DATE 2009: 809-814
Andreas Fidjeland, Etienne B. Roesch, Murray Shanahan, Wayne Luk, NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs., ASAP 2009: 137-144
Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic, Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing., ASAP 2009: 177-182
Andreas Hansson, Mahesh Subburaman, Kees Goossens, Aelite: A flit-synchronous Network on Chip with composable and predictable services., DATE 2009: 250-255
Andreas Persson, Lars Bengtsson, Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems., Signal Processing Systems 56(1): 1-15 (2009)
Andy D. Pimentel, Naehyuck Chang, Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia ESTIMedia 2009 Grenoble France 15-16 October 2009, IEEE 2009
Andy D. Pimentel, Naehyuck Chang, Petru Eles, Samarjit Chakraborty, 2009 IEEE/ACM/IFIP 7th workshop on embedded systems for Real-Time multimedia (ESTIMedia 2009)., ESTImedia 2009: 1
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Christian Pilato, Pier Luca Lanzi, Fabrizio Ferrandi, Donatella Sciuto, Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach., CODES+ISSS 2009: 443-452
Antonino Tumeo, Simone Borgio, Davide Bosisio, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, A multiprocessor self-reconfigurable JPEG2000 encoder., IPDPS 2009: 1-8
Antonio Núñez, Pedro P. Carballo, 12th Euromicro Conference on Digital System Design Architectures Methods and Tools DSD 2009 27-29 August 2009 Patras Greece, IEEE Computer Society 2009
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Implementing a Change Assimilation Mechanism for Source Routing Interconnects., Euro-Par 2009: 1029-1039
Antonis Zissimos, Katerina Doka, Antony Chazapis, Dimitrios Tsoumakos, Nectarios Koziris, Optimizing Data Management in Grid Environments., OTM Conferences (1) 2009: 497-512
Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Evaluating SoC Network Performance in MPEG-4 Encoder., Signal Processing Systems 56(2-3): 105-123 (2009)
Arnaldo Azevedo Filho, Ben H. H. Juurlink, Scalar Processing Overhead on SIMD-Only Architectures., ASAP 2009: 183-190
Arturo González-Escribano, Arjan J. C. van Gemund, Valentín Cardeñoso-Payo, Performance implications of synchronization structure in parallel programming., Parallel Computing 35(8-9): 455-474 (2009)
Asadollah Shahbahrami, Ben H. H. Juurlink, SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform., DSD 2009: 497-504
Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii, Physically clustered forward body biasing for variability compensation in nanometer CMOS design., DATE 2009: 154-159
Ayse Kivilcim Coskun, José L. Ayala, David Atienza, Tajana Simunic Rosing, Yusuf Leblebici, Dynamic thermal management in 3D multicore architectures., DATE 2009: 1410-1415
B. de la Ossa, Julio Sahuquillo, Ana Pont, José A. Gil, An Empirical Study on Maximum Latency Saving in Web Prefetching., Web Intelligence 2009: 556-559
Barbara M. Chapman, Bart Kienhuis, Eduard Ayguadé, François Bodin, Oscar G. Plata, Eric Stotzer, Introduction., Euro-Par 2009: 837-838
Barbara M. Chapman, Jesús Labarta, Vivek Sarkar, Mitsuhisa Sato, Programmability Issues., IJHPCA 23(4): 328-331 (2009)
Bart Coppens, Ingrid Verbauwhede, Koen De Bosschere, Bjorn De Sutter, Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors., IEEE Symposium on Security and Privacy 2009: 45-60
Bart Coppens, Ingrid Verbauwhede, Koen De Bosschere, Bjorn De Sutter, , Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors., IEEE Symposium on Security and Privacy 2009: 45-60
Beniamino Di Martino, Christoph W. Kessler, Yi Pan, Thomas Rauber, Gudula Rünger, Laurence Tianruo Yang, Message from the PDSEC-09 workshop chairs., IPDPS 2009: 1-2
Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José María Llabería, A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors., Euro-Par 2009: 149-161
Benjamin Satzger, Florian Mutschelknaus, Faruk Bagci, Florian Kluge, Theo Ungerer, Towards Trustworthy Self-optimization for Distributed Systems., SEUS 2009: 58-68
Benny Akesson, Andreas Hansson, Kees Goossens, Composable Resource Sharing Based on Latency-Rate Servers., DSD 2009: 547-555
Bjorn De Sutter, Diederik Verkest, Erik Brockmeyer, Eric Delfosse, Arnout Vandecappelle, Jean-Yves Mignolet, Design and Tool Flow of Multimedia MPSoC Platforms., Signal Processing Systems 57(2): 229-247 (2009)
Bo Hu, Yi Lu, Haixia Mao, Inverse Dynamic Modeling of Two Unsymmetrical 3UPU Parallel Manipulators., ICIRA 2009: 580-591
Bo Hu, Yi Lu, Jiayin Xu, Stiffness and Singularity Analysis of 2SPS+2RPS Parallel Manipulator by Using Different Methods., ICIRA 2009: 632-644
Carles Hernandez, Federico Silla, Vicente Santonja, José Duato, A new mechanism to deal with process variability in NoC links., IPDPS 2009: 1-11
Carlo Galuzzi, Chunyang Gou, Humberto Calderon, Georgi Gaydadjiev, Stamatis Vassiliadis, High-bandwidth Address Generation Unit., Signal Processing Systems 57(1): 33-44 (2009)
Carlo Galuzzi, Dimitris Theodoropoulos, Roel Meeuws, Koen Bertels, Algorithms for the automatic extension of an instruction-set., DATE 2009: 548-553
Carlos Domínguez, Houcine Hassan, Alfons Crespo, Real-time Emotional Agent Architecture Application on Service Mobile Robot Control., IC-AI 2009: 385-391
Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González, Boosting single-thread performance in multi-core systems through fine-grain multi-threading., ISCA 2009: 474-483
Carlos Perez-Miguel, José Miguel-Alonso, Alexander Mendiburu, Evaluating the cell broadband engine as a platform to run estimation of distribution algorithms., GECCO (Companion) 2009: 2491-2498
Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala, Programmable and Scalable Architecture for Graphics Processing Units., SAMOS 2009: 2-11
Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Thread to Core Assignment in SMT On-Chip Multiprocessors., SBAC-PAD 2009: 67-74
Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides, Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator., ARC 2009: 231-242
Christian Bachmann, Andreas Genser, Jos Hulzink, Mladen Berekovic, Christian Steger, A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing., DATE 2009: 1614-1619
Christos Strydis, Georgi Gaydadjiev, Evaluating Various Branch-Prediction Schemes for Biomedical-Implant Processors., ASAP 2009: 169-176
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli, NoC topology synthesis for supporting shutdown of voltage islands in SoCs., DAC 2009: 822-825
Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Francky Catthoor, System-level process variability compensation on memory organizations: on the scalability of multi-mode memories., ASP-DAC 2009: 254-259
Corneliu Rusu, Lacrimioara Grama, Jarmo Takala, SPICE Simulation of Analog Filters: A Method for Designing Digital Filters., EUROCAST 2009: 534-539
Cosmin E. Oancea, Alan Mycroft, Stephen M. Watt, A new approach to parallelising tracing algorithms., ISMM 2009: 10-19
Cosmin E. Oancea, Alan Mycroft, Tim Harris, A lightweight in-place implementation for software thread-level speculation., SPAA 2009: 223-232
Craig Moore, Harald Devos, Dirk Stroobandt, Optimizing the FPGA Memory Design for a Sobel Edge Detector., ERSA 2009: 299-300
Crispín Gómez Requena, María Engracia Gómez Requena, Pedro Juan López Rodríguez, J. F. D. Marin, FT2EI: A Dynamic Fault-Tolerant Routing Methodology for Fat Trees with Exclusion Intervals., IEEE Trans. Parallel Distrib. Syst. 20(6): 802-817 (2009)
Damián A. Mallón, Guillermo L. Taboada, Carlos Teijeiro, Juan Touriño, Basilio B. Fraguela, Andrés Gómez, Ramon Doallo, José Carlos Mouriño, Performance Evaluation of MPI UPC and OpenMP on Multicore Architectures., PVM/MPI 2009: 174-184
Daniel Christopher Powell, Björn Franke, Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators., CODES+ISSS 2009: 315-324
Daniel Piso Fernandez, Javier D. Bruguera, Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation., DSD 2009: 293-300
Daniel Sánchez, Juan L. Aragón, José M. García, REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs., Euro-Par 2009: 321-333
Daniel Schmidt, Matthias Berning, Norbert Wehn, Error correction in single-hop wireless sensor networks - A case study., DATE 2009: 1296-1301
Daniel Schmidt, Norbert Wehn, DRAM power management and energy consumption: a critical assessment., SBCCI 2009
Daniele Ludovici, Francisco Gilabert Villamón, Simone Medardoni, Crispín Gómez Requena, María Engracia Gómez, Pedro López, Georgi Nedeltchev Gaydadjiev, Davi, Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints., DATE 2009: 562-565
Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals, Light NUCA: A proposal for bridging the inter-cache latency gap., DATE 2009: 530-535
David Bernstein, Erik Ludvigson, Krishna Sankar, Steve Diamond, Monique Morrow, Blueprint for the Intercloud - Protocols and Formats for Cloud Computing Interoperability., ICIW 2009: 328-336
David Guzman, Manuel Prieto, Daniel Garcia, Victor Ruiz, Javier Almena, Sebastian Sanchez, Daniel Meziat, High Reliable Remote Terminal Unit for Space Applications., DSD 2009: 488-493
Davy Genbrugge, Lieven Eeckhout, Chip Multiprocessor Design Space Exploration through Statistical Simulation., IEEE Trans. Computers 58(12): 1668-1681 (2009)
Demetres Antoniades, Evangelos P. Markatos, Constantine Dovrolis, One-click hosting services: a file-sharing hideout., Internet Measurement Conference 2009: 223-234
Demid Borodin, Ben H. H. Juurlink, Stefanos Kaxiras, Instruction Precomputation for Fault Detection., DSD 2009: 91-99
Diego R. Martínez, José Carlos Cabaleiro, Tomás F. Pena, Francisco F. Rivera, V. Blanco, Accurate analytical performance model of communications in MPI applications., IPDPS 2009: 1-8
Dietmar Ebner, Bernhard Scholz, Andreas Krall, Progressive spill code placement., CASES 2009: 77-86
Dimitris Theodoropoulos, Alexandros Siskos, Dionisios N. Pnevmatikatos, CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers., ARC 2009: 318-323
Dmitry Nadezhkin, Sjoerd Meijer, Todor Stefanov, Ed F. Deprettere, Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell., SAMOS 2009: 308-317
Ed F. Deprettere, Ana Lucia Varbanescu, Introduction to Mastering Cell BE and GPU Execution Platforms., SAMOS 2009: 275-276
Eduard Ayguadé, Rosa M. Badia, Francisco D. Igual, Jesús Labarta, Rafael Mayo, Enrique S. Quintana-Ortí, An Extension of the StarSs Programming Model for Platforms with Multiple GPUs., Euro-Par 2009: 851-862
Eleonora Marchetti, Luca Fanucci, A. Rocchi, Marco De Marinis, Shock immunity enhancement via resonance damping in gyroscopes for automotive applications., DATE 2009: 1094-1099
Enrique F. Torres, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería, Store Buffer Design for Multibanked Data Caches., IEEE Trans. Computers 58(10): 1307-1320 (2009)
Evangelos Mangas, Angelos Bilas, FLASH: Fine-Grained Localization in Wireless Sensor Networks Using Acoustic Sound Transmissions and High Precision Clock Synchronization., ICDCS 2009: 289-298
Farrukh Nadeem, Thomas Fahringer, Predicting the execution time of grid workflow applications through local learning., SC 2009
Felix Wolf, Andy D. Pimentel, Luiz De Rose, Soonhoi Ha, Thilo Kielmann, Anna Morajko, Introduction., Euro-Par 2009: 7-8
Fernando Royo, Teresa Olivares, Luis Orozco-Barbosa, A synchronous engine for wireless sensor networks., Telecommunication Systems 40(3-4): 151-159 (2009)
Field G. Van Zee, Ernie Chan, Robert A. van de Geijn, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, The libflame Library for Dense Matrix Computations., Computing in Science and Engineering 11(6): 56-63 (2009)
Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne, A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions., CHES 2009: 205-219
Francisco Javier Ridruejo, José Miguel-Alonso, Javier Navaridas, Full-system simulation of distributed memory multicomputers., Cluster Computing 12(3): 309-322 (2009)
Frederico Pratas, Leonel Sousa, Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study., SAMOS 2009: 237-246
Georgios I. Goumas, Kornilios Kourtis, Nikos Anastopoulos, Vasileios Karakasis, Nectarios Koziris, Performance evaluation of the sparse matrix-vector multiplication on modern architectures., The Journal of Supercomputing 50(1): 36-77 (2009)
Georgios I. Goumas, Nikolaos Drosinos, Nectarios Koziris, Communication-Aware Supernode Shape., IEEE Trans. Parallel Distrib. Syst. 20(4): 498-511 (2009)
Giacomo Paci, Davide Bertozzi, Luca Benini, Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels., DATE 2009: 1404-1409
Giorgos Vasiliadis, Michalis Polychronakis, Spyros Antonatos, Evangelos P. Markatos, Sotiris Ioannidis, Regular Expression Matching on Graphics Hardware for Intrusion Detection., RAID 2009: 265-283
Giovanni Agosta, Alessandro Barenghi, Fabrizio De Santis, Andrea Di Biagio, Gerardo Pelosi, Fast Disk Encryption through GPGPU Acceleration., PDCAT 2009: 102-109
Giovanni Beltrame, Luca Fossati, Donatella Sciuto, A real-time application design methodology for MPSoCs., DATE 2009: 767-772
Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip., DSD 2009: 383-389
Gonzalo Zarza, Diego Lugones, Daniel Franco, Emilio Luque, A Multipath Fault-Tolerant Routing Method for High-Speed Interconnection Networks., Euro-Par 2009: 1078-1088
Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Robert A. van de Geijn, Field G. Van Zee, Ernie Chan, Programming matrix algorithms-by-blocks for thread-level parallelism., ACM Trans. Math. Softw. 36(3): (2009)
Guillermo L. Taboada, Carlos Teijeiro, Juan Touriño, Basilio B. Fraguela, Ramon Doallo, José Carlos Mouriño, Damián A. Mallón, Andrés Gómez, Performance Evaluation of Unified Parallel C Collective Communications., HPCC 2009: 69-78
Guillermo L. Taboada, Juan Touriño, Ramon Doallo, Yao Lin, Jizhong Han, Efficient Java Communication Libraries over InfiniBand., HPCC 2009: 329-338
H. W. M. van Moll, Henk Corporaal, Víctor Reyes, Marleen Boonen, Fast and accurate protocol specific bus modeling using TLM 2.0., DATE 2009: 316-319
Hai Ngoc Pham, Yan Zhang, Paal E. Engelstad, Tor Skeie, Frank Eliassen, Optimal cooperative spectrum sensing in cognitive sensor networks., IWCMC 2009: 1073-1079
Hajer Chtioui, Rabie Ben Atitallah, Smaïl Niar, Jean-Luc Dekeyser, Mohamed Abid, A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC., DSD 2009: 3-10
Harris Papadakis, Paraskevi Fragopoulou, Evangelos P. Markatos, Marios D. Dikaiakos, Alexandros Labrinidis, Hash-Based Overlay Partitioning in Unstructured Peer-to-Peer Systems., Parallel Processing Letters 19(1): 57-71 (2009)
Hayden Stainsby, Manel Taboada, Emilio Luque, Towards an Agent-Based Simulation of Hospital Emergency Departments., IEEE SCC 2009: 536-539
Heiner Giefers, Marco Platzner, ARMLang: A language and compiler for programming reconfigurable mesh many-cores., IPDPS 2009: 1-8
Henk J. Sips, Dick H. J. Epema, Hai-Xiang Lin, Euro-Par 2009 Parallel Processing 15th International Euro-Par Conference Delft The Netherlands August 25-28 2009. Proceedings, Springer 2009
Holger Blume, Georgi Gaydadjiev, John Glossner, Introduction to the Special Issue on SAMOS 2007., Signal Processing Systems 57(1): 1-3 (2009)
Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich, Impact of Loop Tiling on the Controller Logic of Acceleration Engines., ASAP 2009: 161-168
I-Hsin Chung, Seetharami R. Seelam, Bernd Mohr, Jesús Labarta, Tools for scalable performance analysis on Petascale systems., IPDPS 2009: 1-3
Ian Watson, Santiago Ontañón, Special Track on Case-Based Reasoning., FLAIRS Conference 2009
Igor Loi, Federico Angiolini, Luca Benini, Synthesis of low-overhead configurable source routing tables for network interfaces., DATE 2009: 262-267
Ismo Hänninen, Jarmo Takala, Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata., SAMOS 2009: 118-127
Iván Díaz, Cristian Popi, Olivier Festor, Juan Touriño, Ramon Doallo, Ontological Configuration Management for Wireless Mesh Routers., IPOM 2009: 116-129
Ivan Beretta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, On-line task management for a reconfigurable cryptographic architecture., IPDPS 2009: 1-4
J. Rubén Titos Gil, Manuel E. Acacio, José M. García Carrasco, Speculation-based conflict resolution in hardware transactional memory., IPDPS 2009: 1-12
Javier García Blas, Florin Isaila, Jesús Carretero, Robert Latham, Robert B. Ross, Multiple-Level MPI File Write-Back and Prefetching for Blue Gene Systems., PVM/MPI 2009: 164-173
Javier Hormigo, Manuel Ortiz, Francisco J. Quiles, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata, Efficient Implementation of Carry-Save Adders in FPGAs., ASAP 2009: 207-210
Javier Navaridas, Mikel Luján, José Miguel-Alonso, Luis A. Plana, Steve Furber, Understanding the interconnection network of SpiNNaker., ICS 2009: 286-295
Jean-Yves Mignolet, Rogier Baert, Thomas J. Ashby, Prabhat Avasare, Hye-On Jang, Jae Cheol Son, MPA: Parallelizing an Application onto a Multicore Platform Made Easy., IEEE Micro 29(3): 31-39 (2009)
Jeffrey L. Ram, Yi Lu, Bioinformatics Pipeline for Identification of Binding Motifs of Flexible Protein Tethers., BIBM 2009: 9-14
Jehangir Khan, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Atika Rivenq, Driver assistance system design and its optimization for FPGA based MPSoC., SASP 2009: 62-65
Jesús Labarta, Eduard Ayguadé, Mateo Valero, BSC Vision Towards Exascale., IJHPCA 23(4): 340-343 (2009)
Jesus Garcia, Houcine Hassan, Carlos Domínguez, Alfons Crespo, Simulation Tool Incorporating a Flexible Real-Time Task Model for Mobile Robotic Systems., ESA 2009: 123-129
Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, A high-level virtual platform for early MPSoC software development., CODES+ISSS 2009: 11-20
Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich, Model-based synthesis and optimization of static multi-rate image processing algorithms., DATE 2009: 135-140
Jochen Hollmann, Per Stenström, Using Hoarding to Increase Availability in Shared File Systems., ACIS-ICIS 2009: 422-429
Jonathan Rubin, Ian Watson, A Memory-Based Approach to Two-Player Texas Hold'em., Australasian Conference on Artificial Intelligence 2009: 465-474
Jorge González-Domínguez, María J. Martín, Guillermo L. Taboada, Juan Touriño, Ramon Doallo, Andrés Gómez, A Parallel Numerical Library for UPC., Euro-Par 2009: 630-641
José L. Ayala, Arvind Sridhar, Vinod Pangracious, David Atienza, Yusuf Leblebici, Through Silicon Via-Based Grid for Thermal Control in 3D Chips., NanoNet 2009: 90-98
José Luis Ayala, David Atienza, Philip Brisk, Thermal-aware data flow analysis., DAC 2009: 613-614
José Miguel-Alonso, Javier Navaridas, Francisco Javier Ridruejo Perez, Interconnection Network Simulation Using Traces of MPI Applications., International Journal of Parallel Programming 37(2): 153-174 (2009)
Jose Antonio Pascual, Javier Navaridas, José Miguel-Alonso, Effects of Topology-Aware Allocation Policies on Scheduling Performance., JSSPP 2009: 138-156
Jose Gonzalez-Mora, Nicolas Guil, Emilio L. Zapata, Fernando De la Torre, Efficient image alignment using linear appearance models., CVPR 2009: 2230-2237
Juan A. Lorenzo, Francisco F. Rivera, Peter Tuma, Juan Carlos Pichel, On the Influence of Thread Allocation for Irregular Codes in NUMA Systems., PDCAT 2009: 146-153
Juan Gonzalez, Judit Gimenez, Jesús Labarta, Automatic detection of parallel applications computation phases., IPDPS 2009: 1-11
Judit Planas, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Hierarchical Task-Based Programming With StarSs., IJHPCA 23(3): 284-299 (2009)
Julien Lamoureux, Tony Field, Wayne Luk, Accelerating a Virtual Ecology Model with FPGAs., ASAP 2009: 67-74
Karel Bruneel, Fatma Abouelella, Dirk Stroobandt, Automatically mapping applications to a self-reconfiguring platform., DATE 2009: 964-969
Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad, A high-level debug environment for communication-centric debug., DATE 2009: 202-207
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin, Internet-Router Buffered Crossbars Based on Networks on Chip., DSD 2009: 365-374
Khaled Z. Ibrahim, François Bodin, Efficient SIMDization and data management of the Lattice QCD computation on the Cell Broadband Engine., Scientific Programming 17(1-2): 153-172 (2009)
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)., SAMOS 2009: 204-214
Koen Bertels, Nikitas J. Dimopoulos, Cristina Silvano, Stephan Wong, Embedded Computer Systems: Architectures Modeling and Simulation 9th International Workshop SAMOS 2009 Samos Greece July 20-23 2009. Proceedings, Springer 2009
Kostas Siozios, Vasilis F. Pavlidis, Dimitrios Soudris, A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs., DATE 2009: 172-177
Leandro Fiorin, Gianluca Palermo, Cristina Silvano, MPSoCs run-time monitoring through Networks-on-Chip., DATE 2009: 558-561
Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, TotalProf: a fast and accurate retargetable source code profiler., CODES+ISSS 2009: 305-314
Leonardo Fialho, Guna Santos, Angelo Duarte, Dolores Rexachs, Emilio Luque, Challenges and Issues of the Integration of RADIC into Open MPI., PVM/MPI 2009: 73-83
Li Su, Howard Bowman, Philip Barnard, Bradley P. Wyble, Process algebraic modelling of attentional capture and human electrophysiology in interactive systems., Formal Asp. Comput. 21(6): 513-539 (2009)
Lotfi Mhamdi, PBC: A Partially Buffered Crossbar Packet Switch., IEEE Trans. Computers 58(11): 1568-1581 (2009)
Lotfi Mhamdi, Mounir Hamdi, Distributed parallel scheduling algorithms for high-speed virtual output queuing switches., ISCC 2009: 944-949
Luigi Carro, Stephan Wong, Introduction to the Future of Reconfigurable Computing and Processor Architectures., SAMOS 2009: 226
Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals, Multi-level Adaptive Prefetching based on Performance Gradient Tracking, Proceedings of the The 1st JILP Data Prefetching Championship (DPC-1), Raleigh, North Carolina - February 14-18, 2009 (Best Pape
Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit Singh, Omair Taraq, Wayne Luk, Peter Jamieson, Harnessing Human Computation Cycles for the FPGA Placement Problem., ERSA 2009: 188-194
M. Jesús Zafont, Alberto Martin, Francisco D. Igual, Enrique S. Quintana-Ortí, Fast development of dense linear algebra codes on graphics processors., IPDPS 2009: 1-8
Maayan Zhitomirsky-Geffet, Dror G. Feitelson, Eitan Frachtenberg, Yair Wiseman, A unified strategy for search and result representation for an online bibliographical catalogue., Online Information Review 33(3): 511-536 (2009)
Magnus Jahre, Marius Grannæs, Lasse Natvig, A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures., HPCC 2009: 622-629
Mahmood Ahmadi, Stephan Wong, K-Stage Pipelined Bloom Filter for Packet Classification., CSE (2) 2009: 64-70
Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabeghi, Koen Bertels, Georgi Gaydadjiev, Data path Configuration Time Reduction for Run-time Reconfigurable Systems., ERSA 2009: 323-327
Mahmut T. Kandemir, Ozcan Ozturk, Sai Prashanth Muralidhara, Dynamic thread and data mapping for NoC based CMPs., DAC 2009: 852-857
Mahmut T. Kandemir, Yuanrui Zhang, Ozcan Ozturk, Adaptive prefetching for shared cache based chip multiprocessors., DATE 2009: 773-778
Mahmut T. Kandemir, Yuanrui Zhang, Sai Prashanth Muralidhara, Ozcan Ozturk, Sri Hari Krishna Narayanan, Slicing based code parallelization for minimizing inter-processor communication., CASES 2009: 87-96
Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero, Alexander V. Veidenbaum, Power-aware load balancing of large scale MPI applications., IPDPS 2009: 1-8
Manolis Maragkakis, Martin Reczko, Victor A. Simossis, Panagiotis Alexiou, Giorgos L. Papadopoulos, Theodore Dalamagas, Giorgos Giannopoulos, Georgios I. Goumas, Evangelos Koukis, Kornilios Kourtis, , DIANA-microT web server: elucidating microRNA functions through target prediction., Nucleic Acids Research 37(Web-Server-Issue): 273-276 (2009)
Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne, Introducing control-flow inclusion to support pipelining in custom instruction set extensions., SASP 2009: 114-121
Marco Branca, Lorenzo Camerini, Fabrizio Ferrandi, Pier Luca Lanzi, Christian Pilato, Donatella Sciuto, Antonino Tumeo, Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems., GECCO 2009: 1435-1442
Marco D. Santambrogio, From Reconfigurable Architectures to Self-Adaptive Autonomic Systems., CSE (2) 2009: 926-931
Marco Facchini, Trevor Carlson, Anselme Vignon, Martin Palkovic, Francky Catthoor, Wim Dehaene, Luca Benini, Paul Marchal, System-level power/performance evaluation of 3D stacked DRAMs for mobile applications., DATE 2009: 923-928
Marios Kesoulis, C. Koukourlis, J. N. Lygouras, Dimitrios Soudris, J. N. Sahalos, Design and implementation of a DDS-based multi-carrier GMSK modulator., Int. J. Communication Systems 22(8): 971-987 (2009)
Marius Enachescu, Sorin Cotofana, Arjan J. van Genderen, Dimitrios Tsamados, Adrian M. Ionescu, Can SG-FET Replace FET in Sleep Mode Circuits?, NanoNet 2009: 99-104
Mariusz Grad, Christian Plessl, Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX., ERSA 2009: 319-322
Mark Shifrin, Isaac Keslassy, Small-buffer networks., Computer Networks 53(14): 2552-2565 (2009)
Mark Silberstein, Artyom Sharov, Dan Geiger, Assaf Schuster, GridBot: execution of bags of tasks in multiple grids., SC 2009
Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann, Design optimizations to improve placeability of partial reconfiguration modules., DATE 2009: 976-981
Martin Lukasiewycz, Martin Streubühr, Michael Glaß, Christian Haubelt, Jürgen Teich, Combined system synthesis and communication architecture exploration for MPSoCs., DATE 2009: 472-477
Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Exploiting data-redundancy in reliability-aware networked embedded system design., CODES+ISSS 2009: 229-238
Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt, FlexRay schedule optimization of the static segment., CODES+ISSS 2009: 363-372
Martin Trautmann, Stylianos Mamagkakis, Bruno Bougard, Jeroen Declerck, Erik Umans, Antoine Dejonghe, Liesbet Van der Perre, Francky Catthoor, Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning., DATE 2009: 312-315
Mattias V. Eriksson, Christoph W. Kessler, Integrated Modulo Scheduling for Clustered VLIW Architectures., HiPEAC 2009: 65-79
Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania, Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip., DSD 2009: 119-126
Mercedes Marqués, Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Robert A. van de Geijn, Out-of-Core Computation of the QR Factorization on Multi-core Processors., Euro-Par 2009: 809-820
Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich, Incorporating graceful degradation into embedded system design., DATE 2009: 320-323
Michael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty, Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis., DAC 2009: 43-46
Michel Meulpolder, Johan A. Pouwelse, Dick H. J. Epema, Henk J. Sips, BarterCast: A practical approach to prevent lazy freeriding in P2P networks., IPDPS 2009: 1-8
Michele Lombardi, Michela Milano, Luca Benini, Robust non-preemptive hard real-time scheduling for clustered multicore platforms., DATE 2009: 803-808
Michele Magno, Federico Tombari, Davide Brunelli, Luigi di Stefano, Luca Benini, Multimodal Abandoned/Removed Object Detection for Low Power Video Surveillance Systems., AVSS 2009: 188-193
Michiel D'Haene, Benjamin Schrauwen, Jan Van Campenhout, Dirk Stroobandt, Accelerating Event-Driven Simulation of Spiking Neurons with Multiple Synaptic Time Constants., Neural Computation 21(4): 1068-1099 (2009)
Miguel Vazquez, Pedro Carmona-Saez, Rubén Nogales-Cadenas, Monica Chagoyen, Francisco Tirado, José María Carazo, Alberto D. Pascual-Montano, SENT: semantic features in text., Nucleic Acids Research 37(Web-Server-Issue): 153-159 (2009)
Mojtaba Sabeghi, Koen Bertels, Toward a runtime system for reconfigurable computers: A virtualization approach., DATE 2009: 1576-1579
Morten S. Rasmussen, Matthias B. Stuart, Sven Karlsson, Parallelism and Scalability in an Image Processing Application., International Journal of Parallel Programming 37(3): 306-323 (2009)
Mouad Bahi, Christine Eisenbeis, Spatial complexity of reversibly computable DAG., CASES 2009: 47-56
Mrinmoy Ghosh, Emre Özer, Simon Ford, Stuart Biles, Hsien-Hsin S. Lee, Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches., ISLPED 2009: 165-170
Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov, Ahsan Shabbir, A high-throughput area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC., ESTImedia 2009: 18-27
Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor, Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study., SAMOS 2009: 48-57
Nehir Sönmez, Tim Harris, Adrián Cristal, Osman S. Unsal, Mateo Valero, Taking the heat off transactions: Dynamic selection of pessimistic concurrency control., IPDPS 2009: 1-10
Nicolas Boichat, Nadia Khaled, Francisco J. Rincón, David Atienza, Wavelet-Based ECG Delineation on a Wearable Embedded Sensor Platform., BSN 2009: 256-261
Nikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris, Compilation Technique for Loop Overhead Minimization., DSD 2009: 419-426
Nikos Anastopoulos, Konstantinos Nikas, Georgios I. Goumas, Nectarios Koziris, Early experiences on accelerating Dijkstra's algorithm using transactional memory., IPDPS 2009: 1-8
Nikos Chrysos, Giorgos Dimitrakopoulos, Practical High-Throughput Crossbar Scheduling., IEEE Micro 29(4): 22-35 (2009)
Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki, Reactive NUCA: near-optimal block placement and replication in distributed caches., ISCA 2009: 184-195
Ogier Maitre, Nicolas Lachiche, Philippe Clauss, Laurent A. Baumes, Avelino Corma, Pierre Collet, Efficient Parallel Implementation of Evolutionary Algorithms on GPGPU Cards., Euro-Par 2009: 974-985
Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González, Reducing Soft Errors through Operand Width Aware Policies., IEEE Trans. Dependable Sec. Comput. 6(3): 217-230 (2009)
Olivier Markowitch, Angelos Bilas, Jaap-Henk Hoepman, Chris J. Mitchell, Jean-Jacques Quisquater, Information Security Theory and Practice. Smart Devices Pervasive Systems and Ubiquitous Networks Third IFIP WG 11.2 International Workshop WISTP 2009 Brussels Belgium September 1-4 2009 Proceedings, Springer 2009
Onur Derin, Alberto Ferrante, Antonio Vincenzo Taddeo, , Coordinated management of hardware and software self-adaptivity., Journal of Systems Architecture - Embedded Systems Design 55(3): 170-179 (2009)
Otilia Kocsis, Todor Ganchev, Iosif Mporas, George Papadopoulos, Nikos Fakotakis, Multi-modal System Architecture for Serious Gaming., AIAI 2009: 441-447
Ozcan Ozturk, Mahmut T. Kandemir, Using dynamic compilation for continuing execution under reduced memory availability., DATE 2009: 1373-1378
Panagiotis Afratis, Constantinos Galanakis, Euripides Sotiriades, Georgios-Grigorios Mplemenos, Grigorios Chrysos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Design and implementation of a database filter for BLAST acceleration., DATE 2009: 166-171
Paolo Roberto Grassi, Marco D. Santambrogio, Jens Hagemeyer, Christopher Pohl, Mario Porrmann, SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems., ERSA 2009: 174-180
Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé, Mapping stream programs onto heterogeneous multiprocessor systems., CASES 2009: 57-66
Pavel G. Zaykov, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev, Reconfigurable Multithreading Architectures: A Survey., SAMOS 2009: 263-274
Pepijn J. de Langen, Ben H. H. Juurlink, Limiting the number of dirty cache lines., DATE 2009: 670-675
Philip G. Potter, Wayne Luk, Peter Y. K. Cheung, Partition-based exploration for reconfigurable JPEG designs., DATE 2009: 886-889
Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas, Analysis of Performance Dependencies in NUCA-Based CMP Systems., SBAC-PAD 2009: 49-56
Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, Marco Solinas, An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload., DSD 2009: 26-33
Piero Zappi, Elisabetta Farella, Luca Benini, Hidden Markov Models Implementation for Tangible Interfaces., INTETAIN 2009: 258-263
Pieter Bellens, Josep M. Pérez, Rosa M. Badia, Jesús Labarta, Exploiting Locality on the Cell/B.E. through Bypassing., SAMOS 2009: 318-328
Quan Le Trung, Amirhosein Taherkordi, Frank Eliassen, Hai Ngoc Pham, Tor Skeie, Paal E. Engelstad, DCM-Arch: An Architecture for Data Control and Management in Wireless Sensor Networks., AINA 2009: 898-905
Quan Le Trung, Paal E. Engelstad, Vinh Pham, Tor Skeie, Amirhosein Taherkordi, Frank Eliassen, Providing internet connectivity and mobility management for MANETs., IJWIS 5(2): 239-263 (2009)
Raúl Martínez, Francisco José Alfaro, José L. Sánchez, José M. Claver, Hardware Implementation Study of the SCFQ-CA and DRR-CA Scheduling Algorithms., Euro-Par 2009: 1089-1100
Raúl Sirvent, Rosa M. Badia, Jesús Labarta, Graph-Based Task Replication for Workflow Applications., HPCC 2009: 20-28
Radu Prodan, Vlad Nae, Thomas Fahringer, Herbert Jordan, Dynamic Real-Time Resource Provisioning for Massively Multiplayer Online Games., PaCT 2009: 98-111
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors., Euro-Par 2009: 309-320
Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl, , An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems., SAMOS 2009: 227-236
Rainer Leupers, Andras Vajda, Marco Bekooij, Soonhoi Ha, Rainer Dömer, Achim Nohl, Programming MPSoC platforms: Road works ahead!, DATE 2009: 1584-1589
Rameez Rahman, David Hales, Michel Meulpolder, Vincent Heinink, Johan A. Pouwelse, Henk J. Sips, Robust vote sampling in a P2P media distribution system., IPDPS 2009: 1-8
Raul Soriano, Juan Manuel Orduña, Improving the Scalability of Communication-Aware Task Mapping Techniques., AINA Workshops 2009: 1061-1066
Rhadamés Carmona, Gabriel Rodríguez, Bernd Fröhlich, Reducing Artifacts between Adjacent Bricks in Multi-resolution Volume Rendering., ISVC (1) 2009: 644-655
Ricardo Menotti, João M. P. Cardoso, Marcio Merino Fernandes, Eduardo Marques, LALP: A Novel Language to Program Custom FPGA-Based Architectures., SBAC-PAD 2009: 3-10
Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich, Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors., SAMOS 2009: 277-288
Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich, Acceleration of Multiresolution Imaging Algorithms: A Comparative Study., ASAP 2009: 211-214
Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi, Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management., SAMOS 2009: 88-97
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture., SAMOS 2009: 78-87
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture., IPDPS 2009: 1-8
Rogier Baert, Erik Brockmeyer, Sven Wuytack, Thomas J. Ashby, Exploring parallelizations of applications for MPSoC platforms using MPA., DATE 2009: 1148-1153
Rosa Filgueira, David E. Singh, Alejandro Calderón, Jesús Carretero, CoMPI: Enhancing MPI Based Applications Performance and Scalability Using Run-Time Compression., PVM/MPI 2009: 207-218
Roya Choupani, Stephan Wong, Mehmet R. Tolun, Multiple Description Scalable Coding for Video Transmission over Unreliable Networks., SAMOS 2009: 58-67
Rubén Nogales-Cadenas, Pedro Carmona-Saez, Miguel Vazquez, Cesar Vicente, Xiaoyuan Yang, Francisco Tirado, José María Carazo, Alberto D. Pascual-Montano, GeneCodis: interpreting gene lists through enrichment analysis and integration of diverse biological information., Nucleic Acids Research 37(Web-Server-Issue): 317-322 (2009)
Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería, On reducing misspeculations in a pipelined scheduler., IPDPS 2009: 1-12
Rudolf Eigenmann, Eduard Ayguadé, Guest Editors' Introduction., International Journal of Parallel Programming 37(3): 247-249 (2009)
S. M. A. Abbas, Johan A. Pouwelse, Dick H. J. Epema, Henk J. Sips, A Gossip-Based Distributed Social Networking System., WETICE 2009: 93-98
Salvador Coll, Francisco J. Mora, José Duato, Fabrizio Petrini, Efficient and Scalable Hardware-Based Multicast in Fat-Tree Networks., IEEE Trans. Parallel Distrib. Syst. 20(9): 1285-1298 (2009)
Salvador Petit Marti, Julio Sahuquillo Borrás, Pedro Lopez Rodriguez, Rafael Ubal Tena, Jose Duato Marin, A Complexity-Effective Out-of-Order Retirement Microarchitecture., IEEE Trans. Computers 58(12): 1626-1639 (2009)
Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López, José Duato, An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions., DSD 2009: 635-642
Samir Ammenouche, Sid Ahmed Ali Touati, William Jalby, On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors., HPCC 2009: 196-205
Sascha Uhrig, Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC., SAMOS 2009: 68-77
Sergio Barrachina, Oliver Bender, Francisco Casacuberta, Jorge Civera, Elsa Cubel, Shahram Khadivi, Antonio L. Lagarda, Hermann Ney, Jesús Tomás, Enrique Vidal, Juan Miguel Vilar, Statistical Approaches to Computer-Assisted Translation., Computational Linguistics 35(1): 3-28 (2009)
Sergio Saponara, Pierluigi Nuzzo, Claudio Nani, Geert Van der Plas, Luca Fanucci, Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters., IEICE Transactions 92-C(6): 843-851 (2009)
Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli, Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis., DATE 2009: 616-621
Shengyan Hong, Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk, Process variation aware thread mapping for Chip Multiprocessors., DATE 2009: 821-826
Sid Ahmed Ali Touati, Zsolt Mathe, Periodic register saturation in innermost loops., Parallel Computing 35(4): 239-254 (2009)
Silvia Rueda, Eri Giannaka, Pedro Morillo, Christos Bouras, Juan M. Orduña, Managing Objects in P2P DVEs., PDPTA 2009: 783-789
Simone Campanoni, Martino Sykora, Giovanni Agosta, Stefano Crespi-Reghizzi, Dynamic Look Ahead Compilation: A Technique to Hide JIT Compilation Latencies in Multicore Environment., CC 2009: 220-235
Simone Pellegrini, Jie Wang, Thomas Fahringer, Hans Moritsch, Optimizing MPI Runtime Parameter Settings by Using Machine Learning., PVM/MPI 2009: 196-206
Sonal Kumar, Daya Gupta, V. K. Panchal, Shashi Kumar, Enabling web services for Classification of Satellite Image., SWWS 2009: 89-94
Sonia Gonzalez-Navarro, Juan López, Angeles G. Navarro, Emilio L. Zapata, Analytical Model of Patching and Load Sharing in a Distributed VoD System., PDPTA 2009: 357-363
Sotiria Fytraki, Dionisios N. Pnevmatikatos, ReSim a trace-driven reconfigurable ILP processor simulator., DATE 2009: 536-541
Stefan Müller, Manuel Schreger, Marten Kabutz, Matthias Alles, Frank Kienle, Norbert Wehn, A novel LDPC decoder for DVB-S2 IP., DATE 2009: 1308-1313
Stefan Wildermann, Tobias Ziermann, Jürgen Teich, Self-organizing Bandwidth Sharing in Priority-Based Medium Access., SASO 2009: 144-153
Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Spatio-temporal memory streaming., ISCA 2009: 69-80
Sutirtha Sanyal, Sourav Roy, Adrián Cristal, Osman S. Unsal, Mateo Valero, Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory., HPCC 2009: 171-179
Teemu Pitkänen, Jarno K. Tanskanen, Risto Mäkinen, Jarmo Takala, Parallel Memory Architecture for Application-Specific Instruction-Set Processors., Signal Processing Systems 57(1): 21-32 (2009)
Tero Arpinen, Tapio Koskinen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen, Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA., DATE 2009: 244-249
Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam, A DP-network for optimal dynamic routing in network-on-chip., CODES+ISSS 2009: 119-128
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon, Way Stealing: cache-assisted automatic instruction set extensions., DAC 2009: 31-36
Thomas Fahringer, Alexandru Iosup, Marian Bubak, Matei Ripeanu, Xian-He Sun, Hong Linh Truong, Introduction., Euro-Par 2009: 95-96
Tobias Ziermann, Stefan Wildermann, Jürgen Teich, CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates., DATE 2009: 1088-1093
Toktam Taghavi, Andy D. Pimentel, Mark Thompson, System-level MP-SoC design space exploration using tree visualization., ESTImedia 2009: 80-88
Toktam Taghavi, Mark Thompson, Andy D. Pimentel, Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration., SAMOS 2009: 149-160
Uwe Brinkschulte, Alexander von Renteln, Analyzing the Behavior of an Artificial Hormone System for Task Allocation., ATC 2009: 47-61
Uwe Brinkschulte, Daniel Lohn, Mathias Pacher, Towards a Statistical Model of a Microprocessor's Throughput by Analyzing Pipeline Stalls., SEUS 2009: 82-90
Uwe Brinkschulte, Mathias Pacher, A Theoretical Examination of a Self-Adaptation Approach to Improve the Real-Time Capabilities in Multi-Threaded Microprocessors., SASO 2009: 136-143
Vanderlei Bonato, Eduardo Marques, George A. Constantinides, A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots., Signal Processing Systems 56(1): 41-50 (2009)
Vasileios Karakasis, Georgios I. Goumas, Nectarios Koziris, Exploring the effect of block shapes on the performance of sparse kernels., IPDPS 2009: 1-8
Vasileios Karakasis, Georgios I. Goumas, Nectarios Koziris, A Comparative Study of Blocking Storage Methods for Sparse Matrices on Multicore Architectures., CSE (1) 2009: 247-256
Vicente Chirivella, Rosa Alcover, Jose Flich, José Duato, Dependability Analysis of a Fault-Tolerant Network Reconfiguring Strategy., Euro-Par 2009: 1040-1051
Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser, Traceability Mechanism for Error Localization in Model Transformation., ICSOFT (1) 2009: 66-73
Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Gianmarco De Francisci Morales, An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures., DSD 2009: 643-650
Vincenzo Rana, Srinivasan Murali, David Atienza, Marco D. Santambrogio, Luca Benini, Donatella Sciuto, Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems., CODES+ISSS 2009: 325-334
Waheed Iqbal, Matthew Dailey, David Carrera, SLA-Driven Adaptive Resource Management for Web Applications on a Heterogeneous Compute Cloud., CloudCom 2009: 243-253
Yang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal, Exploring trade-offs between performance and resource requirements for synchronous dataflow graphs., ESTImedia 2009: 96-105
Yuan He, Morteza Biglari-Abhari, Zoran A. Salcic, Rapid Energy Estimation for Embedded Soft-core Microprocessors., ESA 2009: 133-139
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz Ergin, , Reducing parity generation latency through input value aware circuits., ACM Great Lakes Symposium on VLSI 2009: 109-112
Yusuf Osmanlioglu, Y. Sinan Hanay, Oguz Ergin, Modifying the Data-Holding Components of the Microprocessors for Energy Efficiency., Journal of Circuits Systems and Computers 18(6): 1093-1117 (2009)
Álvaro Vazquez, Elisardo Antelo, A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding, ARITH '09: Proceedings of the 2009 19th IEEE Symposium on Computer Arithmetic - Volume 00 , Volume 00, IEEE Computer Society, June 2009
Álvaro Vazquez, Julio Villalba, Elisardo Antelo, Computation of Decimal Transcendental Functions Using the CORDIC Algorithm, ARITH '09: Proceedings of the 2009 19th IEEE Symposium on Computer Arithmetic - Volume 00 , Volume 00, IEEE Computer Society, June 2009
Åshild Grønstad Solheim, Olav Lysne, Tor Skeie, Thomas Sødring, Sven-Arne Reinemo, A framework for routing and resource allocation in network virtualization., HiPC 2009: 129-139
A. Calderón, F. García-Carballeira, L. M. Sánchez, J. D. García, J. Fernandez, Fault tolerant file models for parallel file systems: introducing distribution patterns for every file, The Journal of Supercomputing , Volume 47 Issue 3, Kluwer Academic Publishers, March 2009
A. Heindl, G. Pokam, An Analytic Model for Optimistic STM with Lazy Locking., ASMTA 2009: 339-353
A. Heindl, G. Pokam, An Analytic Framework for Performance Modeling of Software Transactional Memory, Computer Networks, 53(8), 2009
A. Heindl, G. Pokam, Modeling Software Transactional Memory with AnyLogic, SIMUTools 2009
A. Heindl, G. Pokam, A.-R. Adl-Tabatabai, An Analytic Model of Optimistic Software Transactional Memory, ISPASS 2009
A. J. van de Goor, Said Hamdioui, Georgi Nedeltchev Gaydadjiev, Zaid Al-Ars, New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults., Asian Test Symposium 2009: 391-396
A. W. Azman, Abbas Bigdeli, Morteza Biglari-Abhari, Y. M. Mustafah, Brian C. Lovell, Exploiting Bayesian Belief Network for Adaptive IP-Reuse Decision., DICTA 2009: 66-73
Adrian Prantl, Jens Knoop, Raimund Kirner, Albrecht Kadlec, Markus Schordan, From Trusted Annotations to Verified Knowledge., WCET 2009
Adrian Tineo, Francisco Corbera, Angeles G. Navarro, Rafael Asenjo, Emilio L. Zapata, On the Automatic Detection of Heap-Induced Data Dependencies with Interprocedural Shape Analysis., ICPP Workshops 2009: 378-385
Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal, Performance evaluation of concurrently executing parallel applications on multi-processor systems., ICSAMOS 2009: 100-107
Ajay K. Verma, Philip Brisk, Paolo Ienne, Iterative layering: Optimizing arithmetic circuits by structuring the information flow., ICCAD 2009: 797-804
Ajay K. Verma, Philip Brisk, Paolo Ienne, Challenges in Automatic Optimization of Arithmetic Circuits, ARITH '09: Proceedings of the 2009 19th IEEE Symposium on Computer Arithmetic - Volume 00 , Volume 00, IEEE Computer Society, June 2009
Akash Kumar, Analysis, Design and Management of Multimedia Multiprocessor Systems, PhD Thesis, Eindhoven University of Technology
Alastair C. Murray, Richard V. Bennett, Björn Franke, Nigel Topham, Code transformation and instruction set extension, Transactions on Embedded Computing Systems (TECS) , Volume 8 Issue 4, ACM, July 2009
Alastair F. Donaldson, Vector Symmetry Reduction., Electr. Notes Theor. Comput. Sci. 250(2): 3-18 (2009)
Alastair F. Donaldson, Alice Miller, On the constructive orbit problem., Ann. Math. Artif. Intell. 57(1): 1-35 (2009)
Alastair F. Donaldson, Alice Miller, David Parker, Language-Level Symmetry Reduction for Probabilistic Model Checking., QEST 2009: 289-298
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung, Area estimation and optimisation of FPGA routing fabrics., FPL 2009: 256-261
Albert Cohen, A Stochastic Approach to Coarsening of Cellular Networks., Multiscale Modeling & Simulation 8(2): 463-480 (2009)
Albert Hartono, Muthu Manikandan Baskaran, Cédric Bastoul, Albert Cohen, Sriram Krishnamoorthy, Boyana Norris, J. Ramanujam, P. Sadayappan, Parametric multi-level tiling of imperfectly nested loops., ICS 2009: 147-157
Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García, Distance-aware round-robin mapping for large NUCA caches., HiPC 2009: 79-88
Alejandro Duran, Xavier Teruel, Roger Ferrer, Xavier Martorell, Eduard Ayguadé, Barcelona OpenMP Tasks Suite: A Set of Benchmarks Targeting the Exploitation of Task Parallelism in OpenMP., ICPP 2009: 124-131
Alejandro Martínez, Pedro J. García, Francisco J. Alfaro, José L. Sánchez, José Flich, Francisco J. Quiles, José Duato, A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination, IEEE Transactions on Parallel and Distributed Systems , Volume 20 Issue 1, IEEE Press, January 2009
Alejandro Rico, Alex Ramirez, Mateo Valero, Available task-level parallelism on the Cell BE, Scientific Programming , Volume 17 Issue 1-2, IOS Press, January 2009
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato, An hybrid eDRAM/SRAM macrocell to implement first-level data caches., MICRO 2009: 213-221
Ales Friedl, Sven Ubik, Alexandros Kapravelos, Michalis Polychronakis, Evangelos P. Markatos, Realistic Passive Packet Loss Measurement for High-Speed Networks., TMA 2009: 1-7
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paol, Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs., TRETS 2(2): (2009)
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj, 3D configuration caching for 2D FPGAs., FPGA 2009: 286
Alessandro G. Di Nuovo, Santo Di Nuovo, Serafino Buono, Vincenzo Catania, Feedforward artificial neural network to estimate iq of mental retarded people from different psychometric instruments., IJCNN 2009: 690-696
Alessandro G. Di Nuovo, Vincenzo Catania, Linguistic Modifiers to Improve the Accuracy-Interpretability Trade-Off in Multi-Objective Genetic Design of Fuzzy Rule Based Classifier Systems., ISDA 2009: 128-133
Alessio Bonfietti, Michele Lombardi, Michela Milano, Luca Benini, Throughput Constraint for Synchronous Data Flow Graphs., CPAIOR 2009: 26-40
Alexander S. van Amesfoort, Ana Lucia Varbanescu, Henk J. Sips, Rob van Nieuwpoort, Evaluating multi-core platforms for HPC data-intensive kernels., Conf. Computing Frontiers 2009: 207-216
Alexander Sayenko, Olli Alanen, Henrik Martikainen, Vitaliy Tykhomyrov, Alexander Puchko, Timo Hämäläinen, WINSE: WiMAX NS-2 extension., SimuTools 2009: 46
Alexandre Otto Strube, Dolores Rexachs, Emilio Luque, Software Probes: A Method for Quickly Characterizing Applications' Performance on Heterogeneous Environments., ICPP Workshops 2009: 262-269
Alexandros Bartzas, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, Fragkiskos Ieromnimon, Nikolaos S. Voros, Dynamic Data Type Optimization and Memory Assignment Methodologies., PATMOS 2009: 175-185
Alexandros Bartzas, Lazaros Papadopoulos, Dimitrios Soudris, A system-level design methodology for application-specific networks-on-chip., J. Embedded Computing 3(3): 167-177 (2009)
Alexandros Bartzas, Miguel Peón Quirós, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Direct memory access usage optimization in network applications for reduced memory latency and energy consumption., J. Embedded Computing 3(3): 241-254 (2009)
Alexey Rodriguez Yakushev, Johan Jeuring, Enumerating Well-Typed Terms Generically., AAIP 2009: 93-116
Alexey Rodriguez Yakushev, Stefan Holdermans, Andres Löh, Johan Jeuring, Generic programming with fixed points for mutually recursive datatypes., ICFP 2009: 233-244
Ali Azarian, Mahmood Ahmadi, Reconfigurable computing architecture survey and introduction, 2nd IEEE International Conference on Computer Science and Information Technology
Ali Miri, Luis Orozco-Barbosa, Editorial., Ad Hoc & Sensor Wireless Networks 7(1-2): 1-2 (2009)
Alin Suciu, Tudor Carean, André Seznec, Kinga Marton, Parallel HAVEGE., PPAM (2) 2009: 145-154
Alvaro Wong, Dolores Rexachs, Emilio Luque, Parallel application signature., CLUSTER 2009: 1-4
Amine Marref, Guillem Bernat, Predicated Worst-Case Execution-Time Analysis., Ada-Europe 2009: 134-148
Amir-Mohammad Rahmani, I. Kamali, Pejman Lotfi-Kamran, Ali Afzali-Kusha, Saeed Safari, Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips., VLSI Design 2009: 157-162
Amit Golander, Shlomo Weiss, Reexecution and Selective Reuse in Checkpoint Processors., T. HiPEAC 2: 242-268 (2009)
Amit Verma, Ajay K. Verma, Philip Brisk, Paolo Ienne, Hybrid LZA: a near optimal implementation of the leading zero anticipator, ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, IEEE Press, January 2009
Amund Kvalbein, Audun Fosselie Hansen, Tarik Cicic, Stein Gjessing, Olav Lysne, Multiple routing configurations for fast IP network recovery., IEEE/ACM Trans. Netw. 17(2): 473-486 (2009)
Ana Lucia Varbanescu, Henk J. Sips, Kenneth A. Ross, Qiang Liu, Apostol Natsev, John R. Smith, Lurng-Kuo Liu, Evaluating application mapping scenarios on the Cell/B.E., Concurrency and Computation: Practice and Experience 21(1): 85-100 (2009)
Anastasios Gounaris, Jim Smith, Norman W. Paton, Rizos Sakellariou, Alvaro A. A. Fernandes, Paul Watson, Adaptive workload allocation in query processing in autonomous heterogeneous environments., Distributed and Parallel Databases 25(3): 125-164 (2009)
Anastassia Loukina, Greg Kochanski, Chilin Shih, Elinor Keane, Ian Watson, Rhythm measures with language-independent segmentation., INTERSPEECH 2009: 1531-1534
Anastassios Nanos, Nectarios Koziris, MyriXen: Message Passing in Xen Virtual Machines over Myrinet and Ethernet., Euro-Par Workshops 2009: 395-403
André C. Santos, Luís Tarrataca, João M. P. Cardoso, An Analysis of Navigation Algorithms for Smartphones Using J2ME., MOBILWARE 2009: 266-279
André C. Santos, Luís Tarrataca, João M. P. Cardoso, Diogo R. Ferreira, Pedro C. Diniz, Paulo Chainho, Context Inference for Mobile Applications in the UPCASE Project., MOBILWARE 2009: 352-365
André Seznec, Joel S. Emer, Michael F. P. O'Boyle, Margaret Martonosi, Theo Ungerer, High Performance Embedded Architectures and Compilers Fourth International Conference HiPEAC 2009 Paphos Cyprus January 25-28 2009. Proceedings, Springer 2009
Andréea Chis, Eric Fleury, Antoine Fraboulet, An optimized MAC layer to physical device mapping methodology., Mobility Conference 2009
Andrea Alimonda, Salvatore Carta, Andrea Acquaviva, Alessandro Pisano, Luca Benini, A Feedback-Based Approach to DVFS in Data-Flow Applications., IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1691-1704 (2009)
Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis, Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors, IEEE Transactions on Computers, vol. 58, no. 12, pp. 1682-1694, December 2009.
Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Danilo Ravotto, Matteo Sonza Reorda, Test Program Generation for Communication Peripherals in Processor-Based Systems-on-Chip, IEEE Design & Test of Computers Magazine, vol. 26, no. 2, pp. 52-63, March-April 2009.
Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis, Ishwar Parulkar, Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors, IEEE European Test Symposium (ETS 2009), Sevilla, Spain, May 2009.
Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor Stefanov, Daniel D. Gajski, Jürgen Teich, Electronic System-Level Synthesis Methodologies., IEEE Trans. on CAD of Integrated Circuits and Systems 28(10): 1517-1530 (2009)
Andreas Hansson, Benny Akesson, Jef van Meerbergen, Multi-processor programming in the embedded system curriculum, SIGBED Review , Volume 6 Issue 1, ACM, January 2009
Andreas Hansson, Kees Goossens, An on-chip interconnect and protocol stack for multiple communication paradigms and programming models, CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, ACM, October 2009
Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken, CoMPSoC: A template for composable and predictable multi-processor system on chips., ACM Trans. Design Autom. Electr. Syst. 13(1): (2009)
Andres Mejia, Maurizio Palesi, Jose Flich, Shashi Kumar, Pedro López, Rickard Holsmark, José Duato, Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs., IEEE Trans. VLSI Syst. 17(3): 356-369 (2009)
Andres Mejia, Maurizio Palesi, José Flich, Shashi Kumar, Pedro Lopez, Rickard Holsmark, José Duato, Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs, IEEE Transactions on on Very Large Scale Integration Systems
Andrey Brito, Christof Fetzer, Pascal Felber, Minimizing Latency in Fault-Tolerant Distributed Stream Processing Systems., ICDCS 2009: 173-182
Andrey Brito, Christof Fetzer, Pascal Felber, Multithreading-Enabled Active Replication for Event Stream Processing Operators., SRDS 2009: 22-31
Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures., IEEE Trans. VLSI Syst. 17(1): 151-155 (2009)
Ankur Narang, Karthik Swaminathan, Prashant Agrawal, Performance optimizations for distributed real-time text indexing., HiPC 2009: 398-407
Anna Beletska, Denis Barthou, Wlodzimierz Bielecki, Albert Cohen, Computing the Transitive Closure of a Union of Affine Integer Tuple Relations., COCOA 2009: 98-109
Anna Beletska, Wlodzimierz Bielecki, Albert Cohen, Marek Palkowski, Synchronization-Free Automatic Parallelization: Beyond Affine Iteration-Space Slicing., LCPC 2009: 233-246
Anna Beletska, Wlodzimierz Bielecki, Albert Cohen, Marek Palkowski, Krzysztof Siedlecki, Coarse-Grained Loop Parallelization: Iteration Space Slicing vs Affine Transformations., ISPDC 2009: 73-80
Anson H. T. Tse, David B. Thomas, Wayne Luk, Accelerating Quadrature Methods for Option Valuation., FCCM 2009: 29-36
Anthony Danalis, Lori L. Pollock, D. Martin Swany, John Cavazos, MPI-aware compiler optimizations for improving communication-computation overlap., ICS 2009: 316-325
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset, Long-range dependence and on-chip processor traffic, Microprocessors & Microsystems , Volume 33 Issue 1, Elsevier Science Publishers B. V., February 2009
Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, HW/SW methodologies for synchronization in FPGA multiprocessors., FPGA 2009: 265-268
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform, ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, IEEE Press, January 2009
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Åshild Grønstad Solheim, Thomas Sødring, Tor Skeie, A new distributed management mechanism for ASI based networks., Computer Communications 32(2): 294-304 (2009)
Antonio Roldao Lopes, Amir Shahzad, George A. Constantinides, Eric C. Kerrigan, More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control., FCCM 2009: 209-216
Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Integrated verification approach during ADL-driven processor design., Microelectronics Journal 40(7): 1111-1123 (2009)
Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors., ACM Trans. Embedded Comput. Syst. 8(2): (2009)
Arnab Banerjee, Pascal T. Wolkotte, Robert D. Mullins, Simon W. Moore, Gerard J. M. Smit, An Energy and Performance Exploration of Network-on-Chip Architectures., IEEE Trans. VLSI Syst. 17(3): 319-329 (2009)
Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez, Parallel H.264 Decoding on an Embedded Multicore Processor., HiPEAC 2009: 404-418
Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne, FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation., FCCM 2009: 267-270
Asadollah Shahbahrami, Ben Juurlink, Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices, APPT '09: Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies, Springer-Verlag, August 2009
Asadollah Shahbahrami, Mahmood Ahmadi, Stephan Wong, Koen Bertels, A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements., ReConFig 2009: 344-349
Asaf Baron, Ran Ginosar, Isaac Keslassy, The Capacity Allocation Paradox., INFOCOM 2009: 1359-1367
Ashoka Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Springer-Verlag, January 2009
Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung, Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep., ARC 2009: 133-144
Athanasia Asiki, Dimitrios Tsoumakos, Nectarios Koziris, An adaptive online system for efficient processing of hierarchical data., HPDC 2009: 71-80
Athanasia Asiki, Katerina Doka, Ioannis Konstantinou, Antonis Zissimos, Dimitrios Tsoumakos, Nectarios Koziris, Panayotis Tsanakas, A grid middleware for data management exploiting peer-to-peer techniques., Future Generation Comp. Syst. 25(4): 426-435 (2009)
Avi Yadgar, Orna Grumberg, Assaf Schuster, Hybrid BDD and All-SAT Method for Model Checking., Languages: From Formal to Natural 2009: 228-244
Aylin Koca, Mathias Funk, Evangelos Karapanos, Anne Rozinat, Wil M. P. van der Aalst, Henk Corporaal, Jean-Bernard Martens, Piet van der Putten, A. J. M. M. Weijters, Aarnout Brombacher, Soft reliability: an interdisciplinary approach with a user-system focus., Quality and Reliability Eng. Int. 25(1): 3-20 (2009)
Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero, Studying New Ways for Improving Adaptive History Length Branch Predictors, ISHPC '02: Proceedings of the 4th International Symposium on High Performance Computing, Springer-Verlag, May 2009
Basilio B. Fraguela, Yevgen Voronenko, Markus Püschel, Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling, 18th Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT'09). pp. 271-280
Benny Akesson, Liesbeth Steffens, Kees Goossens, Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration, RTCSA '09: Proceedings of the 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications - Volume 00 , Volume 00, IEEE Computer Society, August 2009
Benoit Boissinot, Alain Darte, Fabrice Rastello, Benoît Dupont de Dinechin, Christophe Guillon, Revisiting Out-of-SSA Translation for Correctness Code Quality and Efficiency., CGO 2009: 114-125
Bin Lin, Isaac Keslassy, The interleaved matching switch architecture., IEEE Transactions on Communications 57(12): 3732-3742 (2009)
Biswajit Mishra, Bashir M. Al-Hashimi, Mark Zwolinski, Variation resilient adaptive controller for subthreshold circuits., DATE 2009: 142-147
Boubacar Diouf, Ozcan Ozturk, Albert Cohen, Optimizing Local Memory Allocation and Assignment through a Decoupled Approach., LCPC 2009: 408-415
Bratin Saha, Xiaocheng Zhou, Hu Chen, Ying Gao, Shoumeng Yan, Mohan Rajagopalan, Jesse Fang, Peinan Zhang, Ronny Ronen, Avi Mendelson, Programming model for a heterogeneous x86 platform., PLDI 2009: 431-440
Brian T. Gold, Babak Falsafi, James C. Hoe, Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors., PRDC 2009: 195-201
C. Svenson, D. Kesler, R. Kumar, G. Pokam, MPreplay: Architecture Support for Deterministic Replay of Message Passing Programs on Message Passing Many-core Processors, UIUC CRHC Technical Report 2009
Carlo Brandolese, William Fornaciari, A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes., DSD 2009: 857-864
Carlos Cortes, Yi Lu, Build a Promoter Motif Database for System Biology Research., CAINE 2009: 231-236
Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero, ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs., PACT 2009: 203-213
Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero, CPU Accounting in CMP Processors, IEEE Computer Architecture Letters , Volume 8 Issue 1, IEEE Computer Society, January 2009
Carmela Comito, Anastasios Gounaris, Rizos Sakellariou, Domenico Talia, A service-oriented system for distributed data querying and integration on Grids., Future Generation Comp. Syst. 25(5): 511-524 (2009)
Carmen Martínez, Ramón Beivide, Ernst M. Gabidulin, Perfect codes from Cayley graphs over Lipschitz integers., IEEE Transactions on Information Theory 55(8): 3552-3562 (2009)
Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz, Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router., SBCCI 2009
Charalambos Constantinou, Symeon Retalis, George Papadopoulos, Vrasidas Charalambos, Combining Streaming Media and Collaborative Elements to Support Lifelong Learning., Intelligent Collaborative e-Learning Systems and Applications 2009: 19-36
Chinmay Eishan Kulkarni, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions., PPOPP 2009: 307-308
Chris R. Jesshope, Mike Lankamp, Li Zhang, The implementation of an SVP many-core processor and the evaluation of its memory architecture., SIGARCH Computer Architecture News 37(2): 38-45 (2009)
Chris R. Jesshope, Mike Lankamp, Li Zhang, Evaluating CMPs and Their Memory Architecture., ARCS 2009: 246-257
Christian Ostlund, Karlheinz Kautz, Lars Svensson, Towards adapting authentic learning for formal work-integrated e-learning, DESRIST '09: Proceedings of the 4th International Conference on Design Science Research in Information Systems and Technology, ACM, May 2009
Christine Rochange, Pascal Sainrat, A Context-Parameterized Model for Static Analysis of Execution Times., T. HiPEAC 2: 222-241 (2009)
Christoforos Kachris, Stephan Wong, Stamatis Vassiliadis, Design and performance evaluation of an adaptive FPGA for network applications, Microelectronics Journal , Volume 40 Issue 7, Elsevier Science Publishers B. V., July 2009
Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Grigori Fursin, Michael F. P. O'Boyle, Portable compiler optimisation across embedded programs and microarchitectures using machine learning., MICRO 2009: 78-88
Christos Baloukas, José Luis Risco-Martín, David Atienza, Christophe Poucet, Lazaros Papadopoulos, Stylianos Mamagkakis, Dimitrios Soudris, José Ignacio Hidalgo, Francky Catthoor,, Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems., Journal of Systems and Software 82(4): 590-602 (2009)
Christos D. Antonopoulos, Filip Blagojevic, Andrey N. Chernikov, Nikos Chrisochoides, Dimitrios S. Nikolopoulos, A multigrain Delaunay mesh generation method for multicore SMT-based architectures., J. Parallel Distrib. Comput. 69(7): 589-600 (2009)
Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung, Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs., TRETS 1(4): (2009)
Chun Hok Ho, Chi Wai Yu, Philip Leong, Wayne Luk, Steven J. E. Wilton, Floating-Point FPGA: Architecture and Modeling., IEEE Trans. VLSI Syst. 17(12): 1709-1718 (2009)
Chun Zhu, Weihua Sheng, Multi-sensor fusion for human daily activity recognition in robot-assisted living., HRI 2009: 303-304
Chun Zhu, Weihua Sheng, Online hand gesture recognition using neural network based segmentation., IROS 2009: 2415-2420
Cor Meenderinck, Arnaldo Azevedo, Ben Juurlink, Mauricio Alvarez Mesa, Alex Ramirez, Parallel Scalability of Video Decoders, Journal of Signal Processing Systems , Volume 57 Issue 2, Kluwer Academic Publishers, November 2009
Cor Meenderinck, Ben Juurlink, (When) Will CMPs Hit the Power Wall?, Euro-Par 2008 Workshops - Parallel Processing, Springer-Verlag, April 2009
Cor Meenderinck, Ben Juurlink, Specialization of the Cell SPE for Media Applications, ASAP '09: Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors - Volume 00 , Volume 00, IEEE Computer Society, July 2009
Cosmin E. Oancea, Alan Mycroft, Tim Harris, A lightweight in-place implementation for software thread-level speculation., SPAA 2009: 223-232
Craig Moore, Harald Devos, Dirk Stroobandt, Optimizing the FPGA memory design for a Sobel edge detector, The International Conference on Engineering of Reconfigurable Systems and Algorithms, Proceedings. CSREA Press
Cristiana Bolchini, Carlo Curino, Elisa Quintarelli, Fabio A. Schreiber, Letizia Tanca, Context information for knowledge reshaping., Int. J. Web Eng. Technol. 5(1): 88-103 (2009)
Cristiana Bolchini, Fabrizio Castro, Antonio Miele, A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems., DFT 2009: 173-181
Cristiana Bolchini, Yong-Bin Kim, Guest Editorial., J. Electronic Testing 25(1): 9-10 (2009)
D. Sánchez, M. A. Vila, L. Cerda, J. M. Serrano, Association rules applied to credit card fraud detection, Expert Systems with Applications: An International Journal , Volume 36 Issue 2, Pergamon Press, Inc., March 2009
D. Suárez, T. Monreal, F. Vallejo, R. Beivide, V. Viñals, Light NUCA: A Proposal for Bridging the Inter-Cache Latency Gap., In Proc. of12th Design, Automation & Test in Europe Conference & Exhibition (DATE'09), pp. 530-535. Acropolis, Nice, France. Ap
Damián A. Mallón, Guillermo L. Taboada, Juan Touriño, Ramon Doallo, NPB-MPJ: NAS Parallel Benchmarks Implementation for Message-Passing in Java., PDP 2009: 181-190
Daniel Cabrera, Xavier Martorell, Georgi Gaydadjiev, Eduard Ayguadé, Daniel Jiménez-González, OpenMP extensions for FPGA accelerators., ICSAMOS 2009: 17-24
Daniel Cordes, Heiko Falk, Peter Marwedel, A Fast and Precise Static Loop Analysis Based on Abstract Interpretation Program Slicing and Polytope Models., CGO 2009: 136-146
Daniel Jones, Nigel P. Topham, High Speed CPU Simulation Using LTU Dynamic Binary Translation., HiPEAC 2009: 50-64
Daniel Sánchez, Miguel Delgado, María-Amparo Vila, Fuzzy Quantification Using Restriction Levels, WILF '09: Proceedings of the 8th International Workshop on Fuzzy Logic and Applications, Springer-Verlag, June 2009
Daniel Sanchez, Juan L. Aragon, Jose M. Garcia, Extending SRT for parallel applications in tiled-CMP architectures, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Luca Benini, Georgi Gaydadjiev, Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture., NOCS 2009: 244-249
Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi, Luca Benini, Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip., ACM Great Lakes Symposium on VLSI 2009: 125-128
Dara Rahmati, Srinivasan Murali, Luca Benini, Federico Angiolini, Giovanni De Micheli, Hamid Sarbazi-Azad, A method for calculating hard QoS guarantees for Networks-on-Chip., ICCAD 2009: 579-586
Dario Cozzi, Claudia Farè, Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices., ACM Great Lakes Symposium on VLSI 2009: 421-424
David Atienza, Emilio Martinez, Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip., ISVLSI 2009: 187-192
David B. Thomas, Lee Howes, Wayne Luk, A comparison of CPUs GPUs FPGAs and massively parallel processor arrays for random number generation., FPGA 2009: 63-72
David Bernstein, Erik Ludvigson, Networking Challenges and Resultant Approaches for Large Scale Cloud Construction., GPC Workshops 2009: 136-142
David E. Singh, Florin Isaila, Juan C. Pichel, Jesús Carretero, A collective I/O implementation based on inspector---executor paradigm, The Journal of Supercomputing , Volume 47 Issue 3, Kluwer Academic Publishers, March 2009
David Kammler, Junqing Guan, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations., SSIRI 2009: 309-314
David Novo, Robert Fasthuber, Praveen Raghavan, André Bourdoux, Min Li, Liesbet Van der Perre, Francky Catthoor, Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS., SiPS 2009: 151-156
David Thomas, Wayne Luk, FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks., FCCM 2009: 45-52
Davide Brunelli, D. Dondi, A. Bertacchini, Luca Larcher, Paolo Pavan, Luca Benini, Photovoltaic scavenging systems: Modeling and optimization., Microelectronics Journal 40(9): 1337-1344 (2009)
Debora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, The Need for Reconfigurable Routers in Networks-on-Chip., ARC 2009: 275-280
Demid Borodin, B. H. Juurlink, Said Hamdioui, Stamatis Vassiliadis, Instruction-Level Fault Tolerance Configurability, Journal of Signal Processing Systems , Volume 57 Issue 1, Kluwer Academic Publishers, October 2009
Diana Bautista, Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Duato, Dynamic task set partitioning based on balancing memory requirements to reduce power consumption., ICS 2009: 513-514
Diego Andrade, Basilio B. Fraguela, James C. Brodman, David A. Padua, Task-Parallel versus Data-Parallel Library-Based Programming in Multicore Systems., PDP 2009: 101-110
Diego Andrade, Basilio B. Fraguela, Ramón Doallo, Static Prediction of Worst-Case Data Cache Performance in the Absence of Base Address Information, RTAS '09: Proceedings of the 2009 15th IEEE Real-Time and Embedded Technology and Applications Symposium - Volume 00 , Volume 00, IEEE Computer Society, April 2009
Diego Lugones, Daniel Franco, Dolores Rexachs, Juan C. Moure, Emilio Luque, Eduardo Argollo, Ayose Falcón, Daniel Ortega, Paolo Faraboschi, High-speed network modeling for full system simulation., IISWC 2009: 24-33
Diego Lugones, Daniel Franco, Eduardo Argollo, Emilio Luque, Models for high-speed interconnection networks performance analysis., MASCOTS 2009: 1-4
Diego Lugones, Daniel Franco, Emilio Luque, Adaptive Multipath Routing for Congestion Control in InfiniBand Networks., ICPP Workshops 2009: 222-227
Diego Lugones, Daniel Franco, Emilio Luque, Dynamic and Distributed Multipath Routing Policy for High-Speed Cluster Networks., CCGRID 2009: 396-403
Dietmar Schreiner, Markus Schordan, Jens Knoop, Adding Timing-Awareness to AUTOSAR Basic-Software -- A Component Based Approach., ISORC 2009: 288-292
Dimitrios Dimitriadis, A. Metallinou, Ioannis Konstantinou, Georgios I. Goumas, Petros Maragos, Nectarios Koziris, GridNews: A distributed automatic Greek broadcast transcription system., ICASSP 2009: 1917-1920
Dimitrios Kontos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths., FPL 2009: 282-287
Dimitrios S. Nikolopoulos, Green Building Blocks - Software Stacks for Energy-Efficient Clusters and Data Centres., ERCIM News 2009(79): (2009)
Dimitris Gizopoulos, Online Periodic Self-Test Scheduling for Real-Time Processor-Based Systems Dependability Enhancement, IEEE Transactions on Dependable and Secure Computing, vol. 6, no. 2, pp. 152-158, April-June 2009.
Dimitris Theodoropoulos, Catalin Bogdan Ciobanu, Georgi Kuzmanov, Wave field synthesis for 3D audio: architectural prospectives., Conf. Computing Frontiers 2009: 127-136
Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gayd, Reconfigurable accelerator for WFS-based 3D-audio, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Dirk Koch, Christian Beckhoff, Jürgen Teich, A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs., FPGA 2009: 253-256
Dirk Koch, Christian Beckhoff, Jürgen Teich, Hardware Decompression Techniques for FPGA-Based Embedded Systems., TRETS 2(2): (2009)
Dirk Koch, Christian Beckhoff, Jürgen Teich, Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems., FCCM 2009: 251-254
Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich, Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Springer-Verlag, January 2009
Dmitrijs Zaparanuks, Milan Jovic, Matthias Hauswirth, Accuracy of performance counter measurements., ISPASS 2009: 23-32
Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro, Koen De Bosschere, Linux Kernel Compaction through Cold Code Swapping., T. HiPEAC 2: 173-200 (2009)
Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor, Hierarchical Segmentation for Hardware Function Evaluation., IEEE Trans. VLSI Syst. 17(1): 103-116 (2009)
Dragana Damjanovic, Philipp Gschwandtner, Michael Welzl, Why Is This Web Page Coming Up so Slow? Investigating the Loss of SYN Packets., Networking 2009: 895-906
Dror G. Feitelson, Edi Shmueli, A case for conservative workload modeling: Parallel job scheduling with daily cycles of activity., MASCOTS 2009: 1-8
Dyer Rolán, Basilio B. Fraguela, Ramón Doallo, Adaptive Line Placement with the Set Balancing Cache, 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42). pp. 529-540.
E. G. Paredes, C. Lema, Margarita Amor, Montserrat Bóo, Hybrid Terrain Visualization based on Local Tessellations., GRAPP 2009: 64-69
E. Moyano-Ávila, L. Orozco-Barbosa, F. J. Quiles, Parallel Algorithms Based on the Temporal-Window Method for Non-Alternating 3D-WT over Angiographies Using a Multicomputer, Journal of Signal Processing Systems , Volume 55 Issue 1-3, Kluwer Academic Publishers, April 2009
E. Tiakas, A. N. Papadopoulos, A. Nanopoulos, Y. Manolopoulos, Dragan Stojanovic, Slobodanka Djordjevic-Kajan, Searching for similar trajectories in spatial networks, Journal of Systems and Software , Volume 82 Issue 5, Elsevier Science Inc., May 2009
Edi Shmueli, Dror G. Feitelson, On Simulation and Design of Parallel-Systems Schedulers: Are We Doing the Right Thing?, IEEE Transactions on Parallel and Distributed Systems , Volume 20 Issue 7, IEEE Press, July 2009
Eduard Ayguadé, Jordi Torres, Creating Power-Aware Middleware for Energy-Efficient Data Centres., ERCIM News 2009(79): (2009)
Eduard Ayguadé, Nawal Copty, Alejandro Duran, Jay Hoeflinger, Yuan Lin, Federico Massaioli, Xavier Teruel, Priya Unnikrishnan, Guansong Zhang, The Design of OpenMP Tasks., IEEE Trans. Parallel Distrib. Syst. 20(3): 404-418 (2009)
Eduard Ayguadé, Rosa M. Badia, Daniel Cabrera, Alejandro Duran, Marc González, Francisco D. Igual, Daniel Jimenez, Jesús Labarta, Xavier Martorell, Rafael Mayo, Josep M. Pé, A Proposal to Extend the OpenMP Tasking Model for Heterogeneous Architectures., IWOMP 2009: 154-167
Eduardo Argollo, Ayose Falcón, Paolo Faraboschi, Matteo Monchiero, Daniel Ortega, COTSon: infrastructure for full system simulation, SIGOPS Operating Systems Review , Volume 43 Issue 1, ACM, January 2009
Eduardo Argollo, Ayose Falcón, Paolo Faraboschi, Matteo Monchiero, Daniel Ortega, COTSon: infrastructure for full system simulation., Operating Systems Review 43(1): 52-61 (2009)
Eduardo Quinones, Emery D. Berger, Guillem Bernat, Francisco J. Cazorla, Using Randomized Caches in Probabilistic Real-Time Systems, ECRTS '09: Proceedings of the 2009 21st Euromicro Conference on Real-Time Systems - Volume 00 , Volume 00, IEEE Computer Society, July 2009
Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri Weiser, Multiple clock and voltage domains for chip multi processors., MICRO 2009: 459-468
Eladio Gutiérrez, Sergio Romero, María A. Trenas, Oscar G. Plata, Experiences with Mapping Non-linear Memory Access Patterns into GPUs., ICCS (1) 2009: 924-933
Eleftherios Kolonis, Michael Nicolaidis, Dimitris Gizopoulos, Mihalis Psarakis, Jacques Collet, Piotr Zajac, Enhanced Self-Configurability and Yield in Multicore Grids, IEEE International On-Line Testing Symposium (IOLTS 2009), Sesimbra, Portugal, pp. 75-80, June 2009.
Elisardo Antelo, A Comment on "Beyond Fat-tree: Unidirectional Load-Balanced Multistage Interconnection Network", IEEE Computer Architecture Letters , Volume 8 Issue 1, IEEE Computer Society, January 2009
Emiliano Betti, Marco Cesati, Roberto Gioiosa, Francesco Piermaria, A global operating system for HPC clusters., CLUSTER 2009: 1-10
Emilio J. Padrón, Margarita Amor, Montserrat Bóo, Ramon Doallo, High Performance Global Illumination on Multi-core Architectures., PDP 2009: 93-100
Enno Lübbers, Marco Platzner, ReconOS: Multithreaded programming for reconfigurable computers, Transactions on Embedded Computing Systems (TECS) , Volume 9 Issue 1, ACM, October 2009
Enno Lübbers, Marco Platzner, Cooperative multithreading in dynamically reconfigurable systems., FPL 2009: 551-554
Epifanio Gaona, Juan Fernández, Manuel E. Acacio, Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades., Euro-Par 2009: 900-911
Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi, ProtoFlex: Towards Scalable Full-System Multiprocessor Simulations Using FPGAs., TRETS 2(2): (2009)
Esther Salamí, Sol Pedre, Patricia Borensztejn, Cristina Barrado, Andres Stoliar, Enric Pastor, Decision Support System for Hot Spot Detection., Intelligent Environments 2009: 277-284
Evangelos P. Markatos, Manuel Costa, Proceedings of the Second European Workshop on System Security EUROSEC 2009 Nuremburg Germany March 31 2009, ACM 2009
Evgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Packet-level static timing analysis for NoCs., NOCS 2009: 88
F. Castro, D. Chaver, L. Pinuel, M. Prieto, F. Tirado, Using age registers for a simple load-store queue filtering, Journal of Systems Architecture: the EUROMICRO Journal , Volume 55 Issue 2, Elsevier North-Holland, Inc., February 2009
Fabio Cancare, Marco D. Santambrogio, Donatella Sciuto, An application-centered design flow for self reconfigurable systems implementation, ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, IEEE Press, January 2009
Fabio Checconi, Tommaso Cucinotta, Manuel Stein, Real-Time Issues in Live Migration of Virtual Machines., Euro-Par Workshops 2009: 454-466
Fabio Garzia, Roberto Airoldi, Tapani Ahonen, Jari Nurmi, Dragomir Milojevic, Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios., SiPS 2009: 030-035
Fabio Garzia, Waqar Hussain, Jari Nurmi, CREMA: A coarse-grain reconfigurable array with mapping adaptiveness., FPL 2009: 708-712
Fabrizio Ferrandi, Marco Lattuada, Christian Pilato, Antonino Tumeo, Performance estimation for task graphs combining sequential path profiling and control dependence regions., MEMOCODE 2009: 131-140
Fabrizio Mulas, David Atienza, Andrea Acquaviva, Salvatore Carta, Luca Benini, Giovanni De Micheli, Thermal Balancing Policy for Multiprocessor Stream Computing Platforms., IEEE Trans. on CAD of Integrated Circuits and Systems 28(12): 1870-1882 (2009)
Fakhri Alam Khan, Yuzhang Han, Sabri Pllana, Peter Brezany, Estimation of Parameters Sensitivity for Scientific Workflows., ICPP Workshops 2009: 457-462
Faruk Bagci, Florian Kluge, Theo Ungerer, Nader Bagherzadeh, Optimisations for LocSens - an indoor location tracking system using wireless sensors., IJSNET 6(3/4): 157-166 (2009)
Faruk Bagci, Theo Ungerer, Nader Bagherzadeh, SecSens - Security Architecture for Wireless Sensor Networks, SENSORCOMM '09: Proceedings of the 2009 Third International Conference on Sensor Technologies and Applications - Volume 00 , Volume 00, IEEE Computer Society, June 2009
Ferad Zyulkyarov, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero, Atomic quake: using transactional memory in an interactive multiplayer game server., PPOPP 2009: 25-34
Fermin Ayuso, Javier Setoain, Manuel Prieto, Christian Tenllado, Francisco Tirado, Javier Plaza, Antonio Plaza, Endmember Extraction from Hyperspectral Imagery using a Parallel Ensemble Approach with Consensus Analysis., IGARSS (5) 2009: 88-91
Fernando Castro, Regana Noor, Alok Garg, Daniel Chaver, Michael C. Huang, Luis Piñuel, Manuel Prieto, Francisco Tirado, Replacing Associative Load Queues: A Timing-Centric Approach, IEEE Transactions on Computers , Volume 58 Issue 4, IEEE Computer Society, April 2009
Fernando Royo, Miguel López-Guerrero, Luis Orozco-Barbosa, Teresa Olivares, 2C-WSN: A Configuration Protocol Based on TDMA Communications over WSN., GLOBECOM 2009: 1-6
Filip Blagojevic, Costin Iancu, Katherine A. Yelick, Matthew Curtis-Maury, Dimitrios S. Nikolopoulos, Benjamin Rose, Scheduling dynamic parallelism on accelerators., Conf. Computing Frontiers 2009: 161-170
Florian Kluge, Chenglong Yu, Jörg Mische, Sascha Uhrig, Theo Ungerer, Implementing AUTOSAR scheduling and resource management on an embedded SMT processor, SCOPES '09: Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems, Full text available:, April 2009
Florin Isaila, Javier Garcia Blas, Jesus Carretero, Robert Latham, Samuel Lang, Robert Ross, Latency Hiding File I/O for Blue Gene Systems, CCGRID '09: Proceedings of the 2009 9th IEEE/ACM International Symposium on Cluster Computing and the Grid - Volume 00 , Volume 00, IEEE Computer Society, May 2009
François Bodin, Keynote: Compilers in the Manycore Era., HiPEAC 2009: 2-3
François Bodin, Stéphane Bihan, Heterogeneous multicore parallel programming for graphics processing units., Scientific Programming 17(4): 325-336 (2009)
Francesco Paterna, Andrea Acquaviva, Francesco Papariello, Giuseppe Desoli, Luca Benini, Variability-tolerant Workload Allocation for MPSoC Energy Minimization under Real-time Constraints, 7th IEEE Workshop on Embedded Systems for Real-Time Multimedia
Francesco Paterna, Andrea Acquaviva, Francesco Papariello, Giuseppe Desoli, Mauro Olivieri, Luca Benini, Adaptive Idleness Distribution for Non-uniform Aging Tolerance in MultiProcessor Systems-on-Chip, Design, Automation and Test in Europe '09, IEEE
Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo , Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology., Transactions on Computational Science 4: 230-243 (2009)
Francesco Zanini, David Atienza, Giovanni De Micheli, A control theory approach for thermal balancing of MPSoC, ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, IEEE Press, January 2009
Francisco Gilabert Villamón, Daniele Ludovici, Simone Medardoni, Davide Bertozzi, Luca Benini, Georgi Nedeltchev Gaydadjiev, Designing Regular Network-on-Chip Topologies under Technology Architecture and Software Constraints., CISIS 2009: 681-687
Francisco J. Rincón, Laura Gutiérrez, Mónica Jiménez, Víctor Díaz, Nadia Khaled, David Atienza, Marcos Sanchez-Elez, Joaquín Recas, Giovanni De Micheli, Implementation of an Automated ECG-based Diagnosis Algorithm for a Wireless Body Sensor Plataform., BIODEVICES 2009: 88-96
Francisco José Alfaro, José L. Sánchez, José Duato, A new strategy to manage the InfiniBand arbitration tables., J. Parallel Distrib. Comput. 69(6): 508-520 (2009)
Frank Eichinger, David Kramer, Klemens Böhm, Wolfgang Karl, From Source Code to Runtime Behaviour: Software Metrics Help to Select the Computer Architecture., SGAI Conf. 2009: 363-376
Frank Hannig, Hritam Dutta, Jürgen Teich, Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning., ARCS 2009: 16-27
Frank Ophelders, Marco J.G. Bekooij, Henk Corporaal, A tuneable software cache coherence protocol for heterogeneous MPSoCs, CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, ACM, October 2009
Frederico Pratas, Pedro Trancoso, Alexandros Stamatakis, Leonel Sousa, Fine-grain Parallelism Using Multi-core Cell/BE and GPU Systems: Accelerating the Phylogenetic Likelihood Function., ICPP 2009: 9-17
Frederik Vandeputte, Lieven Eeckhout, Finding Stress Patterns in Microprocessor Workloads., HiPEAC 2009: 153-167
Friman Sánchez, Alex Ramírez, Mateo Valero, Quantitative analysis of sequence alignment applications on multiprocessor architectures., Conf. Computing Frontiers 2009: 61-70
Gábor Fekete, Timo Hämäläinen, State of Host-Centric Multihoming in IP Networks., NTMS 2009: 1-5
G. Delgado, V. Aranda, J. Calero, M. Sánchez-Marañón, J. M. Serrano, D. Sánchez, M. A. Vila, Using fuzzy data mining to evaluate survey data from olive grove cultivation, Computers and Electronics in Agriculture , Volume 65 Issue 1, Elsevier Science Publishers B. V., January 2009
G. Pokam, C. Pereira, K. Danne, R. Kassa, A-R. Adl-Tabatabai, Architecting a Chunk-based Memory Race Recorder in Modern CMPs, MICRO 2009
Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva, José Marinho, Parallel LDPC Decoding on the Cell/B.E. Processor., HiPEAC 2009: 389-403
Gabriel Falcão Paiva Fernandes, Vítor Manuel Mendes da Silva, Leonel Sousa, How GPUs can outperform ASICs for fast LDPC decoding., ICS 2009: 390-399
Gabriel Rodríguez, María J. Martín, Patricia González, Juan Touriño, A Heuristic Approach for the Automatic Insertion of Checkpoints in Message-Passing Codes., J. UCS 15(14): 2894-2911 (2009)
Gearold Johnson, Carsten Trinitis, Georgi Gaydadjiev, Alexander V. Veidenbaum, Proceedings of the 6th Conference on Computing Frontiers 2009 Ischia Italy May 18-20 2009, ACM 2009
George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Manolis Katevenis, Dionisios Pnevmatikatos, Xiaojun Yang, FPGA Implementation of a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability, Proc. IEEE Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2009),ISBN 978-1-4244-4501
George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Manolis Katevenis, Dionisios Pnevmatikatos, Xiaojun Yang, FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability, IEEE Computer Society (International Symposium on Systems, Architectures, Modeling, and Simulation, IC-SAMOS 2009)
George Panagiotakis, Michail D. Flouris, Angelos Bilas, Reducing Disk I/O Performance Sensitivity for Large Numbers of Sequential Streams, ICDCS '09: Proceedings of the 2009 29th IEEE International Conference on Distributed Computing Systems - Volume 00 , Volume 00, IEEE Computer Society, June 2009
George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis, Instruction-based On-line Periodic Self-testing of Microprocessors With Floating-point Units, IEEE Transactions on Dependable and Secure Computing, vol. 6, no. 2, pp. 124-134, April-June 2009.
Georgi Kuzmanov, Polymorphic architectures: from media processing to supercomputing., CompSysTech 2009: 4
Georgios Goumas, Nikolaos Drosinos, Nectarios Koziris, Communication-Aware Supernode Shape, IEEE Transactions on Parallel and Distributed Systems , Volume 20 Issue 4, IEEE Press, April 2009
Georgios I. Goumas, Nikos Anastopoulos, Nectarios Koziris, Nikolas Ioannou, Overlapping computation and communication in SMT clusters with commodity interconnects., CLUSTER 2009: 1-10
Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras, Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches., T. HiPEAC 2: 4-22 (2009)
Georgios Tournavitis, Zheng Wang, Björn Franke, Michael O'Boyle, Towards a Holistic Approach to Auto-Parallelization: Integrating Profile-Driven Parallelism Detection and Machine-Learning Based Mapping, ACM SIGPLAN 2009 Conference on Programming Language Design and Implementation (PLDI)
Germán Rodríguez, Ramón Beivide, Cyriel Minkenberg, Jesús Labarta, Mateo Valero, Exploring pattern-aware routing in generalized fat tree networks., ICS 2009: 276-285
Gesner Passos, Nuno Roma, Bertinho Andrade da Costa, Leonel Sousa, João Miranda Lemos, Distributed Software Platform for Automation and Control of General Anaesthesia., ISPDC 2009: 135-142
Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, Variability-aware robust design space exploration of chip multiprocessor architectures, ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, IEEE Press, January 2009
Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration., IEEE Trans. on CAD of Integrated Circuits and Systems 28(12): 1816-1829 (2009)
Giovanni Agosta, Francesco Bruschi, Gerardo Pelosi, Donatella Sciuto, A transform-parametric approach to Boolean matching, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Volume 28 Issue 6, Institute of Electrical and Electronics Engineers Inc., The, June 2009
Giovanni Beltrame, Cristiana Bolchini, Antonio Miele, Multi-level fault modeling for transaction-level specifications., ACM Great Lakes Symposium on VLSI 2009: 87-92
Giovanni Beltrame, Luca Fossati, Donatella Sciuto, ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration., IEEE Trans. on CAD of Integrated Circuits and Systems 28(12): 1857-1869 (2009)
Gregorio Bernabé, José M. García, José González, A lossy 3D wavelet transform for high-quality compression of medical video., Journal of Systems and Software 82(3): 526-534 (2009)
Gregorio Quintana-Ortí, Francisco D. Igual, Enrique S. Quintana-Ortí, Robert A. van de Geijn, Solving dense linear systems on platforms with multiple hardware accelerators., PPOPP 2009: 121-130
Grigori Fursin, Olivier Temam, Collective Optimization., HiPEAC 2009: 34-49
Grzegorz Danilewicz, Wojciech Kabacinski, Remigiusz Rajewski, The New Banyan-Based Switching Fabric Architecture Composed of Asymmetrical Optical Switching Elements., GLOBECOM 2009: 1-6
Guillermo L. Taboada, Juan Touriño, Ramon Doallo, Java for high performance computing: assessment of current research and practice., PPPJ 2009: 30-39
Guna Santos, Leonardo Fialho, Dolores Rexachs, Emilio Luque, Increasing the availability provided by RADIC with low overhead., CLUSTER 2009: 1-8
Guttorm Sindre, Lasse Natvig, Magnus Jahre, Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals., IEEE Trans. Education 52(1): 10-18 (2009)
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne, Exploiting fast carry-chains of FPGAs for designing compressor trees., FPL 2009: 242-249
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne, An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor, Transactions on Reconfigurable Technology and Systems (TRETS) , Volume 2 Issue 3, ACM, September 2009
Hans Vandierendonck, André Seznec, Fetch Gating Control through Speculative Instruction Window Weighting., T. HiPEAC 2: 128-148 (2009)
Haohuan Fu, William Osborne, Robert G. Clapp, Oskar Mencer, Wayne Luk, Accelerating seismic computations using customized number representations on FPGAs, EURASIP Journal on Embedded Systems , Volume 2009, Hindawi Publishing Corp., January 2009
Harald Servat, Germán Llort, Judit Gimenez, Jesús Labarta, Detailed Performance Analysis Using Coarse Grain Sampling., Euro-Par Workshops 2009: 185-198
Harris Papadakis, Mema Roussopoulos, Paraskevi Fragopoulou, Evangelos P. Markatos, Imbuing Unstructured P2P Systems with Non-Intrusive Topology Awareness., Peer-to-Peer Computing 2009: 51-60
Hayden Stainsby, Ronal Muresano, Leonardo Fialho, Juan Carlos González, Dolores Rexachs, Emilio Luque, Teaching Model for Computational Science and Engineering Programme., ICCS (2) 2009: 34-43
Heikki Hurskainen, Elena Simona Lohan, Jari Nurmi, Stephan Sand, Christian Mensing, Marco Detratti, Optimal dual frequency combination for Galileo mass market receiver baseband., SiPS 2009: 261-266
Heikki Hurskainen, Jussi Raasakka, Tapani Ahonen, Jari Nurmi, Multicore Software-Defined Radio Architecture for GNSS Receiver Signal Processing., EURASIP J. Emb. Sys. 2009: (2009)
Heiko Sturzrehm, Pascal Felber, Christof Fetzer, TM-Stream: An STM framework for distributed event stream processing., IPDPS 2009: 1-8
Heiner Giefers, Marco Platzner, Program-driven fine-grained power management for the reconfigurable mesh., FPL 2009: 119-125
Hiroyuki Yagi, Wolfgang Rosenstiel, Jakob Engblom, Jason Andrews, Kees Vissers, Marc Serughetti, The wild west: conquest of complex hardware-dependent software design, DAC '09: Proceedings of the 46th Annual Design Automation Conference, ACM, July 2009
Hong Linh Truong, Peter Brunner, Vlad Nae, Thomas Fahringer, DIPAS: A distributed performance analysis service for grid service-based workflows., Future Generation Comp. Syst. 25(4): 385-398 (2009)
Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier, A holistic approach for tightly coupled reconfigurable parallel processors, Microprocessors & Microsystems , Volume 33 Issue 1, Elsevier Science Publishers B. V., February 2009
Hritam Dutta, Frank Hannig, Jürgen Teich, Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis., ARCS 2009: 233-245
Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli, Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits., NanoNet 2009: 141-150
Hugh Leather, Edwin Bonilla, Michael O'Boyle, Automatic Feature Generation for Machine Learning Based Optimizing Compilation, CGO '09: Proceedings of the 2009 International Symposium on Code Generation and Optimization, IEEE Computer Society, March 2009
Hugh Leather, Michael O'Boyle, Bruce Worton, Raced profiles: efficient selection of competing compiler optimizations, LCTES '09: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, ACM, June 2009
Hung Manh La, Weihua Sheng, Adaptive flocking control for dynamic target tracking in mobile sensor networks., IROS 2009: 4843-4848
Hung Manh La, Weihua Sheng, Flocking control of a mobile sensor network to track and observe a moving target., ICRA 2009: 3129-3134
Iñigo Artundo, Wim Heirman, Mikel Loperena, Christof Debaes, Jan Van Campenhout, Hugo Thienpont, Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects, HOTI '09: Proceedings of the 2009 17th IEEE Symposium on High Performance Interconnects - Volume 00 , Volume 00, IEEE Computer Society, August 2009
Iñigo Goiri, Ferran Julià, Jorge Ejarque, Marc de Palol, Rosa M. Badia, Jordi Guitart, Jordi Torres, Introducing Virtual Execution Environments for Application Lifecycle Management and SLA-Driven Resource Distribution within Service Providers., NCA 2009: 211-218
Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman, Power efficient tree-based crosslinks for skew reduction., ACM Great Lakes Symposium on VLSI 2009: 285-290
Ioannis Konstantinou, Dimitrios Tsoumakos, Nectarios Koziris, Measuring the Cost of Online Load-Balancing in Distributed Range-Queriable Systems., Peer-to-Peer Computing 2009: 135-138
Ioannis Sourdis, Ruben de Smet, Georgi N. Gaydadjiev, Range Trees with Variable Length Comparisons, EEE Workshop on High Performance Switching and Routing (HPSR), Paris, France, June 2009.
Ioannis Sourdis, Ruben de Smet, Georgi N. Gaydadjiev, Georgios Stefanakis, Range Tries for Scalable Address Lookup, ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), Princeton, New Jersey, USA, October 2009.
Iouliia Skliarova, Valery Sklyarov, Recursion in reconfigurable computing: A survey of implementation approaches., FPL 2009: 224-229
Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip., PATMOS 2009: 86-95
Iria Varela Senin, Lotfi Mhamdi, Kees Goossens, Efficient Multicast Support in Buffered Crossbars using Networks on Chip., GLOBECOM 2009: 1-7
Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos, Extending an embedded RISC microprocessor for efficient translation based Java execution., Microprocessors and Microsystems - Embedded Hardware Design 33(7-8): 415-429 (2009)
Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai, Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors., ASP-DAC 2009: 449-454
Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai, Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors., IEICE Transactions 92-A(4): 1161-1173 (2009)
Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer, IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor., HiPEAC 2009: 125-139
J. Benton, Minh Do, Subbarao Kambhampati, Anytime heuristic search for partial satisfaction planning, Artificial Intelligence , Volume 173 Issue 5-6, Elsevier Science Publishers Ltd., April 2009
J. C. Pichel, D. B. Heras, J. C. Cabaleiro, F. F. Rivera, Increasing data reuse of sparse algebra codes on simultaneous multithreading architectures, Concurrency and Computation: Practice & Experience , Volume 21 Issue 15, John Wiley and Sons Ltd., October 2009
J. Gómez, Some new large (Δ, 3)-graphs, Networks , Volume 53 Issue 1, Wiley-Interscience, January 2009
Jack Dongarra, Pete Beckman, Patrick Aerts, Frank Cappello, Thomas Lippert, Satoshi Matsuoka, Paul Messina, Terry Moore, Rick Stevens, Anne Trefethen, Mateo Valero, The International Exascale Software Project: a Call To Cooperative Action By the Global High-Performance Community, International Journal of High Performance Computing Applications , Volume 23 Issue 4, Sage Publications, Inc., November 2009
Jacob Jan-David Mol, Arno Bakker, Johan A. Pouwelse, Dick H. J. Epema, Henk J. Sips, The Design and Deployment of a BitTorrent Live Video Streaming Solution., ISM 2009: 342-349
Jai Vaze, W. H. Johnston, Jin Teng, Narendra Kumar Tuteja, Ian Johnson, Development and implementation of a generic pasture growth model (CLASS PGM)., Environmental Modelling and Software 24(1): 107-114 (2009)
Jan Beutel, Stephan Gruber, Andreas Hasler, Roman Lim, Andreas Meier, Christian Plessl, Igor Talzi, Lothar Thiele, Christian Tschudin, Matthias Woehrle, Mustafa Yuecel, PermaDAQ: A scientific instrument for precision sensing and data recovery in environmental extremes, IPSN '09: Proceedings of the 2009 International Conference on Information Processing in Sensor Networks - Volume 00 , Volume 00, IEEE Computer Society, April 2009
Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne, Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications., SiPS 2009: 115-120
Jani Puttonen, Gábor Fekete, Tapio Väärämäki, Timo Hämäläinen, Multiple Interface Management of Multihomed Mobile Hosts in Heterogeneous Wireless Environments., ICN 2009: 324-331
Jari Heikkinen, Jarmo Takala, Henk Corporaal, Dictionary-based program compression on customizable processor architectures, Microprocessors & Microsystems , Volume 33 Issue 2, Elsevier Science Publishers B. V., March 2009
Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen, A Configurable Motion Estimation Architecture for Block-Matching Algorithms., IEEE Trans. Circuits Syst. Video Techn. 19(4): 466-477 (2009)
Javier Cabezas, Mauricio Araya-Polo, Isaac Gelado, Nacho Navarro, Enric Morancho, José María Cela, High-Performance Reverse Time Migration on GPU., SCCC 2009: 77-86
Javier D. Bruguera, Marius Cornea, Debjit Das Sarma, John Harrison, 19th IEEE Symposium on Computer Arithmetic ARITH 2009 Portland Oregon USA 9-10 June 2009, IEEE Computer Society 2009
Javier Navaridas, Jose A. Pascual, José Miguel-Alonso, Effects of Job and Task Placement on Parallel Scientific Applications Performance., PDP 2009: 55-61
Javier Navaridas, Jose Miguel-Alonso, Realistic Evaluation of Interconnection Networks Using Synthetic Traffic, ISPDC '09: Proceedings of the 2009 Eighth International Symposium on Parallel and Distributed Computing - Volume 00 , Volume 00, IEEE Computer Society, June 2009
Javier Navaridas, Mikel Luján, José Miguel-Alonso, Luis A. Plana, Steve Furber, Understanding the interconnection network of SpiNNaker., ICS 2009: 286-295
Jay L. T. Cornwall, Lee W. Howes, Paul H. J. Kelly, Phil Parsonage, Bruno Nicoletti, High-performance SIMT code generation in an active visual effects library., Conf. Computing Frontiers 2009: 175-184
Jean Christophe Beyler, Michael Klemm, Philippe Clauss, Michael Philippsen, A meta-predictor framework for prefetching in object-based DSMs., Concurrency and Computation: Practice and Experience 21(14): 1789-1803 (2009)
Jeffrey C. Mogul, Eduardo Argollo, Mehul A. Shah, Paolo Faraboschi, Operating System Support for NVM+DRAM Hybrid Main Memory., HoHotOS 2009
Jehangir Khan, Smaïl Niar, Mazen A. R. Saghir, Yassine El-Hillali, Atika Rivenq-Menhaj, Trade-Off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture., EURASIP J. Emb. Sys. 2009: (2009)
Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid, Task management in MPSoCs: An ASIP approach., ICCAD 2009: 587-594
Jesús Delicado, Qiang Ni, Francisco Delicado, Luis Orozco-Barbosa, New contention resolution schemes for WiMAX., WCNC 2009: 1736-1741
Jesus Carretero, Jose Daniel Garcia, Scalability in data management, The Journal of Supercomputing , Volume 47 Issue 3, Kluwer Academic Publishers, March 2009
Jia Guo, Ganesh Bikshandi, Basilio B. Fraguela, David Padua, Writing productive stencil codes with overlapped tiling, Concurrency and Computation: Practice & Experience , Volume 21 Issue 1, John Wiley and Sons Ltd., January 2009
Jie Xiang, Yan Zhang, Tor Skeie, Dynamic Spectrum Sharing in Cognitive Radio Femtocell Networks., AccessNets 2009: 164-178
Jie Xiang, Yan Zhang, Tor Skeie, Jianhua He, QoS aware admission and power control for cognitive radio cellular networks., Wireless Communications and Mobile Computing 9(11): 1520-1531 (2009)
Jin Wang, Guofeng Li, Yiyi Liu, Yi Lu, Xianhu Gao, Yong Zhang, Ke Tao, Vehicle supervision system based on MEMS geomagnetic sensor., NEMS 2009: 331-334
João Martins, Pedro Tomás, Leonel Sousa, Neural code metrics: Analysis and application to the assessment of neural models., Neurocomputing 72(10-12): 2337-2350 (2009)
Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith, SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications., ACM Trans. Design Autom. Electr. Syst. 13(1): (2009)
Joaquín Franco, Gregorio Bernabé, Juan Fernández, Manuel E. Acacio, A Parallel Implementation of the 2D Wavelet Transform Using CUDA., PDP 2009: 111-118
John Thomson, Michael F. P. O'Boyle, Grigori Fursin, Björn Franke, Reducing Training Time in a One-Shot Machine Learning-Based Compiler., LCPC 2009: 399-407
Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Word-length selection for power minimization via nonlinear optimization., ACM Trans. Design Autom. Electr. Syst. 14(3): (2009)
Joon Edward Sim, Weng-Fai Wong, Jürgen Teich, Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators., FCCM 2009: 279-282
José L. Risco-Martín, David Atienza, Rubén Gonzalo, J. Ignacio Hidalgo, Optimization of dynamic memory managers for embedded systems using grammatical evolution, GECCO '09: Proceedings of the 11th Annual conference on Genetic and evolutionary computation, ACM, July 2009
José L. Risco-Martín, J. Ignacio Hidalgo, David Atienza, Juan Lanchares, Oscar Garnica, Mixed heuristic and mathematical programming using reference points for dynamic data types optimization in multimedia embedded systems, GECCO '09: Proceedings of the 11th Annual conference on Genetic and evolutionary computation, ACM, July 2009
José Duato, Francisco D. Igual, Rafael Mayo, Antonio J. Peña, Enrique S. Quintana-Ortí, Federico Silla, An Efficient Implementation of GPU Virtualization in High Performance Clusters., Euro-Par Workshops 2009: 385-394
José Ignacio Aliaga, Francisco Almeida, José M. Badía, Sergio Barrachina, Vicente Blanco Pérez, María Isabel Castillo, Rafael Mayo, Enrique S. Quintana-Ortí, , Toward the parallelization of GSL., The Journal of Supercomputing 48(1): 88-114 (2009)
José Luis Martínez, Hari Kalva, Warnakulasuriya Anil Chandana Fernando, Pedro Cuenca, Francisco J. Quiles, Effiecient WZ-to-H264 transcoding using motion vector information sharing., ICME 2009: 1394-1397
José M. Cecilia, José M. García, Ginés D. Guerrero, Miguel A. Martínez-del-Amor, Ignacio Pérez-Hurtado, Mario J. Pérez-Jiménez, Implementing P Systems Parallelism by Means of GPUs., Workshop on Membrane Computing 2009: 227-241
José Manuel Velasco, David Atienza, Katzalin Olcoz, Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems., ACM Great Lakes Symposium on VLSI 2009: 3-8
Jose M. Badía, Peter Benner, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Alfredo Remón, Parallel Implementation of LQG Balanced Truncation for Large-Scale Systems, Large-Scale Scientific Computing, Springer-Verlag, March 2009
Jose Maria Quintana, Maria Jose Avedillo, Juan Nuñez, Hector Pettenghi, Operation Limits for RTD-based MOBILE Circuits, IEEE Trans. on Circuits and Systems I, vol. 56, no. 2, pp. 350-363
Josef Angermeier, Abdulazim Amouri, Jürgen Teich, General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems., FPL 2009: 302-307
Josef Kanizo, David Hay, Isaac Keslassy, The Crosspoint-Queued Switch., INFOCOM 2009: 729-737
Josef Kanizo, David Hay, Isaac Keslassy, Optimal Fast Hashing., INFOCOM 2009: 2500-2508
Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk, Modeling post-techmapping and post-clustering FPGA circuit depth., FPL 2009: 205-211
Juan Carlos González, Christianne Dalforno, Remo Suppi, Emilio Luque, A Fuzzy Logic Fish School Model., ICCS (1) 2009: 13-22
Juan Carlos Pichel, Dora Blanco Heras, José Carlos Cabaleiro, Francisco F. Rivera, Increasing data reuse of sparse algebra codes on simultaneous multithreading architectures., Concurrency and Computation: Practice and Experience 21(15): 1838-1856 (2009)
Juan M. Cebrian, Juan L. Aragon, Jose M. Garcia, Pavlos Petoumenos, Stefanos Kaxiras, Efficient microarchitecture policies for accurately adapting to power constraints, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Julien Dusser, Thomas Piquet, André Seznec, Zero-content augmented caches., ICS 2009: 46-55
Julio Merino, Lluc Alvarez, Marisa Gil, Nacho Navarro, Cetra: A Trace and Analysis Framework for the Evaluation of Cell BE Systems, ISPASS-2009
Jun Qin, Thomas Fahringer, Radu Prodan, A novel graph based approach for automatic composition of high quality grid workflows., HPDC 2009: 167-176
Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung, Self-Measurement of Combinatorial Circuit Delays in FPGAs., TRETS 2(2): (2009)
K. Bousias, L. Guang, C. R. Jesshope, M. Lankamp, Implementation and evaluation of a microthread architecture, Journal of Systems Architecture: the EUROMICRO Journal , Volume 55 Issue 3, Elsevier North-Holland, Inc., March 2009
K. Geihs, P. Barone, F. Eliassen, J. Floch, R. Fricke, E. Gjorven, S. Hallsteinsen, G. Horn, M. U. Khan, A. Mamelli, G. A. Papadopoulos, N. Paspallis, R. Reichle, E. Stav, A comprehensive solution for application-level adaptation, Software—Practice & Experience , Volume 39 Issue 4, John Wiley & Sons, Inc., March 2009
K. Stavrou, D. Pavlou, , M. Nikolaides, P. Petrides , P. Evripidou, P. Trancoso, Z. Popovic, R. Giorgi, Programming Abstractions and Toolchain for Dataflow Multithreading Architectures, IEEE Proc. Eighth Int.l Symp. on Parallel and Distributed Computing (ISPDC 2009), ISBN:978-0-7695-3680-4, Lisbon, Portugal, July
Kamana Sigdel, Mark Thompson, Andy D. Pimentel, Carlo Galuzzi, Koen Bertels, System-level runtime mapping exploration of reconfigurable architectures, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Katherine Compton, Roger Woods, Christos-Savvas Bouganis, Pedro C. Diniz, Introduction to the Special Issue ARC'08., TRETS 2(4): (2009)
Kathryn E. Gray, Alan Mycroft, Logical Testing., FASE 2009: 186-200
Kees van der Bok, Mottaqiallah Taouil, Panagiotis Afratis, Ioannis Sourdis, The TU Delft Sudoku Solver on FPGA, Int. Conf. on Field-Programmable Technology (FPT), Sydney, Australia, December 2009.
Kenneth Hoste, Lieven Eeckhout, A Methodology for Analyzing Commercial Processor Performance Numbers, Computer , Volume 42 Issue 10, IEEE Computer Society Press, October 2009
Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout, MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor., HiPEAC 2009: 110-124
Kevin Lee, Norman W. Paton, Rizos Sakellariou, Alvaro A. A. Fernandes, Utility Driven Adaptive Work?ow Execution., CCGRID 2009: 220-227
Kevin Williams, Jason McCandless, David Gregg, Portable Just-in-Time Specialization of Dynamically Typed Scripting Languages., LCPC 2009: 391-398
Khaled Z. Ibrahim, Smaïl Niar, Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC., T. HiPEAC 2: 286-306 (2009)
Kleopatra Konstanteli, Dimosthenis Kyriazis, Theodora A. Varvarigou, Tommaso Cucinotta, Gaetano Anastasi, Real-Time Guarantees in Flexible Advance Reservations., COMPSAC (2) 2009: 67-72
Kong Woei Susanto, Tim Todman, José Gabriel F. Coutinho, Wayne Luk, Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation., SOFSEM 2009: 509-520
Konrad Trifunovic, Dorit Nuzman, Albert Cohen, Ayal Zaks, Ira Rosen, Polyhedral-Model Guided Loop-Nest Auto-Vectorization, PACT '09: Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques - Volume 00 , Volume 00, IEEE Computer Society, September 2009
Konstantinos I. Karantasis, Eleftherios D. Polychronopoulos, Is shared memory programming attainable on clusters of embedded processors?, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Konstantinos I. Karantasis, Eleftherios D. Polychronopoulos, Pleiad: a cross-environment middleware providing efficient multithreading on clusters, CF '09: Proceedings of the 6th ACM conference on Computing frontiers, ACM, May 2009
Konstantinos Kyriakoulakos, Dionisios N. Pnevmatikatos, A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support., FPL 2009: 193-198
Konstantinos Nikas, Nikos Anastopoulos, Georgios I. Goumas, Nectarios Koziris, Employing Transactional Memory and Helper Threads to Speedup Dijkstra's Algorithm., ICPP 2009: 388-395
Kostas Siozios, Dimitrios Soudris, An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Springer-Verlag, January 2009
Kostas Siozios, Dimitrios Soudris, Designing a novel high-performance FPGA architecture for data intensive applications., J. Real-Time Image Processing 4(2): 155-166 (2009)
Krisztián Flautner, Life on the Treadmill., ARCS 2009: 1
Lassi Nurmi, Perttu Salmela, Pertti Kellomäki, Pekka Jääskeläinen, Jarmo Takala, Reconfigurable video decoder with transform acceleration., SiPS 2009: 081-086
Laura C. De Giusti, Emilio Luque, Franco Chichizola, Marcelo R. Naiouf, Armando De Giusti, AMTHA: An Algorithm for Automatically Mapping Tasks to Processors in Heterogeneous Multiprocessor Architectures., CSIE (2) 2009: 481-485
Laura Prada, José Daniel García Sánchez, Jesús Carretero, Felix Garcia, Saving power in flash and disk hybrid storage system., MASCOTS 2009: 1-3
Leandro Fiorin, Gianluca Palermo, Cristina Silvano, MPSoCs Run-Time Monitoring through Networks-on-Chip, ACM
Leandro Fiorin, Gianluca Palermo, Cristina Silvano, Mariagiovanna Sami, "Security in NoC". In "Networks-on-Chips: Theory and Practice", Taylor & Francis Group
Lee W. Howes, Anton Lokhmotov, Alastair F. Donaldson, Paul H. J. Kelly, Deriving Efficient Data Movement from Decoupled Access/Execute Specifications., HiPEAC 2009: 168-182
Lee W. Howes, Anton Lokhmotov, Alastair F. Donaldson, Paul H. J. Kelly, Towards Metaprogramming for Parallel Systems on a Chip., Euro-Par Workshops 2009: 36-45
Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee, A software pipelining algorithm in high-level synthesis for FPGA architectures., ISQED 2009: 297-302
Lei Gao, Guangzhou Zeng, A Novel Sequential Testing Algorithm Based on Rough-Compact Sets Theory for Multiple Fault Diagnosis., CSIE (6) 2009: 17-23
Lennart Yseboodt, Michael Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jos Hulzink, Jef Meerbergen, Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring, Journal of Signal Processing Systems , Volume 57 Issue 1, Kluwer Academic Publishers, October 2009
Leonel Sousa, Preface., Euro-Par Workshops 2009: 69-70
Leonel Sousa, Svetislav Momcilovic, Vítor Manuel Mendes da Silva, Gabriel Falcão Paiva Fernandes, Multi-core platforms for signal processing: source and channel coding., ICME 2009: 1809-1812
Leonel Sousa, Yves Robert, Eighth International Symposium on Parallel and Distributed Computing ISPDC 2009 Lisbon Portugal June 30-July 4 2009, IEEE Computer Society 2009
Lik Wong, Nimar S. Arora, Lei Gao, Thuvan Hoang, Jingwei Wu, Oracle Streams: A High Performance Implementation for Near Real Time Asynchronous Replication., ICDE 2009: 1363-1374
Lionel Lacassagne, Antoine Manzanera, Antoine Dupret, Motion detection: Fast and robust algorithms for embedded systems., ICIP 2009: 3265-3268
Lionel Lacassagne, Antoine Manzanera, Julien Denoulet, Alain Mérigot, High performance motion detection: some trends toward new embedded architectures for vision systems., J. Real-Time Image Processing 4(2): 127-146 (2009)
Lionel Lacassagne, Bertrand Zavidovique, Light Speed Labeling for RISC architectures., ICIP 2009: 3245-3248
Lorenzo Leonini, Etienne Riviere, Pascal Felber, SPLAY: Distributed Systems Evaluation Made Simple (or How to Turn Ideas into Live Systems in a Breeze)., NSDI 2009: 185-198
Lotfi Mhamdi, On the Integration of Unicast and Multicast Cell Scheduling in Buffered Crossbar Switches, IEEE Transactions on Parallel and Distributed Systems , Volume 20 Issue 6, IEEE Press, June 2009
Luís Tarrataca, André C. Santos, João M. P. Cardoso, The current feasibility of gesture recognition for a smartphone using J2ME., SAC 2009: 1642-1649
Luca Amati, Cristiana Bolchini, Laura Frigerio, Fabio Salice, William Eklow, Arnold Suvatne, Eugenio Brambilla, Federico Franzoso, Michele Martin, An Incremental Approach to Functional Diagnosis., DFT 2009: 392-400
Luca Benini, Predictability vs. Efficiency in the Multicore Era: Fight of Titans or Happy Ever after?., CAV 2009: 50
Luca Fossati, Daniele Varacca, The Calculus of Handshake Configurations., FOSSACS 2009: 227-241
Lucas Charles, Pascal Felber, Christophe Gête, TMBean: Optimistic Concurrency in Application Servers Using Transactional Memory., OTM Conferences (1) 2009: 484-496
Luigi Palopoli, Tommaso Cucinotta, Luca Marzario, Giuseppe Lipari, AQuoSA - adaptive quality of service architecture., Softw. Pract. Exper. 39(1): 1-31 (2009)
M. Alvarez Mesa, Alex Ramírez, Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mateo Valero, Scalability of Macroblock-level Parallelism for H.264 Decoding., ICPADS 2009: 236-243
M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli, A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories, ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, IEEE Press, January 2009
M. Lozano, P. Morillo, J. M. Orduña, V. Cavero, G. Vigueras, A new system architecture for crowd simulation, Journal of Network and Computer Applications , Volume 32 Issue 2, Academic Press Ltd., March 2009
M. M. Waliullah, Per Stenström, Schemes for avoiding starvation in transactional memory systems., Concurrency and Computation: Practice and Experience 21(7): 859-873 (2009)
M. Mustafa Rafique, Benjamin Rose, Ali R. Butt, Dimitrios S. Nikolopoulos, Supporting MapReduce on large-scale asymmetric multi-core clusters, SIGOPS Operating Systems Review , Volume 43 Issue 2, ACM, April 2009
M. W. van Tol, C. R. Jesshope, M. Lankamp, S. Polstra, An implementation of the SANE Virtual Processor using POSIX threads, Journal of Systems Architecture: the EUROMICRO Journal , Volume 55 Issue 3, Elsevier North-Holland, Inc., March 2009
Mafijul Md Islam, Sally A. McKee, Per Stenström, Cancellation of loads that return zero using zero-value caches., ICS 2009: 493-494
Mafijul Md. Islam, Per Stenstrom, Zero-Value Caches: Cancelling Loads that Return Zero, PACT '09: Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques - Volume 00 , Volume 00, IEEE Computer Society, September 2009
Magnus Jahre, Lasse Natvig, A light-weight fairness mechanism for chip multiprocessor memory systems., Conf. Computing Frontiers 2009: 1-10
Magnus Själander, Per Larsson-Edefors, Multiplication Acceleration Through Twin Precision., IEEE Trans. VLSI Syst. 17(9): 1233-1246 (2009)
Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk, Optimizing shared cache behavior of chip multiprocessors., MICRO 2009: 505-516
Manoj Gupta, Fermin Sanchez, Josep Llosa, Hybrid multithreading for VLIW processors, CASES '09: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems, ACM, October 2009
Manoj Gupta, R. C. Joshi, Hiding Fuzzy Association Rules Set., IICAI 2009: 275-289
Manolis Maragkakis, Panagiotis Alexiou, Giorgos L. Papadopoulos, Martin Reczko, Theodore Dalamagas, Giorgos Giannopoulos, George I. Goumas, Evangelos Koukis, Kornilios Kourtis, Victor A. Simossis, Pra, Accurate microRNA target prediction correlates with protein repression levels., BMC Bioinformatics 10: 295 (2009)
Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, A SIMD optimization framework for retargetable compilers., TACO 6(1): (2009)
Manuel Nickschas, Uwe Brinkschulte, CARISMA - A Service-Oriented Real-Time Organic Middleware Architecture., JSW 4(7): 654-663 (2009)
María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, Román Hermida, Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications., IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 60-73 (2009)
Marc Daumas, David Lester, César Muñoz, Verified Real Number Calculations: A Library for Interval Arithmetic., IEEE Trans. Computers 58(2): 226-237 (2009)
Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Phu V. Luong, Dual-Level Parallelism Exploitation with OpenMP in Coastal Ocean Circulation Modeling, ISHPC '02: Proceedings of the 4th International Symposium on High Performance Computing, Springer-Verlag, May 2009
Marc Schiely, Pascal Felber, Tit-for-tat revisited: Trading bandwidth for reliability in P2P media streaming., Multiagent and Grid Systems 5(2): 197-215 (2009)
Marcela Zuluaga, Nigel P. Topham, Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions., IEEE Trans. on CAD of Integrated Circuits and Systems 28(12): 1788-1801 (2009)
Marco Aldinucci, Hinde-Lilia Bouziane, Marco Danelutto, Christian Pérez, Stkm on Sca: A Unified Framework with Components Workflows and Algorithmic Skeletons., Euro-Par 2009: 678-690
Marco Aldinucci, Marco Danelutto, Peter Kilpatrick, Towards Hierarchical Management of Autonomic Components: A Case Study., PDP 2009: 3-10
Marco Aldinucci, Marco Danelutto, Peter Kilpatrick, Autonomic management of non-functional concerns in distributed & parallel application programming., IPDPS 2009: 1-12
Marco D. Santambrogio, Massimo Morandi, Marco Novati, Donatella Sciuto, A runtime relocation based workflow for self dynamic reconfigurable systems design., FPL 2009: 86-91
Marco D. Santambrogio, Massimo Redaelli, Marco Maggioni, Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuse., ACM Great Lakes Symposium on VLSI 2009: 21-26
Marco Garatti, Roberto Costa, Stefano Crespi Reghizzi, Erven Rohou, The Impact of Alias Analysis on VLIW Scheduling, ISHPC '02: Proceedings of the 4th International Symposium on High Performance Computing, Springer-Verlag, May 2009
Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero, Hardware support for WCET analysis of hard real-time multicore systems, ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture, ACM, June 2009
Marcos Sanchez-Elez, Nader Bagherzadeh, Román Hermida, A framework for low energy data management in reconfigurable multi-context architectures., Journal of Systems Architecture - Embedded Systems Design 55(2): 127-139 (2009)
Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, A sensor-based approach to linear blur identification for real-time video enhancement., ICIP 2009: 141-144
Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides, Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement, Transactions on Reconfigurable Technology and Systems (TRETS) , Volume 2 Issue 4, ACM, September 2009
Maribel Castillo, Francisco D. Igual, Mercedes Marqués, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Rafael Rubio, Robert A. van de Geijn, Out-of-core solution of linear systems on graphics processors., IJPEDS 24(6): 521-538 (2009)
Marina Biberstein, S. Dori-Hacohen, Yuval Harel, Andre Heilper, Bilha Mendelson, Uzi Shvadron, E. Treister, Javier Turek, Moon S. Chang, Cell Broadband Engine processor performance optimization: Tracing tools implementation and use., IBM Journal of Research and Development 53(5): 7 (2009)
Marina Biberstein, Yuval Harel, Andre Heilper, Clock synchronization in Cell/B.E. traces., Concurrency and Computation: Practice and Experience 21(14): 1760-1774 (2009)
Mario Leandro Bertogna, Eduardo Grosclaude, Marcelo Naiouf, Armando Giusti, Emilio Luque, Dynamic on Demand Virtual Clusters in Grid, Euro-Par 2008 Workshops - Parallel Processing, Springer-Verlag, April 2009
Marius Monton, Jakob Engblom, Mark Burton, Checkpoint and Restore for SystemC models., FDL 2009: 1-6
Mark Purcell, Owen Callanan, David Gregg, Streamlining Offload Computing to High Performance Architectures., ICCS (1) 2009: 974-983
Mark Woh, Sangwon Seo, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztian Flautner, AnySP: anytime anywhere anyway signal processing, ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture, ACM, June 2009
Markus Happe, Enno Lübbers, Marco Platzner, A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms., ARC 2009: 380-385
Martín Abadi, Andrew Birrell, Tim Harris, Johnson Hsieh, Michael Isard, Implementation and Use of Transactional Memory with Dynamic Separation., CC 2009: 63-77
Martín Abadi, Tim Harris, Perspectives on Transactional Memory., CONCUR 2009: 1-14
Martín Abadi, Tim Harris, Mojtaba Mehrara, Transactional memory with strong atomicity using off-the-shelf memory protection hardware., PPOPP 2009: 185-196
Marta Garcia, Julita Corbalán, Jesús Labarta, LeWI: A Runtime Balancing Algorithm for Nested Parallelism., ICPP 2009: 526-533
Martin Palkovic, Francky Catthoor, Henk Corporaal, Trade-offs in loop transformations., ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
Martin Palkovic, Henk Corporaal, Francky Catthoor, Dealing with data dependent conditions to enable general global source code transformations., IJES 4(1): 27-39 (2009)
Martin Sandrieser, Sabri Pllana, Siegfried Benkner, Evaluation of the SUN UltraSparc T2+ Processor for Computational Science., ICCS (1) 2009: 964-973
Martin Streubühr, Jens Gladigau, Christian Haubelt, Jürgen Teich, Efficient approximately-timed performance modeling for architectural exploration of MPSoCs., FDL 2009: 1-6
Martin Thuresson, Magnus Själander, Magnus Björk, Lars Svensson, Per Larsson-Edefors, Per Stenstrom, FlexCore: Utilizing Exposed Datapath Control for Efficient Computing, Journal of Signal Processing Systems , Volume 57 Issue 1, Kluwer Academic Publishers, October 2009
Martin Thuresson, Magnus Själander, Per Stenström, A Flexible Code Compression Scheme Using Partitioned Look-Up Tables., HiPEAC 2009: 95-109
Martino Ruggiero, Davide Bertozzi, Luca Benini, Michela Milano, A. Andrei, Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms., IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 378-391 (2009)
Martti Forsell, Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff, HPPC 2009 Panel: Are Many-Core Computer Vendors on Track?, Euro-Par Workshops 2009: 9-15
Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci, Reply to "Comments on Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes"., EURASIP J. Emb. Sys. 2009: (2009)
Mateo Valero, A european perspective on supercomputing., ICS 2009: 1
Mathias Funk, Anne Rozinat, Ana Karla Alves de Medeiros, Piet van der Putten, Henk Corporaal, Wil M. P. van der Aalst, Improving Product Usage Monitoring and Analysis with Semantic Concepts., UNISCON 2009: 190-201
Mathias Funk, Piet van der Putten, Henk Corporaal, Analytics for the internet of things., CHI Extended Abstracts 2009: 4195-4200
Matteo Monchiero, Jung Ho Ahn, Ayose Falcón, Daniel Ortega, Paolo Faraboschi, How to simulate 1000 cores, SIGARCH Computer Architecture News , Volume 37 Issue 2, ACM, July 2009
Matteo Monchiero, Jung Ho Ahn, Ayose Falcón, Daniel Ortega, Paolo Faraboschi, How to simulate 1000 cores., SIGARCH Computer Architecture News 37(2): 10-19 (2009)
Matthias Braun, Sebastian Hack, Register Spilling and Live-Range Splitting for SSA-Form Programs., CC 2009: 174-189
Matthias Hauswirth, Andrea Adamoli, Solve & evaluate with informa: a Java-based classroom response system for teaching Java, PPPJ '09: Proceedings of the 7th International Conference on Principles and Practice of Programming in Java, ACM, August 2009
Mauricio Alvarez, David Luengo, Neil D. Lawrence, Latent Force Models., Journal of Machine Learning Research - Proceedings Track 5: 9-16 (2009)
Maurizio Palesi , Rickard Holsmark, Shashi Kumar , Vincenzo Catania. , Application Specific Routing Algorithms for Networks on Chip, IEEE Transactions on Parallel and Distributed Systems
Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania, Application Specific Routing Algorithms for Networks on Chip., IEEE Trans. Parallel Distrib. Syst. 20(3): 316-330 (2009)
Maurizio Palesi, Shashi Kumar, Vincenzo Catania, Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms, Computers & Digital Techniques, IET
Md. Mafijul Islam, Per Stenström, Zero-Value Caches: Cancelling Loads that Return Zero., PACT 2009: 237-245
Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang, Computation reuse in domain-specific optimization of signal recognition., FPGA 2009: 281
Mercedes Marqués, Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Robert A. van de Geijn, Using Graphics Processors to Accelerate the Solution of Out-of-Core Linear Systems., ISPDC 2009: 169-176
Miao Wang, François Bodin, Sébastien Matz, Automatic Data Distribution for Improving Data Locality on the Cell BE Architecture., LCPC 2009: 247-262
Miao Wang, Nicolas Benoit, François Bodin, Model-Directed Multi-Level Parallelization for Multi-Task Programs on the Cell BE., CSA 2009: 1-6
Michael Factor, Assaf Schuster, Konstantin Shagin, Tal Zamir, Optimistic concurrency for clusters via speculative locking., SYSTOR 2009: 1
Michael O'Boyle, Henk Sips, Obituary: Peter Knijnenburg (1961–2007), Concurrency and Computation: Practice & Experience , Volume 21 Issue 1, John Wiley and Sons Ltd., January 2009
Michel Meulpolder, Johan A. Pouwelse, Dick H. J. Epema, Henk J. Sips, Modeling and Analysis of Bandwidth-Inhomogeneous Swarms in BitTorrent., Peer-to-Peer Computing 2009: 232-241
Michiel van Tol, Chris R. Jesshope, Mike Lankamp, Simon Polstra, An implementation of the SANE Virtual Processor using POSIX threads., Journal of Systems Architecture - Embedded Systems Design 55(3): 162-169 (2009)
Miguel Delgado, Daniel Sánchez, María-Amparo Vila, International journal of intelligent systems: Special issue on “fuzzy bags, cardinality, and quantification”, International Journal of Intelligent Systems , Volume 24 Issue 6, John Wiley & Sons, Inc., June 2009
Miguel Delgado, María-José Martín-Bautista, Daniel Sánchez, María-Amparo Vila, An extended characterization of fuzzy bags, International Journal of Intelligent Systems , Volume 24 Issue 6, John Wiley & Sons, Inc., June 2009
Mikael Collin, Mats Brorsson, Two-Level Dictionary Code Compression: A New Scheme to Improve Instruction Code Density of Embedded Applications, Proceedings of the 2009 International Symposium on Code Generation and Optimization
Mikko Kohvakka, Jukka Suhonen, Mauri Kuorilehto, Ville Kaseva, Marko Hännikäinen, Timo D. Hämäläinen, Energy-efficient neighbor discovery protocol for mobile wireless sensor networks., Ad Hoc Networks 7(1): 24-41 (2009)
Mikko Majanen, Pekka H. J. Perälä, Thomas Casey, Jari Nurmi, Nenad Veselinovic, Mobile WiMAX Handover Performance Evaluation., ICNS 2009: 263-269
Miljana Sokolovic, Vanco B. Litovski, Mark Zwolinski, New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits., Microelectronics Reliability 49(2): 186-198 (2009)
Ming-che Lai, Lei Gao, Nong Xiao, Zhiying Wang, An accurate and efficient performance analysis approach based on queuing model for network on chip., ICCAD 2009: 563-570
Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Rizos Sakellariou, Mateo Valero, FlexDCP: a QoS framework for CMP architectures, SIGOPS Operating Systems Review , Volume 43 Issue 2, ACM, April 2009
Miriam Allalouf, Michael Factor, Dror G. Feitelson, Proceedings of of SYSTOR 2009: The Israeli Experimental Systems Conference 2009 Haifa Israel May 4-6 2009, ACM 2009
Mladen Berekovic, Andreas Kanstein, Bingfeng Mei, Bjorn De Sutter, Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor, Microprocessors & Microsystems , Volume 33 Issue 4, Elsevier Science Publishers B. V., June 2009
Mladen Berekovic, Christian Müller-Schloer, Christian Hochberger, Stephan Wong, Architecture of Computing Systems - ARCS 2009 22nd International Conference Delft The Netherlands March 10-13 2009. Proceedings, Springer 2009
Mladen Berekovic, Frank Bouwens, Tom Aa, Diederik Verkest, Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Springer-Verlag, January 2009
Mladen Berekovic, Vipin Chaudhary, Alex Dean, Jason Fritts, Editorial, Microprocessors & Microsystems , Volume 33 Issue 4, Elsevier Science Publishers B. V., June 2009
Mohammad Ansari, Kim Jarvis, Christos Kotselidis, Mikel Luján, Chris C. Kirkham, Ian Watson, Profiling Transactional Memory Applications., PDP 2009: 11-20
Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris C. Kirkham, Ian Watson, Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering., HiPEAC 2009: 4-18
Mohammed Fellahi, Albert Cohen, Software Pipelining in Nested Loops with Prolog-Epilog Merging., HiPEAC 2009: 80-94
Mojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels, Compiler assisted runtime task scheduling on a reconfigurable computer., FPL 2009: 44-50
Montserrat Boo, Margarita Amor, Dynamic hybrid terrain representation based on convexity limits identification, International Journal of Geographical Information Science , Volume 23 Issue 4, Taylor & Francis, Inc., April 2009
Mounira Bachir, David Gregg, Sid Ahmed Ali Touati, Using the Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops., LCPC 2009: 278-292
Muhammad Aqeel Wahlah, Kees Goossens, Modeling reconfiguration in a FPGA with a hardwired network on chip, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Muhammad Mukaram Khan, Javier Navaridas Palma, Alexander D. Rast, Xin Jin, Luis A. Plana, Mikel Lujan, John Viv Woods, Jose Miguel-Alonso, Steve B. Furber, Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric, ISPDC '09: Proceedings of the 2009 Eighth International Symposium on Parallel and Distributed Computing - Volume 00 , Volume 00, IEEE Computer Society, June 2009
Muhammad Mukaram Khan, Javier Navaridas, Alexander D. Rast, Xin Jin, Luis A. Plana, Mikel Luján, John V. Woods, José Miguel-Alonso, Steve Furber, Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric., ISPDC 2009: 54-61
Muhammad Rashid, Fabrizio Ferrandi, Koen Bertels, hArtes design flow for heterogeneous platforms., ISQED 2009: 330-338
Muhammad Shafiq, Miquel Pericas, Nacho Navarro, Eduard Ayguade, A Streaming Based High Performance FPGA Core for 3D Reverse Time Migrationrn, HiPEAC - ACACES
Muhammad Shafiq, Miquel Pericas, Nacho Navarro, Eduard Ayguade, Three-dimensional memory organization for stencil computations in FPGA, ASIP and ASIC, UPC-DAC
Muhammad Shafiq, Raul de la Cruz, Mauricio Araya Polo, Miquel Pericas, Nacho Navarro, Eduard Ayguade, Exploiting Memory Customization in FPGA for 3D Stencil Computationsrn, IEEE FPT
N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung, Compensating for variability in FPGAs by re-mapping and re-placement., FPL 2009: 613-616
Nathan Grasso Bronson, Christos Kozyrakis, Kunle Olukotun, Feedback-directed barrier optimization in a strongly isolated STM., POPL 2009: 213-225
Nehir Sonmez, Tim Harris, Adrian Cristal, Osman S. Unsal, Mateo Valero, Taking the heat off transactions: Dynamic selection of pessimistic concurrency control, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Nestor Suarez Alfonso, Gustavo M.Callico, Roberto Sarmiento, Octavio Santana, Anteneh A. Abbo, Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks., PATMOS 2009: 326-335
Nick-Barrow Williams, Christian Fensch, Simon Moore, A Communication Characterisation of Splash-2 and Parsec, IEEE
Nicolas Fournel, Antoine Fraboulet, Paul Feautrier, Embedded software energy characterization: Using non-intrusive measures for application source code annotation., J. Embedded Computing 3(3): 179-188 (2009)
Niklas Holsti, Guillem Bernat, Christian Ferdinand, Peter P. Puschner, Reinhard Wilhelm, Teaching WCET Analysis in Academia and Industry: A Panel Discussion., WCET 2009
Nikola Vujic, Lluc Alvarez, Marc González Tallada, Xavier Martorell, Eduard Ayguadé, Adaptive and Speculative Memory Consistency Support for Multi-core Architectures with On-Chip Local Memories., LCPC 2009: 218-232
Nikolaos Drosinos, Nectarios Koziris, Efficient hybrid parallelisation of tiled algorithms on SMP clusters, International Journal of Computational Science and Engineering , Volume 4 Issue 2, Inderscience Publishers, July 2009
Nikolaos Zompakis, Martin Trautmann, Alexandros Bartzas, Stylianos Mamagkakis, Dimitrios Soudris, Liesbet Van der Perre, Francky Catthoor, Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms., PATMOS 2009: 165-174
Nor Zaidi Haron, Said Hamdioui, Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories., DFT 2009: 85-93
Nor Zaidi Haron, Said Hamdioui, Sorin Cotofana, Emerging non-CMOS nanoelectronic devices - What are they?., NEMS 2009: 63-68
Norman W. Paton, Marcelo A. T. Aragão, Kevin Lee, Alvaro A. A. Fernandes, Rizos Sakellariou, Optimizing Utility in Cloud Computing through Autonomic Workload Execution., IEEE Data Eng. Bull. 32(1): 51-58 (2009)
Oana Florescu, Jeroen Voeten, Bart Theelen, Henk Corporaal, Patterns for Automatic Generation of Soft Real-time System Models, Simulation , Volume 85 Issue 11-12, Society for Computer Simulation International, November 2009
Oliverio J. Santana, Ayose Falcón, Alex Ramirez, Mateo Valero, DIA: A Complexity-Effective Decoding Architecture, IEEE Transactions on Computers , Volume 58 Issue 4, IEEE Computer Society, April 2009
Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero, A Comprehensive Analysis of Indirect Branch Prediction, ISHPC '02: Proceedings of the 4th International Symposium on High Performance Computing, Springer-Verlag, May 2009
Omer Duskin, Dror G. Feitelson, Distinguishing humans from robots in web search logs: preliminary results using query rates and intervals, WSCD '09: Proceedings of the 2009 workshop on Web Search Click Data, ACM, February 2009
Ozana Silvia Dragomir, Todor Stefanov, Koen Bertels, Optimal Loop Unrolling and Shifting for Reconfigurable Architectures, Transactions on Reconfigurable Technology and Systems (TRETS) , Volume 2 Issue 4, ACM, September 2009
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Using Data Compression for Increasing Memory System Utilization., IEEE Trans. on CAD of Integrated Circuits and Systems 28(6): 901-914 (2009)
Ozcan Ozturk, Mahmut T. Kandemir, Seung Woo Son, Ibrahim Kolcu, Shared scratch pad memory space management across applications., IJES 4(1): 54-65 (2009)
Pablo Abad, Valentin Puente, Jos?-?ngel Gregorio, MRR: Enabling fully adaptive multicast routing for CMP interconnection networks., HPCA 2009: 355-366
Panagiota Fatourou, Nikolaos D. Kallimanis, The RedBlue Adaptive Universal Constructions., DISC 2009: 127-141
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Memory organization and data layout for instruction set extensions with architecturally visible storage., ICCAD 2009: 689-696
Pao-Ann Hsiung, Marco D. Santambrogio, Chun-Hsian Huang, Reconfigurable System Design and Verification, 1st edition, Reconfigurable System Design and Verification, 1st edition, CRC Press, Inc., February 2009
Paolo Bientinesi, Francisco D. Igual, Daniel Kressner, Enrique S. Quintana-Ortí, Reduction to Condensed Forms for Symmetric Eigenvalue Problems on Multi-core Architectures., PPAM (1) 2009: 387-395
Pascal Felber, Ernst W. Biersack, Peer-To-Peer Content Distribution., Encyclopedia of Database Systems 2009: 2061-2065
Pascal Felber, Vincent Gramoli, Rachid Guerraoui, Elastic Transactions., DISC 2009: 93-107
Patrick Bellasi, William Fornaciari, David Siorpaes, Predictive models for multimedia applications power consumption based on use-case and OS level analysis., DATE 2009: 1446-1451
Paul Biggar, Edsko de Vries, David Gregg, A practical solution for scripting language compilers., SAC 2009: 1916-1923
Paul Chow, Peter Y. K. Cheung, Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays FPGA 2009 Monterey California USA February 22-24 2009, ACM 2009
Paul Lokuciejewski, Peter Marwedel, Combining Worst-Case Timing Models Loop Unrolling and Static Loop Analysis for WCET Minimization., ECRTS 2009: 35-44
Paula Cecilia Fritzsche, Ronal Muresano, Dolores Rexachs, Emilio Luque, An assessment of multi-core for a performance prediction model of tomographic reconstruction., CLUSTER 2009: 1-4
Pavlos Petoumenos, Georgios Keramidas, Stefanos Kaxiras, Instruction-based reuse-distance prediction for effective cache management., ICSAMOS 2009: 49-58
Pedro C. Diniz, Guest Editorial., Concurrency and Computation: Practice and Experience 21(1): 1-3 (2009)
Pedro C. Diniz, Ben Juurlink, Alain Darte, Wolfgang Karl, Introduction, Euro-Par '09: Proceedings of the 15th International Euro-Par Conference on Parallel Processing, Springer-Verlag, August 2009
Pedro Diaz, Marcelo Cintra, Stream chaining: exploiting multiple levels of correlation in data prefetching, ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture, ACM, June 2009
Pedro Morillo, Juan M. Orduña, José Duato, M-GRASP: A GRASP With Memory for Latency-Aware Partitioning Methods in DVE Systems., IEEE Transactions on Systems Man and Cybernetics Part A 39(6): 1214-1223 (2009)
Pedro Tomás, Leonel Augusto Sousa, A Feature Selection Algorithm for the Regularization of Neuron Models., IEEE T. Instrumentation and Measurement 58(11): 3824-3830 (2009)
Pedro Trancoso, Despo Othonos, Artemakis Artemiou, Data parallel acceleration of decision support queries using Cell/BE and GPUs., Conf. Computing Frontiers 2009: 117-126
Pepijn Langen, Ben Juurlink, Leakage-Aware Multiprocessor Scheduling, Journal of Signal Processing Systems , Volume 57 Issue 1, Kluwer Academic Publishers, October 2009
Per Larsen, Sven Karlsson, Jan Madsen, Identifying Inter-task Communication in Shared Memory Programming Models., IWOMP 2009: 168-182
Per Stenström, Transactions on High-Performance Embedded Architectures and Compilers II , Springer 2009
Per Stenström, David B. Whalley, Introduction., T. HiPEAC 2: 3 (2009)
Peter Benner, Pablo Ezzatti, Enrique S. Quintana-Ortí, Alfredo Remón, Using Hybrid CPU-GPU Platforms to Accelerate the Computation of the Matrix Sign Function., Euro-Par Workshops 2009: 132-139
Peter Bertels, Michiel D'Haene, Tom Degryse, Dirk Stroobandt, Teaching skills and concepts for embedded systems design, SIGBED Review , Volume 6 Issue 1, ACM, January 2009
Peter Bertels, Wim Heirman, Dirk Stroobandt, Strategies for dynamic memory allocation in hybrid architectures., Conf. Computing Frontiers 2009: 217-220
Peter Bertels, Wim Heirman, Erik D'Hollander, Dirk Stroobandt, Efficient memory management for hardware accelerated Java Virtual Machines, Transactions on Design Automation of Electronic Systems (TODAES) , Volume 14 Issue 4, ACM, August 2009
Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen, Benchmarking Reconfigurable Architectures in the Mobile Domain., FCCM 2009: 131-138
Peter Marwedel, Plädoyer für eine ganzheitliche Betrachtung des Zusammenhangs zwischen Informationstechnologie und CO2-Produktion., GI Jahrestagung 2009: 273
Peter Molnar, Andreas Krall, Florian Brandner, Stack allocation of objects in the CACAO virtual machine, PPPJ '09: Proceedings of the 7th International Conference on Principles and Practice of Programming in Java, ACM, August 2009
Philippe Clauss, Federico Javier Fernández, Diego Garbervetsky, Sven Verdoolaege, Symbolic Polynomial Maximization Over Convex Sets and Its Application to Memory Requirement Estimation., IEEE Trans. VLSI Syst. 17(8): 983-996 (2009)
Philippe Grosse, Yves Durand, Paul Feautrier, Methods for power optimization in SOC-based data flow systems., ACM Trans. Design Autom. Electr. Syst. 14(3): (2009)
Pierre Michaud, Online compression of cache-filtered address traces., ISPASS 2009: 185-194
Pieter Bellens, Josep M. Perez, Felipe Cabarcas, Alex Ramirez, Rosa M. Badia, Jesus Labarta, CellSs: Scheduling techniques to better exploit memory hierarchy, Scientific Programming , Volume 17 Issue 1-2, IOS Press, January 2009
Polychronis Xekalakis, Nikolas Ioannou, Marcelo Cintra, Combining thread level speculation helper threads and runahead execution., ICS 2009: 410-420
Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures., IEEE Trans. Computers 58(3): 311-321 (2009)
Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, EMPIRE: Empirical power/area/timing models for register files., Microprocessors and Microsystems - Embedded Hardware Design 33(4): 295-300 (2009)
Praveen Raghavan, Francky Catthoor, Register file exploration for a multi-standard wireless forward error correction ASIP., SiPS 2009: 024-029
Praveen Raghavan, Francky Catthoor, SARA: StreAm register allocation., CODES+ISSS 2009: 41-50
Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor, Playing the trade-off game: Architecture exploration using Coffeee., ACM Trans. Design Autom. Electr. Syst. 14(3): (2009)
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung, Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework., IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 305-315 (2009)
Qiang Liu, Tim Todman, José Gabriel de F. Coutinho, Wayne Luk, George A. Constantinides, Optimising designs by combining model-based and pattern-based transformations., FPL 2009: 308-313
Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope, Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models, Transactions on Reconfigurable Technology and Systems (TRETS) , Volume 2 Issue 4, ACM, September 2009
R. Castillo, F. Corbera, A. Navarro, R. Asenjo, E. L. Zapata, Complete Def-Use Analysis in Recursive Programs with Dynamic Data Structures, Euro-Par 2008 Workshops - Parallel Processing, Springer-Verlag, April 2009
Raúl Peña-Ortiz, Julio Sahuquillo, Ana Pont, José A. Gil, Dweb model: Representing Web 2.0 dynamism, Computer Communications , Volume 32 Issue 6, Butterworth-Heinemann, April 2009
Rafael Tornero, Shashi Kumar, Saad Mubeen, Juan Manuel Orduña, Distance Constrained Mapping to Support NoC Platforms Based on Source Routing., Euro-Par Workshops 2009: 16-25
Rafael Tornero, Valentino Sterrantino, Maurizio Palesi, Juan M. Orduna, A multi-objective strategy for concurrent mapping and routing in networks on chip, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Rainer Buchty, David Kramer, Fabian Nowak, Wolfgang Karl, A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems., ARC 2009: 362-367
Rainer Buchty, David Kramer, Mario Kicherer, Wolfgang Karl, A Light-Weight Approach to Dynamical Runtime Linking Supporting Heterogenous Parallel and Reconfigurable Architectures., ARCS 2009: 60-71
Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl, An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems, SAMOS '09: Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, Springer-Verlag, July 2009
Rajendra P. Srivastava, Lei Gao, Peter R. Gillett, Representation of interrelationships among binary variables under dempster-shafer theory of belief functions., Int. J. Intell. Syst. 24(4): 459-475 (2009)
Raymond Manley, David Gregg, Mapping Streaming Languages to General Purpose Processors through Vectorization., LCPC 2009: 95-110
Riadh Ben Abdallah, Tanguy Risset, Antoine Fraboulet, Yves Durand, The Radio Virtual Machine: A solution for SDR portability and platform reconfigurability, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Ricardo Ferreira, Alex Damiany, Julio Vendramini, Tiago Teixeira, João M. P. Cardoso, On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks., ARC 2009: 145-156
Ricardo Menotti, João M. P. Cardoso, Marcio Merino Fernandes, Eduardo Marques, Automatic generation of FPGA hardware accelerators using a domain specific language., FPL 2009: 457-461
Ricardo Quislant, Eladio Gutiérrez, Oscar G. Plata, Emilio L. Zapata, Improving Signatures by Locality Exploitation for Transactional Memory., PACT 2009: 303-312
Rickard Holsmark, Shashi Kumar, Maurizio Palesi, Andres Mejia, HiRA: A methodology for deadlock free routing in hierarchical networks on chip., NOCS 2009: 2-11
Rob Hoes, Twan Basten, Wai-Leong Yeow, Chen-Khong Tham, Marc Geilen, Henk Corporaal, QoS Management for Wireless Sensor Networks with a Mobile Sink., EWSN 2009: 53-68
Robert Fasthuber, Min Li, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor, Novel energy-efficient scalable soft-output SSFE MIMO detector architectures., ICSAMOS 2009: 165-171
Roberto Cordone, Francesco Redaelli, Massimo Antonio Redaelli, Marco Domenico Santambrogio, Donatella Sciuto, Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Volume 28 Issue 5, Institute of Electrical and Electronics Engineers Inc., The, May 2009
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Introducing Hardware TLP Support in the Cell Processor., CISIS 2009: 657-662
Roberto Morales, Marisa Gil, CARM: Composable, Adaptive Resource Management System in Ubiquitous Computing Environments, Advances in Soft Computing. Springer Berlin/Heidelberg
Roberto R. Osorio, Javier D. Bruguera, High Performance Image Processing on a Massively Parallel Processor Array, Euromicro Digital System Design (DSD)
Robin Von Haartman, Lars Bengtsson, Manufacturing competence: a key to successful supplier integration., IJMTM 16(3): 283-299 (2009)
Rodrigo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado, Stack oriented data cache filtering, CODES+ISSS '09: Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, ACM, October 2009
Roger Ferrer, Alejandro Duran, Xavier Martorell, Eduard Ayguadé, Unrolling Loops Containing Task Parallelism., LCPC 2009: 416-423
Roger Ferrer, Vicenç Beltran, Marc González, Xavier Martorell, Eduard Ayguadé, Achieving high memory performance from heterogeneous architectures with the SARC programming model, MEDEA '09: Proceedings of the 10th MEDEA workshop on MEmory performance: DEaling with Applications, systems and architecture, ACM, September 2009
Ron Gabor, Avi Mendelson, Shlomo Weiss, Service level agreement for multithreaded processors, Transactions on Architecture and Code Optimization (TACO) , Volume 6 Issue 2, ACM, June 2009
Ronal Muresano, Dolores Rexachs, Emilio Luque, How SPMD applications could be efficiently executed on multicore environments?, CLUSTER 2009: 1-4
Rosa M. Badia, José R. Herrero, Jesús Labarta, Josep M. Pérez, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Parallelizing dense and banded linear algebra libraries using SMPSs, Concurrency and Computation: Practice & Experience , Volume 21 Issue 18, John Wiley and Sons Ltd., December 2009
Rosa M. Badia, José R. Herrero, Jesús Labarta, Josep M. Pérez, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Parallelizing dense and banded linear algebra libraries using SMPSs., Concurrency and Computation: Practice and Experience 21(18): 2438-2456 (2009)
Rosa M. Badia, Josep M. Pérez, Eduard Ayguadé, Jesús Labarta, Impact of the Memory Hierarchy on Shared Memory Architectures in Multicore Programming Models., PDP 2009: 437-445
Rosa Risueño, Pedro Cuenca, Francisco Delicado, Luis Orozco-Barbosa, On the effect of handover mechanisms on the performance of video communications in WATM networks., IJWMC 3(4): 320-336 (2009)
Rostislav (Reuven) Dobkin, Ran Ginosar, Two-phase synchronization with sub-cycle latency, Integration, the VLSI Journal , Volume 42 Issue 3, Elsevier Science Publishers B. V., June 2009
Rostislav (Reuven) Dobkin, Ran Ginosar, Fast Universal Synchronizers, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Springer-Verlag, January 2009
Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny, QNoC asynchronous router, Integration, the VLSI Journal , Volume 42 Issue 2, Elsevier Science Publishers B. V., February 2009
Roya Choupani, Stephan Wong, Mehmet R. Tolun, A Drift-Reduced Hierarchical Wavelet Coding Scheme for Scalable Video Transmissions., MMEDIA 2009: 68-73
Rubén Gran Tejero, Enric Morancho, Angel Olive, José María Llabería, On Reducing Misspeculations on a Pipelined Scheduler, 23 IEEE International Parallel & Distributed Processing Symposium
Rubing Duan, Farrukh Nadeem, Jie Wang, Yun Zhang, Radu Prodan, Thomas Fahringer, A Hybrid Intelligent Method for Performance Modeling and Prediction of Workflow Activities in Grids., CCGRID 2009: 339-347
Ruixing Yang, Lachlan Pockett, Jari Nurmi, Realization of Free Viewpoint TV Based on Improved MVC., FMN 2009: 143-151
Ryan Johnson, Ippokratis Pandis, Nikos Hardavellas, Anastasia Ailamaki, Babak Falsafi, Shore-MT: a scalable storage manager for the multicore era., EDBT 2009: 24-35
S. Arash Ostadzadeh, Roel Meeuws, Kamana Sigdel, Koen Bertels, A clustering framework for task partitioning based on function-level data usage analysis., FPGA 2009: 279
Sabina Serbu, Etienne Riviere, Pascal Felber, Network-Friendly Gossiping., SSS 2009: 655-669
Sabri Pllana, Jesper Larsson Träff, Introduction to the Scientific Programming Special Issue: Software Development for Multi-core Computing Systems., Scientific Programming 17(4): 283-284 (2009)
Sabri Pllana, Siegfried Benkner, Eduard Mehofer, Lasse Natvig, Fatos Xhafa, Towards an Intelligent Environment for Programming Multi-core Computing Systems , Springer-Verlag Berlin Heidelberg
Said Hamdioui, Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?., Asian Test Symposium 2009: 339
Salman Khan, Password detection via imagined wrist movement in BCI., IMCSIT 2009: 401-404
Salvador Petit Marti, Julio Sahuquillo Borrás, Pedro Lopez Rodriguez, Rafael Ubal Tena, José Duato Marín, A Complexity-Effective Out-of-Order Retirement Microarchitecture., IEEE Trans. Computers 58(12): 1626-1639 (2009)
Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier Temam, Reconciling specialization and flexibility through compound circuits., HPCA 2009: 277-288
Samuel Antao, Ricardo Chaves, Leonel Sousa, Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices., FCCM 2009: 193-200
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero, EazyHTM: eager-lazy hardware transactional memory., MICRO 2009: 145-155
Sascha Plazar, Paul Lokuciejewski, Peter Marwedel, WCET-aware Software Based Cache Partitioning for Multi-Task Real-Time Systems., WCET 2009
Sascha Uhrig, Theo Ungerer, A Garbage Collection Technique for Embedded Multithreaded Multicore Processors., ARCS 2009: 207-218
Scott Schneider, Jae-Seung Yeom, Benjamin Rose, John C. Linford, Adrian Sandu, Dimitrios S. Nikolopoulos, A comparison of programming models for multiprocessors with explicitly managed memory hierarchies., PPOPP 2009: 131-140
Sean Rul, Hans Vandierendonck, Koen De Bosschere, Towards automatic program partitioning., Conf. Computing Frontiers 2009: 89-98
Sebastian Lopez, Gustavo M. Callico, Félix Tobajas, Jose F. Lopez, Roberto Sarmiento, A Novel Real-Time DSP-Based Video Super-Resolution System, IEEE Transaction on Consumer Electronics
Sergio Barrachina, Maribel Castillo, Francisco D. Igual, Rafael Mayo, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Exploiting the capabilities of modern GPUs for dense matrix computations., Concurrency and Computation: Practice and Experience 21(18): 2457-2477 (2009)
Sergio Saponara, Nicola E. L'Insalata, Luca Fanucci, Low-complexity FFT/IFFT IP hardware macrocells for OFDM and MIMO-OFDM CMOS transceivers, Microprocessors & Microsystems , Volume 33 Issue 3, Elsevier Science Publishers B. V., May 2009
Shelly Bansal, Daya Gupta, V. K. Panchal, Shashi Kumar, Swarm Intelligence Inspired Classifiers in Comparison with Fuzzy and Rough Classifiers: A Remote Sensing Approach., IC3 2009: 284-294
Shidhartha Das, David Blaauw, David Bull, Krisztián Flautner, Rob Aitken, Addressing design margins through error-tolerant circuits, DAC '09: Proceedings of the 46th Annual Design Automation Conference, ACM, July 2009
Shimin Chen, Michael Kozuch, Phillip B. Gibbons, Michael Ryan, Theodoros Strigkos, Todd C. Mowry, Olatunji Ruwase, Evangelos Vlachos, Babak Falsafi, Vijaya Ramachandran, Flexible Hardware Acceleration for Instruction-Grain Lifeguards, IEEE Micro , Volume 29 Issue 1, IEEE Computer Society Press, January 2009
Shinichi Yamagiwa, Leonel Sousa, Modelling and programming stream-based distributed computing based on the meta-pipeline approach., IJPEDS 24(4): 311-330 (2009)
Shinichi Yamagiwa, Leonel Sousa, CaravelaMPI: Message Passing Interface for Parallel GPU-Based Applications., ISPDC 2009: 161-168
Shun Long, Grigori Fursin, Systematic search within an optimisation space based on Unified Transformation Framework, International Journal of Computational Science and Engineering , Volume 4 Issue 2, Inderscience Publishers, July 2009
Sijian Zhang, Gangfeng Yan, Weihua Sheng, Viewpoint planning for automated 3D digitization using a low-cost mobile platform., IROS 2009: 4369-4374
Simon Kluyskens, Lieven Eeckhout, Branch Predictor Warmup for Sampled Simulation through Branch History Matching., T. HiPEAC 2: 45-64 (2009)
Simone Campanoni, Stefano Crespi Reghizzi, Traces of control-flow graphs, DLT 2009, Stuttgart University, Germany, June, 2009., Springer
Simone Campanoni, Stefano Crespi-Reghizzi, Traces of Control-Flow Graphs., Developments in Language Theory 2009: 156-169
Simone Corbetta, Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini, Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration., IEEE Trans. VLSI Syst. 17(11): 1650-1654 (2009)
Sotiris Ioannidis, Evangelos P. Markatos, Christopher Kruegel, On looking FORWARD., ERCIM News 2009(76): (2009)
Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli, Synthesis of networks on chips for 3D systems on chips, ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, IEEE Press, January 2009
Stavros Passas, Kostas Magoutis, Angelos Bilas, Towards 100 gbit/s ethernet: multicore-based parallel communication protocol design., ICS 2009: 214-224
Stefan Valentin Gheorghita, Martin Palkovic, Juan Hamers, Arnout Vandecappelle, Stelios Mamagkakis, Twan Basten, Lieven Eeckhout, Henk Corporaal, Francky Catthoor, Frederik Vandeputte, Koen De Bossche, System-scenario-based design of dynamic embedded systems., ACM Trans. Design Autom. Electr. Syst. 13(1): (2009)
Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich, Self-organizing multi-cue fusion for FPGA-based embedded imaging., FPL 2009: 132-137
Stefanos Gritzalis, Dimitris Plexousakis, Dionisios N. Pnevmatikatos, PCI 2009 13th Panhellenic Conference on Informatics 10-12 September 2009 Corfu Greece, IEEE Computer Society 2009
Stephanie Drzevitzky, Uwe Kastens, Marco Platzner, Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules., ReConFig 2009: 189-194
Steven J. Lynden, Arijit Mukherjee, Alastair C. Hume, Alvaro A. A. Fernandes, Norman W. Paton, Rizos Sakellariou, Paul Watson, The design and implementation of OGSA-DQP: A service-based distributed query processor., Future Generation Comp. Syst. 25(3): 224-236 (2009)
Stijn Eyerman, Lieven Eeckhout, Memory-level parallelism aware fetch policies for simultaneous multithreading processors., TACO 6(1): (2009)
Stijn Eyerman, Lieven Eeckhout, Per-thread cycle accounting in SMT processors., ASPLOS 2009: 133-144
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith, A mechanistic performance model for superscalar out-of-order processors., ACM Trans. Comput. Syst. 27(2): (2009)
Sutirtha Sanyal, Sourav Roy, Adrian Cristal, Osman S. Unsal, Mateo Valero, Clock gate on abort: Towards energy-efficient hardware Transactional Memory, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Sutirtha Sanyal, Sourav Roy, Adrian Cristal, Osman S. Unsal, Mateo Valero, Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory, HPCC '09: Proceedings of the 2009 11th IEEE International Conference on High Performance Computing and Communications - Volume 00 , Volume 00, IEEE Computer Society, June 2009
Svetislav Momcilovic, Leonel Sousa, Development and evaluation of scalable video motion estimators on GPU., SiPS 2009: 291-296
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero, Code Semantic-Aware Runahead Threads., ICPP 2009: 437-444
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel Lacassagne, Daniel Etiemble, Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor, PACT '09: Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques - Volume 00 , Volume 00, IEEE Computer Society, September 2009
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel Lacassagne, Daniel Etiemble, Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor., PACT 2009: 67-76
Tarik Saidani, Joel Falcou, Lionel Lacassagne, Claude Tadonki, Daniel Etiemble, Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor, PACT
Tariq Abdullah, Koen Bertels, Luc Onana Alima, Ant Colony Inspired Microeconomic Based Resource Management in Ad Hoc Grids., GPC 2009: 189-198
Tariq Abdullah, Lotfi Mhamdi, Behnaz Pourebrahimi, Koen Bertels, Resource Discovery with Dynamic Matchmakers in Ad Hoc Grid, ICONS '09: Proceedings of the 2009 Fourth International Conference on Systems, IEEE Computer Society, March 2009
Tariq Abdullah, Luc Onana Alima, Vassiliy Sokolov, David Calomme, Koen Bertels, Hybrid Resource Discovery Mechanism in Ad Hoc Grid Using Structured Overlay., ARCS 2009: 108-119
Teemu Laukkarinen, Ville Kaseva, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen, HybridKernel: Preemptive kernel with event-driven extension for resource constrained wireless sensor networks., SiPS 2009: 161-166
Teemu Pitkänen, Jarmo Takala, Low-power application-specific processor for FFT computations., ICASSP 2009: 593-596
Tero Arpinen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen, Performance Evaluation of UML2-Modeled Embedded Streaming Applications with System-Level Simulation., EURASIP J. Emb. Sys. 2009: (2009)
Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne, MPSoC Design Using Application-Specific Architecturally Visible Communication., HiPEAC 2009: 183-197
Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos, Practical off-chip meta-data for temporal memory streaming., HPCA 2009: 79-90
Thomas Schilling, Magnus Själander, Per Larsson-Edefors, Scheduling for an Embedded Architecture with a Flexible Datapath., ISVLSI 2009: 151-156
Thomas Schilling, Magnus Sjalander, Per Larsson-Edefors, Scheduling for an Embedded Architecture with a Flexible Datapath, ISVLSI '09: Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI - Volume 00 , Volume 00, IEEE Computer Society, May 2009
Thomas Weigold, Marco Aldinucci, Marco Danelutto, Vladimir Getov, Integrating Autonomic Grid Components and Process-Driven Business Applications., Autonomics 2009: 96-113
Tim Harris, Language constructs for transactional memory., POPL 2009: 1
Tim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk, Smart Enumeration: A Systematic Approach to Exhaustive Search, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, Springer-Verlag, January 2009
Timothy Jones, Ramesh S. Sankaranarayana, David Hawking, Nick Craswell, Nullification test collections for web spam and SEO., AIRWeb 2009: 53-60
Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oğuz Ergin, Energy-efficient register caching with compiler assistance, Transactions on Architecture and Code Optimization (TACO) , Volume 6 Issue 4, ACM, October 2009
Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Parametric Design for Reconfigurable Software-Defined Radio., ARC 2009: 15-26
Tobias Schumacher, Christian Plessl, Marco Platzner, IMORC: Application Mapping Monitoring and Optimization for High-Performance Reconfigurable Computing., FCCM 2009: 275-278
Tobias Schumacher, Christian Plessl, Marco Platzner, An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure., FPL 2009: 338-344
Tobias Schumacher, Tim Suss, Christian Plessl, Marco Platzner, Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000., ReConFig 2009: 119-124
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney, Producing wrong data without doing anything obviously wrong!, ASPLOS 2009: 265-276
Tom Crick, Martin Brain, Marina De Vos, John Fitch, Generating Optimal Code Using Answer Set Programming., LPNMR 2009: 554-559
Tommaso Cucinotta, Antonio Mancina, Gaetano Anastasi, Giuseppe Lipari, Leonardo Mangeruca, Roberto Checcozzo, Fulvio Rusina, A Real-time Service-Oriented Architecture for Industrial Automation., IEEE Trans. Industrial Informatics 5(3): 267-277 (2009)
Tommaso Cucinotta, Gaetano Anastasi, Luca Abeni, Respecting Temporal Constraints in Virtualised Services., COMPSAC (2) 2009: 73-78
Tommaso Cucinotta, Kleopatra Konstanteli, Theodora A. Varvarigou, Advance reservations for distributed real-time workflows with probabilistic service guarantees., SOCA 2009: 1-8
Tommaso Cucinotta, Luca Abeni, Luigi Palopoli, Fabio Checconi, The wizard of OS: a heartbeat for Legacy multimedia applications., ESTImedia 2009: 70-79
Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios., VLSI Design 2009: 281-286
Tung Thanh Hoang, Magnus Sjalander, Per Larsson-Edefors, Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Uwe Brinkschulte, Model-Driven Design and Organic Computing - Contradictory or Synergetic Approaches to Overcome the Embedded Software Crisis., ISORC 2009: 91-92
Uwe Brinkschulte, Vorwort der Workshop-Leitung., GI Jahrestagung 2009: 270-271
Uwe Brinkschulte, Marcello Cinque, Tony Givargis, Stefano Russo, Guest Editorial., JSW 4(7): 631-633 (2009)
Víctor J. Jiménez, Lluís Vilanova, Isaac Gelado, Marisa Gil, Grigori Fursin, Nacho Navarro, Predictive Runtime Code Scheduling for Heterogeneous Architectures., HiPEAC 2009: 19-33
Vahid Lari, Frank Hannig, Jürgen Teich, System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance., ICPP Workshops 2009: 528-534
Vasilis F. Pavlidis, Giovanni De Micheli, Power distribution paths in 3-D ICS., ACM Great Lakes Symposium on VLSI 2009: 263-268
Vassos Soteriou, Rohit Sunkam Ramanujam, Bill Lin, Li-Shiuan Peh, A High-Throughput Distributed Shared-Buffer NoC Router., Computer Architecture Letters 8(1): 21-24 (2009)
Venkateswaran Nagarajan, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundrajan, T. P. Ramnath Sai Sagar, Madhavan Manivannan, Sriram Murali, Vinoth Krishnan Elangovan, Towards modeling and integrated design automation of supercomputing clusters (MIDAS)., Computer Science - R&D 24(1-2): 1-10 (2009)
Vicenç Beltran, David Carrera, Jordi Torres, Eduard Ayguadé, CellMT: A cooperative multithreading library for the Cell/B.E., HiPC 2009: 245-253
Vijay Janapa Reddi, Simone Campanoni, Meeta Sharma Gupta, Michael D. Smith, Gu-Yeon Wei, David M. Brooks, Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack., DAC 2009: 788-793
Ville Kaseva, Timo D. Hämäläinen, Marko Hännikäinen, Robust tree construction and maintenance for global time synchronization protocols in Wireless Sensor Networks., SiPS 2009: 197-201
Vimal Mehta, Weihua Sheng, Tianzhou Chen, Quan Shi, Development and calibration of a low cost wireless camera sensor network., IROS 2009: 110-115
Vinay Gidwani, Yi Lu, Donna D. Zhang, Pak Kin Wong, Nanoengineered platforms for cancer chemoprevention., NEMS 2009: 832-836
Vlad Nae, Radu Prodan, Thomas Fahringer, Monitoring and Fault Tolerance for Real-Time Online Interactive Applications., Euro-Par Workshops 2009: 255-265
Vlad-Mihai Sima, Koen Bertels, Runtime decision of hardware or software execution on a heterogeneous reconfigurable platform, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Vladimír Guzma, Teemu Pitkänen, Pertti Kellomäki, Jarmo Takala, Reducing processor energy consumption by compiler optimization., SiPS 2009: 063-068
Vladimir ?akarevi?, Petar Radojkovi?, Javier Verdu, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero, Characterizing the Resource-Sharing Levels in the UltraSPARC T2 Processorrn, ACM - MICRO '09
Vladimir Gajinov, Ferad Zyulkyarov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Tim Harris, Mateo Valero, QuakeTM: parallelizing a complex sequential application using transactional memory., ICS 2009: 126-135
W. Bielecki, T. Klimek, Konrad Trifunovic, Calculating Exact Transitive Closure for a Normalized Affine Integer Tuple Relation., Electronic Notes in Discrete Mathematics 33: 7-14 (2009)
W. Y. Chin, Evangelos P. Markatos, Spyros Antonatos, Sotiris Ioannidis, HoneyLab: Large-Scale Honeypot Deployment and Resource Sharing., NSS 2009: 381-388
Wojciech Kabaciński, Jiajia Chen, Grzegorz Danilewicz, Janusz Kleban, Maria Spyropoulou, Ioannis Tomkos, Emmanouel Varvarigos, Kyriakos Vlachos, Slawomir Wêclewski, Lena Wosinska, Konstantin, Novel Switch Architectures, Towards Digital Optical Networks, Springer-Verlag, April 2009
Wolfgang Karl, Djamshid Tavangarian, Ulrike Lucke, Vorwort der Workshop-Leitung., GI Jahrestagung 2009: 220-223
X. Dutoit, B. Schrauwen, J. Van Campenhout, D. Stroobandt, H. Van Brussel, M. Nuttin, Pruning and regularization in reservoir computing, Neurocomputing , Volume 72 Issue 7-9, Elsevier Science Publishers B. V., March 2009
Xavier Teruel, Christopher Barton, Alejandro Duran, Xavier Martorell, Eduard Ayguadé, Priya Unnikrishnan, Guansong Zhang, Raúl Silvera, OpenMP tasking analysis for programmers., CASCON 2009: 32-42
Xoán C. Pardo, María J. Martín, José Sanjurjo, Carlos V. Regueiro, Teaching Digital Systems in the Context of the New European Higher Education Area: A Practical Experience., IEEE Trans. Education 52(4): 513-523 (2009)
Yi Lu, Balaji Prabhakar, Robust Counting Via Counter Braids: An Error-Resilient Network Measurement Architecture., INFOCOM 2009: 522-530
Yi Lu, Bo Hu, Analyzing kinematics and solving active/constrained forces of a 4-dof 3SPS+SP parallel manipulator., Robotica 27(1): 29-36 (2009)
Yi Lu, Bo Hu, Tao Sun, Analyses of velocity acceleration statics and workspace of a 2(3-SPR) serial-parallel manipulator., Robotica 27(4): 529-538 (2009)
Yi Lu, Ming Zhang, Yan Shi, Jianping Yu, Kinematics and statics analysis of a novel 4-dof 2SPS+2SPR parallel manipulator and solving its workspace., Robotica 27(5): 771-778 (2009)
Yi Lu, Thomas Marconi, Koen Bertels, Georgi Gaydadjiev, Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems., ARC 2009: 216-230
Yi Lu, Yan Shi, Jianping Yu, Kinematic analysis of limited-dof parallel manipulators based on translational/rotational Jacobian and Hessian matrices., Robotica 27(7): 971-980 (2009)
Yiouli Kritikou, Giorgos Dimitrakopoulos, E. Dimitrellou, Panagiotis Demestichas, A management scheme for improving transportation efficiency and contributing to the enhancement of the social fabric., Telematics and Informatics 26(4): 375-390 (2009)
Yoav Etsion, Tal Ben-Nun, Dror G. Feitelson, A global scheduling framework for virtualization environments, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Yolanda Becerra, David Carrera, Eduard Ayguadé, Batch Job Profiling and Adaptive Profile Enforcement for Virtualized Environments., PDP 2009: 414-418
Yolanda Becerra, Vicenç Beltran, David Carrera, Marc González, Jordi Torres, Eduard Ayguadé, Speeding Up Distributed MapReduce Applications Using Hardware Accelerators., ICPP 2009: 42-49
Yoonseo Choi, Yuan Lin, Nathan Chong, Scott A. Mahlke, Trevor N. Mudge, Stream Compilation for Real-Time Embedded Multicore Systems., CGO 2009: 210-220
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz Ergin, Reducing parity generation latency through input value aware circuits., ACM Great Lakes Symposium on VLSI 2009: 109-112
Zaid Al-Ars, Said Hamdioui, Fault Diagnosis Using Test Primitives in Random Access Memories., Asian Test Symposium 2009: 403-408
Zheng Wang, Michael F. P. O'Boyle, Mapping parallelism to multi-cores: a machine learning based approach., PPOPP 2009: 75-84
Zheng Wang, Michael O'Boyle , Mapping Parallelism to Multi-cores: A Machine Learning Based Approach, 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)
Zoltán Herczeg, Daniel Schmidt, Ákos Kiss, Norbert Wehn, Tibor Gyimóthy, Energy simulation of embedded XScale systems with XEEMU., J. Embedded Computing 3(3): 209-219 (2009)
Zubair Nawaz, Thomas Marconi, Koen Bertels, Todor Stefanov, Flexible pipelining design for recursive variable expansion, IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, IEEE Computer Society, May 2009
Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser, Many-Core vs. Many-Thread Machines: Stay Away From the Valley, IEEE Computer Architecture Letters , Volume 8 Issue 1, IEEE Computer Society, January 2009

2010

Lei Gao, Guangda Li, Yantao Zheng, Richang Hong, Tat-Seng Chua, Video Reference: A Video Question Answering Engine., MMM 2010: 799-801
Roger Kahn, Shlomo Weiss, Reducing leakage power with BTB access prediction., Integration 43(1): 49-57 (2010)
Tobias J. K. Edler von Koch, Igor Böhm, Björn Franke, , Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions., CGO 2010: 180-189
Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi, Improved Design of High-Performance Parallel Decimal Multipliers., IEEE Trans. Computers 59(5): 679-693 (2010)
A. J. van de Goor, Georgi Gaydadjiev, Said Hamdioui, Memory testing with a RISC microcontroller., DATE 2010: 214-219
A. Makridakis, Elias Athanasopoulos, Spyros Antonatos, Demetres Antoniades, Sotiris Ioannidis, Evangelos P. Markatos, Understanding the behavior of malicious applications in social networks., IEEE Network 24(5): 14-19 (2010)
A. Roca, Jose Flich, F. Silla, J. Duato, VCTlite: towards an Efficient Implementation of Virtual Cut-Through Switching in On-chip Networks, HIPC
A. Strano, D. Ludovici, D. Bertozzi, A Library of Dual-Clock FIFOs for Cost-Effective and Flexible MPSoCs Design, Proceedings of SAMOS, pp. 20-27, Samos, Greece, July 2010.
Abdelhafid Mazouz, Sid Ahmed Ali Touati, Denis Barthou, Study of Variations of Native Program Execution Times on Multi-Core Architectures., CISIS 2010: 919-924
Abdelhafid Mazouz, Sid-Ahmed-Ali Touati, Denis Barthou, Study of Variations of Native Program Execution Times on Multi-Core Architectures, IEEE
Abdelillah Karouit, Abdelkrim Haqiq, Luis Orozco-Barbosa, A team study of the IEEE 802.16 collision resolution protocol., Wireless Days 2010: 1-6
Adam Betts, Nicholas Merriam, Guillem Bernat, Hybrid measurement-based WCET analysis at the source level using object-level traces., WCET 2010: 54-63
Adam Pocock, Paraskevas Yiapanis, Jeremy Singer, Mikel Luján, Gavin Brown, Online Non-stationary Boosting., MCS 2010: 205-214
Adriano K. Sanches, João M. P. Cardoso, On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates., FPL 2010: 267-270
Adrien Le Masle, Wayne Luk, Design space exploration of parametric pipelined designs., ASAP 2010: 47-54
Adrien Le Masle, Wayne Luk, Jared Eldredge, Kris Carver, Parametric Encryption Hardware Design., ARC 2010: 68-79
Ahsan Shabbir, Akash Kumar, Sander Stuijk, Bart Mesman, Henk Corporaal, CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications., Journal of Systems Architecture - Embedded Systems Design 56(7): 265-277 (2010)
Ahsan Shabbir, Sander Stuijk, Akash Kumar, Bart D. Theelen, Bart Mesman, Henk Corporaal, A predictable communication assist., Conf. Computing Frontiers 2010: 97-98
Aislan Gomide Foina, Javier Javier Ramirez Fernandez, Rosa M. Badia, Cell BE and Bluetooth applied to Digital TV., NOMS 2010: 825-828
Aislan Gomide Foina, Rosa M. Badia, Ahmed El-Deeb, Francisco Javier Ramirez Fernandez, Player Tracker - a tool to analyze sport players using RFID., PerCom Workshops 2010: 772-775
Ajay K. Verma, Philip Brisk, Paolo Ienne, Fast Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration., IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 341-354 (2010)
Akash Kumar, Bart Mesman, Henk Corporaal, Yajun Ha, Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems., IEEE Trans. on CAD of Integrated Circuits and Systems 29(4): 538-551 (2010)
Akin Tanatmis, Stefan Ruzika, Horst W. Hamacher, Mayur Punekar, Frank Kienle, Norbert Wehn, A separation algorithm for improved LP-decoding of linear block codes., IEEE Transactions on Information Theory 56(7): 3277-3289 (2010)
Alain Darte, Understanding loops: The influence of the decomposition of Karp Miller and Winograd., MEMOCODE 2010: 139-148
Alastair F. Donaldson, Daniel Kroening, Philipp Rümmer, Automatic Analysis of Scratch-Pad Memory Code for Heterogeneous Multicore Processors., TACAS 2010: 280-295
Alastair F. Donaldson, Simon J. Gay, Type inference and strong static type checking for Promela., Sci. Comput. Program. 75(11): 1165-1191 (2010)
Alastair F. Donaldson, Uwe Dolinsky, Andrew Richards, George Russell, Automatic Offloading of C++ for the Cell BE Processor: A Case Study Using Offload., CISIS 2010: 901-906
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung, An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays., TRETS 3(3): 13 (2010)
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung, FPGA Architecture Optimization Using Geometric Programming., IEEE Trans. on CAD of Integrated Circuits and Systems 29(8): 1163-1176 (2010)
Albert Cohen, Erven Rohou, Processor Virtualization and Split Compilation for Heterogeneous Multicore Embedded Systems, ACM
Albert Cohen, Erven Rohou, Processor virtualization and split compilation for heterogeneous multicore embedded systems., DAC 2010: 102-107
Albert Cohen, Ronald A. DeVore, Christoph Schwab, Convergence Rates of Best N-term Galerkin Approximations for a Class of Elliptic sPDEs., Foundations of Computational Mathematics 10(6): 615-646 (2010)
Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Román Hermida, Seda Ogrenci Memik, Using Speculative Functional Units in high level synthesis., DATE 2010: 1779-1784
Alberto Corrales-García, Gerardo Fernández-Escribano, Francisco J. Quiles, Mapping GOPS in an Improved DVC to H.264 Video Transcoder., ACIVS (2) 2010: 22-33
Alberto Corrales-García, José Luis Martínez, Francisco J. Quiles, Flexible GOP transcoding between DVC and H.264., MoMM 2010: 234-240
Alberto Corrales-García, Rafael Rodríguez-Sánchez, José Luis Martínez, Gerardo Fernández-Escribano, José M. Claver, José Luis Sánchez, A GPU-Based DVC to H.264/AVC Transcoder., HAIS (2) 2010: 233-240
Alberto Nuñez, Javier Fernández, Jesús Carretero, New Contributions for Simulating Large Distributed Systems., DS-RT 2010: 227-230
Alberto Nuñez, Javier Fernández, José Daniel García, Félix García, Jesús Carretero, New techniques for simulating high performance MPI applications on large storage networks., The Journal of Supercomputing 51(1): 40-57 (2010)
Alberto Ros, Manuel E. Acacio, José M. García, A scalable organization for distributed directories., Journal of Systems Architecture - Embedded Systems Design 56(2-3): 77-87 (2010)
Alejandro Duran, Roger Ferrer, Michael Klemm, Bronis R. de Supinski, Eduard Ayguadé, A Proposal for User-Defined Reductions in OpenMP., IWOMP 2010: 43-55
Aleksandar Ilic, Leonel Sousa, Collaborative Execution Environment for Heterogeneous Parallel Systems, 2th Workshop on Advances in Parallel and Distributed Computational Models (APDCM/IPDPS 2010)
Alen Bardizbanyan, Kasyab P. Subramaniyan, Per Larsson-Edefors, Generation and Exploration of Layouts for Area-Efficient Barrel Shifters., ISVLSI 2010: 454-455
Alessandro Barenghi, Luca Breveglieri, Israel Koren, Gerardo Pelosi, Francesco Regazzoni, Countermeasures against fault attacks on software implemented AES: effectiveness and cost., WESS 2010: 7
Alessandro Cilardo, Luigi Esposito, Antonio Veniero, Antonino Mazzeo, Vicenç Beltran, Eduard Ayguadé, A CellBE-based HPC Application for the Analysis of Vulnerabilities in Cryptographic Hash Functions., HPCC 2010: 450-457
Alessandro Panella, Marco D. Santambrogio, Francesco Redaelli, Fabio Cancare, Donatella Sciuto, A design workflow for dynamically reconfigurable multi-FPGA systems., VLSI-SoC 2010: 414-419
Alessandro Strano, Daniele Ludovici, Davide Bertozzi, A library of dual-clock FIFOs for cost-effective and flexible MPSoC design., ICSAMOS 2010: 20-27
Alessio Bechini, Jacopo Viotto, Riccardo Giannini, Smooth Introduction of Semantic Tagging in Genotyping Procedures., ITBAM 2010: 201-214
Alessio Bonfietti, Luca Benini, Michele Lombardi, Michela Milano, An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms., DATE 2010: 897-902
Alessio Montone, Marco D. Santambrogio, Donatella Sciuto, Wirelength driven floorplacement for FPGA-based partial reconfigurable systems., IPDPS Workshops 2010: 1-8
Alessio Montone, Marco D. Santambrogio, Donatella Sciuto, Seda Ogrenci Memik, Placement and Floorplanning in Dynamically Reconfigurable FPGAs., TRETS 3(4): 24 (2010)
Alex Ramírez, Felipe Cabarcas, Ben H. H. Juurlink, Mauricio Alvarez, Friman Sánchez, Arnaldo Azevedo, Cor Meenderinck, Catalin Bogdan Ciobanu, Sebastian Isaza, Georgi Gaydadjiev, The SARC Architecture., IEEE Micro 30(5): 16-29 (2010)
Alexander A. Shvartsman, Pascal Felber, Editors' preface., Theor. Comput. Sci. 411(14-15): 1543 (2010)
Alexander Mendiburu, José Miguel-Alonso, José Antonio Lozano, A Review on Parallel Estimation of Distribution Algorithms., Parallel and Distributed Computational Intelligence 2010: 143-163
Alexander Monakov, Anton Lokhmotov, Arutyun Avetisyan, Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures., HiPEAC 2010: 111-125
Alexandros Bartzas, Miguel Peón Quirós, Christophe Poucet, Christos Baloukas, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Software metadata: Systematic characterization of the memory behaviour of dynamic applications., Journal of Systems and Software 83(6): 1051-1075 (2010)
Alexandros Kapravelos, Iasonas Polakis, Elias Athanasopoulos, Sotiris Ioannidis, Evangelos P. Markatos, D(e|i)aling with VoIP: Robust Prevention of DIAL Attacks., ESORICS 2010: 663-678
Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi, Luca Benini, Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks., IEEE Trans. VLSI Syst. 18(1): 1-14 (2010)
Allen Leung, Nicolas Vasilache, Benoît Meister, Muthu Manikandan Baskaran, David Wohlford, Cédric Bastoul, Richard Lethin, A mapping path for multi-GPGPU accelerated computers from a portable high level programming abstraction., GPGPU 2010: 51-61
Alvaro Wong, Dolores Rexachs, Emilio Luque, Extraction of Parallel Application Signatures for Performance Prediction., HPCC 2010: 223-230
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman, Timing-driven variation-aware nonuniform clock mesh synthesis., ACM Great Lakes Symposium on VLSI 2010: 15-20
Amelia W. Azman, Abbas Bigdeli, Yasir Mohd-Mustafah, Morteza Biglari-Abhari, Brian C. Lovell, A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design., ASAP 2010: 81-88
Amir Shahzad, Eric C. Kerrigan, George A. Constantinides, A fast well-conditioned interior point method for predictive control., CDC 2010: 508-513
Amit Berman, Ran Ginosar, Idit Keidar, Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip., VLSI-SoC 2010: 37-42
Amit Kumar Singh, Thambipillai Srikanthan, Akash Kumar, Wu Jigang, Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms., Journal of Systems Architecture - Embedded Systems Design 56(7): 242-255 (2010)
Amit Kumar Singh, Wu Jigang, Akash Kumar, Thambipillai Srikanthan, Run-time mapping of multiple communicating tasks on MPSoC platforms., Procedia CS 1(1): 1019-1026 (2010)
Amit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne, Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic., FPL 2010: 19-24
Ammar Hasan, Eric C. Kerrigan, George A. Constantinides, An ISS and l-stability approach to forward error analysis of iterative numerical algorithms., CDC 2010: 780-785
Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería, Filtering Directory Lookups in CMPs., DSD 2010: 207-216
André C. Santos, João M. P. Cardoso, Diogo R. Ferreira, Pedro C. Diniz, Paulo Chainho, Providing user context for mobile and social networking applications., Pervasive and Mobile Computing 6(3): 324-341 (2010)
André C. Santos, Luís Tarrataca, João M. P. Cardoso, The Feasibility of Navigation Algorithms on Smartphones using J2ME., MONET 15(6): 819-830 (2010)
André Seznec, A Phase Change Memory as a Secure Main Memory., Computer Architecture Letters 9(1): 5-8 (2010)
André Seznec, Uri Weiser, Ronny Ronen, 37th International Symposium on Computer Architecture (ISCA 2010) June 19-23 2010 Saint-Malo France, ACM 2010
Andrea Adamoli, Matthias Hauswirth, Trevis: a context tree visualization & analysis framework and its use for classifying performance failure reports., SOFTVIS 2010: 73-82
Andrea Adamoli, Milan Jovic, Matthias Hauswirth, LagAlyzer: A latency profile analysis and visualization tool., ISPASS 2010: 13-22
Andrea Bartolini, Matteo Cacciari, Andrea Tilli, Luca Benini, Matthias Gries, A virtual platform environment for exploring power thermal and reliability management control strategies in high-performance multicores., ACM Great Lakes Symposium on VLSI 2010: 311-316
Andrea Marongiu, Martino Ruggiero, Luca Benini, Efficient OpenMP data mapping for multicore platforms with vertically stacked memory., DATE 2010: 105-110
Andrea Marongiu, Paolo Burgio, Luca Benini, Vertical stealing: robust, locality-aware do-all workload distribution for 3D MPSoCs, Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems (CASES)
Andrea Marongiu, Paolo Burgio, Luca Benini, Vertical stealing: robust locality-aware do-all workload distribution for 3D MPSoCs., CASES 2010: 207-216
Andrea Marongiu, Paolo Burgio, Luca Benini, Evaluating OpenMP Support Costs on MPSoCs., DSD 2010: 191-198
Andrea Marongiu, Paolo Burgio, Luca Benini, Evaluating OpenMP Support Costs on MPSoCs, Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference
Andreas Krall, Hanspeter Mössenböck, Proceedings of the 8th International Conference on Principles and Practice of Programming in Java PPPJ 2010 Vienna Austria September 15-17 2010, ACM 2010
Andreas Merentitis, Antonis Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Energy-Optimal On-Line Self-Test of Microprocessors in WSN Nodes, IEEE International Conference on Computer Design (ICCD), 2010
Andreas Merentitis, Dimitris Margaris, Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, SBST for On-Line Detection of Hard Faults in Multiprocessor Applications Under Energy Constraints, IEEE International On-Line Testing Symposium (IOLTS), 2010
Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch, A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs., FPL 2010: 234-239
Andreas Sandberg, David Eklov, Erik Hagersten, Reducing Cache Pollution Through Detection and Elimination of Non-Temporal Memory Accesses., SC 2010: 1-11
Andrew D. Brown, Steve Furber, Jeff S. Reeve, Peter R. Wilson, Mark Zwolinski, John E. Chad, Luis A. Plana, David R. Lester, A communication infrastructure for a million processor machine., Conf. Computing Frontiers 2010: 75-76
Anis Charfi, Chokri Mraidha, Sébastien Gérard, François Terrier, Pierre Boulet, Toward optimized code generation through model-based optimization., DATE 2010: 1313-1316
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk, Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options., FPL 2010: 364-367
António Rodrigues, Nuno Roma, Leonel Sousa, p264: open platform for designing parallel H.264/AVC video encoders on multi-core systems., NOSSDAV 2010: 81-86
Anthony Brandon, Ioannis Sourdis, Georgi Nedeltchev Gaydadjiev, General Purpose Computing with Reconfigurable Acceleration., FPL 2010: 588-591
Antoni Roca, Jose Flich, Federico Silla, José Duato, A Latency-Efficient Router Architecture for CMP Systems., DSD 2010: 165-172
Antonino Tumeo, Francesco Regazzoni, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto, A reconfigurable multiprocessor architecture for a reliable face recognition implementation., DATE 2010: 319-322
Antonino Tumeo, Oreste Villa, Donatella Sciuto, Efficient pattern matching on GPUs for intrusion detection systems., Conf. Computing Frontiers 2010: 87-88
Antonio Flores, Juan L. Aragón, Manuel E. Acacio, Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs., IEEE Trans. Computers 59(1): 16-28 (2010)
Antonio Flores, Juan L. Aragón, Manuel E. Acacio, Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects., PDP 2010: 147-154
Antonio J. Dios, Rafael Asenjo, Angeles G. Navarro, Francisco Corbera, Emilio L. Zapata, Evaluation of the Task Programming Model in the Parallelization of Wavefront Problems., HPCC 2010: 257-264
Antonio Roldao Lopes, George A. Constantinides, A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices., TRETS 3(1): (2010)
Antonio Roldao Lopes, George A. Constantinides, A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs., ARC 2010: 157-168
Antonis Papadogiannakis, Michalis Polychronakis, Evangelos P. Markatos, RRDtrace: Long-term Raw Network Traffic Recording using Fixed-size Storage., MASCOTS 2010: 101-110
Antonis Papadogiannakis, Michalis Polychronakis, Evangelos P. Markatos, Improving the accuracy of network intrusion detection systems under load using selective packet discarding., EUROSEC 2010: 15-21
Antony Chazapis, Athanasia Asiki, Georgios Tsoukalas, Dimitrios Tsoumakos, Nectarios Koziris, Replica-aware multi-dimensional range queries in Distributed Hash Tables., Computer Communications 33(8): 984-996 (2010)
Anurag Negi, M. M. Waliullah, Per Stenström, LV*: A low complexity lazy versioning HTM infrastructure., ICSAMOS 2010: 231-240
Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens, Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism., J. Electronic Testing 26(4): 453-464 (2010)
Arik Friedman, Assaf Schuster, Data mining with differential privacy., KDD 2010: 493-502
Arindam Mallik, Peter Marwedel, Dimitrios Soudris, Sander Stuijk, MNEMEE: a framework for memory management and optimization of static and dynamic data in MPSoCs., CASES 2010: 257-258
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny, Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect., IEEE Trans. VLSI Syst. 18(5): 689-696 (2010)
Arnaldo Azevedo, Ben H. H. Juurlink, A Multidimensional Software Cache for Scratchpad-Based Systems., IJERTCS 1(4): 1-20 (2010)
Arpad Gellert, Gianluca Palermo, Vittorio Zaccaria, Adrian Florea, Lucian N. Vintan, Cristina Silvano, Energy-performance design space exploration in SMT architectures exploiting selective load value predictions., DATE 2010: 271-274
Arun A. Nair, Lizy Kurian John, Lieven Eeckhout, AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors., MICRO 2010: 125-136
Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, Thomas Brunschwiler, David Atienza, 3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling., ICCAD 2010: 463-470
Athanasia Asiki, Dimitrios Tsoumakos, Nectarios Koziris, Distributing and searching concept hierarchies: an adaptive DHT-based system., Cluster Computing 13(3): 257-276 (2010)
Avi Timor, Avi Mendelson, Yitzhak Birk, Neeraj Suri, Using Underutilized CPU Resources to Enhance Its Reliability., IEEE Trans. Dependable Sec. Comput. 7(1): 94-109 (2010)
Ayelet Israeli, Dror G. Feitelson, The Linux kernel as a case study in software evolution., Journal of Systems and Software 83(3): 485-501 (2010)
Ayse Kivilcim Coskun, David Atienza, Tajana Simunic Rosing, Thomas Brunschwiler, Bruno Michel, Energy-efficient variable-flow liquid cooling in 3D stacked architectures., DATE 2010: 111-116
B. de la Ossa, Ana Pont, Julio Sahuquillo, José A. Gil, Referrer graph: a low-cost web prediction algorithm., SAC 2010: 831-838
Bartosz Bogdanski, Frank Olaf Sem-Jacobsen, Sven-Arne Reinemo, Tor Skeie, Line Holen, Lars Paul Huse, Achieving Predictable High Performance in Imbalanced Fat Trees, Proc. of the 16th IEEE International Conference on Parallel and Distributed Systems, pp. 381-388, IEEE Computer Society, 2010
Basher Shehan, Ralf Jahr, Sascha Uhrig, Theo Ungerer, Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration., DSD 2010: 71-79
Basilio B. Fraguela, Diego Andrade, Ramon Doallo, Address-Independent Estimation of the Worst-case Memory Performance., IEEE Trans. Industrial Informatics 5(4): 664-677 (2010)
Behram Khan, Matthew Horsnell, Mikel Luján, Ian Watson, Scalable Object-Aware Hardware Transactional Memory., Euro-Par (1) 2010: 268-279
Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes, Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study., IEEE Trans. Computers 59(4): 433-448 (2010)
Ben Titzer, Thomas Würthinger, Doug Simon, Marcelo Cintra, Improving compiler-runtime separation with XIR., VEE 2010: 39-50
Benjamin Aziz, Alvaro Arenas, Ian Johnson, Matej Artac, Ales Cernivec, Philip Robinson, Management of Security Policies in Virtual Organisations., SECRYPT 2010: 467-477
Benjamin Satzger, Faruk Bagci, Florian Kluge, Theo Ungerer, Towards lightweight self-configuration in wireless sensor networks., SAC 2010: 791-792
Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, A, Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach., ISVLSI 2010: 518-523
Bertrand Rousseau, Philippe Manet, Igor Loiselle, Jean-Didier Legat, Hans Vandierendonck, A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms., DASIP 2010: 273-280
Bhavishya Goel, Sally A McKee, Roberto Gioiosa, Karan Singh, Major Bhadauria, Marco Cesati, Portable, scalable, per-core power estimation for intelligent resource management, IEEE
Bill Lin, Isaac Keslassy, The Concurrent Matching Switch Architecture., IEEE/ACM Trans. Netw. 18(4): 1330-1343 (2010)
Björn Lisper, Andreas Ermedahl, Dietmar Schreiner, Jens Knoop, Peter Gliwa, Practical Experiences of Applying Source-Level WCET Flow Analysis on Industrial Code., ISoLA (2) 2010: 449-463
Björn Nilsson, Lars Bengtsson, Bertil Svensson, An Energy and Application Scenario Aware Active RFID Protocol., EURASIP J. Wireless Comm. and Networking 2010: (2010)
Bjorn De Sutter, Osman Allam, Praveen Raghavan, Roeland Vandebriel, Hans Cappelle, Tom Vander Aa, Bingfeng Mei, An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors., Signal Processing Systems 61(2): 157-179 (2010)
Blanca Callén, Daniel López, Miquel Doménech, Francisco Tirado, Not Just Software: Free Software and the (Techno) Political Action., IJT 1(2): 27-36 (2010)
Bo Hu, Yi Lu, Jianping Yu, Dynamics Analysis of Some Limited-Degree-of-Freedom Parallel Manipulators with n UPS Active Legs and a Passive Constraining Leg., Advanced Robotics 24(7): 1003-1016 (2010)
Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon, A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis., FPL 2010: 556-561
Boris Feigin, Alan Mycroft, Formally Efficient Program Instrumentation., RV 2010: 245-252
Boubacar Diouf, Albert Cohen, Fabrice Rastello, John Cavazos, Split Register Allocation: Linear Complexity Without the Performance Penalty., HiPEAC 2010: 66-80
Boxun Zhang, Alexandru Iosup, Johan A. Pouwelse, Dick H. J. Epema, Henk J. Sips, Sampling Bias in BitTorrent Measurements., Euro-Par (1) 2010: 484-496
Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt, Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only)., FPGA 2010: 287
Brandon Ingram, Daniel Jones, Andrew Lewis, Matthew Richards, Charles Rich, Lance Schachterle, A code of ethics for robotics engineers., HRI 2010: 103-104
Bruno Francisco, Frederico Pratas, Leonel Sousa, Unifying stream based and reconfigurable computing to design application accelerators., VLSI-SoC 2010: 408-413
C. Gimmler, Timo Lehnigk-Emden, Norbert Wehn, Low-complexity iteration control for MIMO-BICM systems., PIMRC 2010: 241-246
Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet, High-Level Synthesis for Designing Multimode Architectures., IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1736-1749 (2010)
Carles Hernandez, Antoni Roca, Federico Silla, Jose Flich, José Duato, Improving the Performance of GALS-Based NoCs in the Presence of Process Variation., NOCS 2010: 35-42
Carles Hernandez, Federico Silla, José Duato, A methodology for the characterization of process variation in NoC links., DATE 2010: 685-690
Carlo Bergonzini, Davide Brunelli, Luca Benini, Comparison of energy intake prediction algorithms for systems powered by photovoltaic harvesters., Microelectronics Journal 41(11): 766-777 (2010)
Carlo Caione, Davide Brunelli, Luca Benini, Compressive sensing optimization over ZigBee networks., SIES 2010: 36-44
Carlos de Blas Carton, Arturo González-Escribano, Diego R. Llanos Ferraris, Effortless and Efficient Distributed Data-Partitioning in Linear Algebra., HPCC 2010: 89-97
Carlos Domínguez, Houcine Hassan, José Albaladejo, Alfons Crespo, Simulation Fframework for Validation of Emotional Agents., IC-AI 2010: 982-988
Carlos García-Cabrera, Pedro Morillo, Juan M. Orduña, Analyzing Large-Scale Crowd Simulations for Building Evacuation., PAAMS (Special Sessions and Workshops) 2010: 591-598
Carlos H. Gonzalez, Basilio B. Fraguela, A Generic Algorithm Template for Divide-and-Conquer in Multicore Systems., HPCC 2010: 79-88
Carlos Pérez-Miguel, José Miguel-Alonso, Alexander Mendiburu, Porting Estimation of Distribution Algorithms to the Cell Broadband Engine., Parallel Computing 36(10-11): 618-634 (2010)
Carmen Martínez, Ramón Beivide, Cristobal Camarero, Esteban Stafford, Ernst M. Gabidulin, Quotients of Gaussian graphs and their application to perfect codes., J. Symb. Comput. 45(7): 813-824 (2010)
Carolina Bonacic, Carlos García, Mauricio Marín, Manuel Prieto-Matías, Francisco Tirado, Building efficient multi-threaded search nodes., CIKM 2010: 1249-1258
Catalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Gaydadjiev, Alex Ramírez, A Polymorphic Register File for matrix operations., ICSAMOS 2010: 241-249
Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides, Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA., ARC 2010: 182-193
Changhua Wu, Ying Zhang, Weihua Sheng, Saroja Kanchi, Rigidity guided localisation for mobile robotic sensor networks., IJAHUC 6(2): 114-128 (2010)
Chi Ching Chi, Ben H. H. Juurlink, Cor Meenderinck, Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine., ICS 2010: 105-114
Christian Bertin, Christophe Guillon, Koen De Bosschere, Compilation and virtualization in the HiPEAC vision., DAC 2010: 96-101
Christian Müller-Schloer, Wolfgang Karl, Sami Yehia, Architecture of Computing Systems - ARCS 2010 23rd International Conference Hannover Germany February 22-25 2010. Proceedings, Springer 2010
Christian Pilato, Fabrizio Ferrandi, Davide Pandini, A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells., ISVLSI 2010: 23-28
Christian Spielvogel, Sabina Serbu, Pascal Felber, Peter Kropf, Semantic Based Error Avoidance and Correction for Video Streaming., Semantics in Adaptive and Personalized Services 2010: 73-92
Christian Tenllado, José Ignacio Gómez, Javier Setoain, Darío Mora, Manuel Prieto, Improving face recognition by combination of natural and Gabor faces., Pattern Recognition Letters 31(11): 1453-1460 (2010)
Christian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Efficient High-Level modeling in the networking domain., DATE 2010: 1189-1194
Christine Rochange, Armelle Bonenfant, Pascal Sainrat, Mike Gerdes, Julian Wolf, Theo Ungerer, Zlatko Petrov, Frantisek Mikulu, WCET Analysis of a Parallel 3D Multigrid Solver Executed on the MERASA Multi-Core., WCET 2010: 90-100
Christoforos Kachris, George Nikiforos, Stamatis Kavadias, Vassilis Papaefstathiou, Manolis Katevenis, Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface, International Conference on Reconfigurable Computing and FPGAs
Christoforos Kachris, George Nikiforos, Vassilis Papaefstathiou, Xiaojun Yang, Stamatis Kavadias, Manolis Katevenis, Low-latency Explicit Communication and Synchronization in Scalable Multi-core Clusters, IEEE International Conference on Cluster Computing (Cluster 2010)
Christoph Puttmann, Mario Porrmann, Paolo Roberto Grassi, Marco D. Santambrogio, Ulrich Rückert, High level specification of embedded listeners for monitoring of Network-on-Chips., ISCAS 2010: 3333-3336
Christoph Schumacher, Rainer Leupers, Dietmar Petras, Andreas Hoffmann, parSC: synchronous parallel systemc simulation on multi-core host architectures., CODES+ISSS 2010: 241-246
Christophe Alias, Alain Darte, Alexandra Plesco, Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool., ASAP 2010: 329-332
Christophe Alias, Alain Darte, Paul Feautrier, Laure Gonnord, Multi-dimensional Rankings Program Termination and Complexity Bounds of Flowchart Programs., SAS 2010: 117-133
Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Michael F. P. O'Boyle, A Predictive Model for Dynamic Microarchitectural Adaptivity Control., MICRO 2010: 485-496
Christos Baloukas, Lazaros Papadopoulos, Dimitrios Soudris, Sander Stuijk, Olivera Jovanovic, Florian Schmoll, Daniel Cordes, Robert Pyka, Arindam Mallik, Stylianos Mamagkakis, François Capman,, Mapping Embedded Applications on MPSoCs: The MNEMEE Approach., ISVLSI 2010: 512-517
Christos Baloukas, Lazaros Papadopoulos, Robert Pyka, Dimitrios Soudris, Peter Marwedel, An automatic framework for dynamic data structures optimization in C., VLSI-SoC 2010: 155-160
Christos Kotselidis, Mikel Luján, Mohammad Ansari, Konstantinos Malakasis, Behram Khan, Chris C. Kirkham, Ian Watson, Clustering JVMs with software transactional memory support., IPDPS 2010: 1-12
Christos Strydis, Dhara Dave, Georgi Gaydadjiev, ImpBench revisited: An extended characterization of implant-processor benchmarks., ICSAMOS 2010: 126-135
Chunyang Gou, Georgi Kuzmanov, Georgi Gaydadjiev, SAMS multi-layout memory: providing multiple views of data to boost SIMD performance., ICS 2010: 179-188
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli, SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips., IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1987-2000 (2010)
Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli, A method to remove deadlocks in Networks-on-Chips with Wormhole flow control., DATE 2010: 1625-1628
Clément Ballabriga, Hugues Cassé, Christine Rochange, Pascal Sainrat, OTAWA: An Open Toolbox for Adaptive WCET Analysis., SEUS 2010: 35-46
Claudio Brunelli, Fabio Garzia, Davide Rossi, Jari Nurmi, A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations., Journal of Systems Architecture - Embedded Systems Design 56(1): 38-47 (2010)
Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini, Adaptive Power Management for Environmentally Powered Systems., IEEE Trans. Computers 59(4): 478-491 (2010)
Concepción Sanz Pineda, Manuel Prieto, José Ignacio Gómez, Christian Tenllado, Francky Catthoor, Statistical approach in a system level methodology to deal with process variation., CODES+ISSS 2010: 115-124
Cor Meenderinck, Ben H. H. Juurlink, A Case for Hardware Task Management Support for the StarSS Programming Model., DSD 2010: 347-354
Craig Moore, Wim Meeus, Harald Devos, Dirk Stroobandt, A Parallel for Loop Memory Template for a High Level Synthesis Compiler., DSD 2010: 449-455
Cristian Perfumo, John K. Ward, Julio H. Braslavsky, Reducing energy use and operational cost of air conditioning systems with multi-objective evolutionary algorithms., IEEE Congress on Evolutionary Computation 2010: 1-8
Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Niccolò Battezzati, Luca Sterpone, Massimo Violante, An integrated flow for the design of hardened circuits on SRAM-based FPGAs., European Test Symposium 2010: 214-219
Cristiana Bolchini, Donatella Sciuto, Guest Editors' Introduction: Special Section on System-Level Design of Reliable Architectures., IEEE Trans. Computers 59(5): 577-578 (2010)
Cristiana Bolchini, Pier Luca Lanzi, Antonio Miele, A multi-objective genetic algorithm framework for design space exploration of reliable FPGA-based systems., IEEE Congress on Evolutionary Computation 2010: 1-8
Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Co, MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures., ISVLSI 2010: 488-493
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, S. Corbetta, Andrea Di Biagio, E. Speziale, M. Ta, 2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures., ISVLSI 2010: 494-499
Cupertino Miranda, Philippe Dumont, Albert Cohen, Marc Duranton, Antoniu Pop, ERBIUM: a deterministic concurrent intermediate representation for portable and scalable performance., Conf. Computing Frontiers 2010: 119-120
D. Benitez, J.C. Moure, D.I. Rexachs, E. Luque, A RECONFIGURABLE CACHE MEMORY WITH HETEROGENEOUS BANKS; Proceedings of the Design, Automation & Test in Europe 2010 Conference and Exhibition (DATE10); pp. 825-830, EDAA
D. Ludovici, A. Strano, G. N. Gaydadjiev, L. Benini, D. Bertozzi, Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCs, Proceedings of Design, Automation and Test in Europe 2010 (DATE), pp. 679-684, Dresden, Germany, March 2010
D. Ludovici, F. Gilabert, M. E. Gomez, G. N. Gaydadjiev, D. Bertozzi, Contrasting Topologies for Regular Interconnection Networks under the Constraints of Nanoscale Silicon Technology, Proceedings of the 3rd ACM/IEEE International Workshop on Network-on-Chip Architectures (NoCArc), pp. 37-42, 2010
Damon Fenacci, Björn Franke, Empirical evaluation of data transformations for network infrastructure applications., ICSAMOS 2010: 55-62
Daniel Cordes, Peter Marwedel, Arindam Mallik, Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming., CODES+ISSS 2010: 267-276
Daniel Ziener, Florian Baueregger, Jürgen Teich, Multiplexing Methods for Power Watermarking., HOST 2010: 36-41
Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Luca Benini, Davide Bertozzi, Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs., DATE 2010: 679-684
Dario Faggioli, Giuseppe Lipari, Tommaso Cucinotta, The Multiprocessor Bandwidth Inheritance Protocol., ECRTS 2010: 90-99
Dave Christie, Jae-Woong Chung, Stephan Diestelhorst, Michael Hohmuth, Martin Pohlack, Christof Fetzer, Martin Nowack, Torvald Riegel, Pascal Felber, Patrick Marlier, Etienne Riviere, Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack., EuroSys 2010: 27-40
David Andrews, Christian Plessl, Configurable Processor Architectures: History and Trends., ERSA 2010: 165
David B. Thomas, Wayne Luk, An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers., ASAP 2010: 208-215
David B. Thomas, Wayne Luk, FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers., FPL 2010: 77-82
David Bernstein, Deepak Vij, Intercloud Security Considerations., CloudCom 2010: 537-544
David Bernstein, Deepak Vij, Using Semantic Web Ontology for Intercloud Directories and Exchanges., International Conference on Internet Computing 2010: 18-24
David Bernstein, Deepak Vij, Intercloud Directory and Exchange Protocol Detail Using XMPP and RDF., SERVICES 2010: 431-438
David Boland, George A. Constantinides, Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods., ARC 2010: 169-181
David Cuesta, José L. Ayala, José Ignacio Hidalgo, David Atienza, Andrea Acquaviva, Enrico Macii, Adaptive Task Migration Policies for Thermal Control in MPSoCs., ISVLSI 2010: 110-115
David Cuesta, José Luis Ayala, Jose Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii, Thermal-aware floorplanning exploration for 3D multi-core architectures., ACM Great Lakes Symposium on VLSI 2010: 99-102
David Eklov, David Black-Schaffer, Erik Hagersten, StatCC: a statistical cache contention model., PACT 2010: 551-552
David Eklov, Erik Hagersten, StatStack: Efficient modeling of LRU caches., ISPASS 2010: 55-65
David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung, A Salient Region Detector for GPU Using a Cellular Automata Architecture., ICONIP (2) 2010: 501-508
David J. Pearce, Paul H. J. Kelly, A batch algorithm for maintaining a topological order., ACSC 2010: 79-88
David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Automatic Generation of Memory Interfaces for ASIPs., IJERTCS 1(3): 1-23 (2010)
David Novo, Min Li, Robert Fasthuber, Praveen Raghavan, Francky Catthoor, Exploiting finite precision information to guide data-flow mapping., DAC 2010: 248-253
Davide Figo, Pedro C. Diniz, Diogo R. Ferreira, João M. P. Cardoso, Preprocessing techniques for context recognition from accelerometer data., Personal and Ubiquitous Computing 14(7): 645-662 (2010)
Davy Genbrugge, Stijn Eyerman, Lieven Eeckhout, Interval simulation: Raising the level of abstraction in architectural simulation., HPCA 2010: 1-12
Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Márcio Eduardo Kreutz, Monitor-adapter coupling for NOC performance tuning., ICSAMOS 2010: 193-199
Debora Matos, Luigi Carro, Altamiro Amadeu Susin, Associating packets of heterogeneous cores using a synchronizer wrapper for NoCs., ISCAS 2010: 4177-4180
Debora Matos, Miklecio Costa, Luigi Carro, Altamiro Amadeu Susin, Network interface to synchronize multiple packets on NoC-based Systems-on-Chip., VLSI-SoC 2010: 31-36
Demetres Antoniades, Evangelos P. Markatos, Constantine Dovrolis, MOR: Monitoring and Measurements through the Onion Router., PAM 2010: 131-140
Demid Borodin, Ben H. H. Juurlink, Instruction precomputation with memoization for fault detection., DATE 2010: 1665-1668
Demid Borodin, Ben H. H. Juurlink, Protective redundancy overhead reduction using instruction vulnerability factor., Conf. Computing Frontiers 2010: 319-326
Dennis Bode, Mladen Berekovic, Axel Borkowski, Ludger Buker, QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration., DSD 2010: 141-146
Derin Harmanci, Vincent Gramoli, Pascal Felber, Christof Fetzer, Extensible transactional memory testbed., J. Parallel Distrib. Comput. 70(10): 1053-1067 (2010)
Devis Bianchini, Stefano Montanelli, Carola Aiello, Roberto Baldoni, Cristiana Bolchini, Silvia Bonomi, Silvana Castano, Tiziana Catarci, Valeria De Antonellis, Alfio Ferrara, Michele Melchiori, Elisa, Emergent Semantics and Cooperation in Multi-knowledge Communities: the ESTEEM Approach., World Wide Web 13(1-2): 3-31 (2010)
Dhara Dave, Christos Strydis, Georgi Gaydadjiev, ImpEDE: A multidimensional design-space exploration framework for biomedical-implant processors., ASAP 2010: 39-46
Diana Bautista Rayo, Julio Sahuquillo Borrás, Houcine Hassan Mohamed, Salvador Petit, José Duato, Balancing Task Resource Requirements in Embedded Multithreaded Multicore Processors to Reduce Power Consumption., PDP 2010: 200-204
Diego Rodriguez Martínez, José Carlos Cabaleiro, Tomás Fernandez Pena, Francisco Fernandez Rivera, Vicente Blanco Pérez, Performance Modeling of MPI Applications Using Model Selection Techniques., PDP 2010: 95-102
Diego Rodriguez Martínez, V. Blanco, José Carlos Cabaleiro, Tomás F. Pena, Francisco F. Rivera, Automatic parameter assessment of logp-based communication models in MPI environments., Procedia CS 1(1): 2155-2164 (2010)
Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi, A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework., PATMOS 2010: 73-83
Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev, A 3d-audio reconfigurable processor., FPGA 2010: 107-110
Dmitri Vainbrand, Ran Ginosar, Network-on-Chip Architectures for Neural Networks., NOCS 2010: 135-144
Dmitrijs Zaparanuks, Matthias Hauswirth, Characterizing the design and performance of interactive java applications., ISPASS 2010: 23-32
Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque, A reconfigurable cache memory with heterogeneous banks., DATE 2010: 825-830
Dominic A. Orchard, Max Bolingbroke, Alan Mycroft, Ypnos: declarative parallel structured grid programming., DAMP 2010: 15-24
Dong Li, Bronis R. de Supinski, Martin Schulz, Kirk W. Cameron, Dimitrios S. Nikolopoulos, Hybrid MPI/OpenMP power-aware computing., IPDPS 2010: 1-12
Dong Li, Dimitrios S. Nikolopoulos, Kirk W. Cameron, Bronis R. de Supinski, Martin Schulz, Power-aware MPI task aggregation prediction for high-end computing systems., IPDPS 2010: 1-12
Edson Borin, Youfeng Wu, Cheng Wang, Wei Liu, Mauricio Breternitz Jr., Shiliang Hu, Esfir Natanzon, Shai Rotem, Roni Rosner, TAO: two-level atomicity for dynamic binary optimizations., CGO 2010: 12-21
Eduard Ayguadé, James Beyer, Alejandro Duran, Roger Ferrer, Grant Haab, Kelvin Li, Federico Massaioli, An Extension to Improve OpenMP Tasking Control., IWOMP 2010: 56-69
Eduard Ayguadé, Rosa M. Badia, Pieter Bellens, Daniel Cabrera, Alejandro Duran, Roger Ferrer, Marc González, Francisco D. Igual, Daniel Jiménez-González, Jesús Labar, Extending OpenMP to Survive the Heterogeneous Multi-Core Era., International Journal of Parallel Programming 38(5-6): 440-459 (2010)
Edward A. Stott, Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung, Degradation in FPGAs: measurement and modelling., FPGA 2010: 229-238
Eladio Gutiérrez, Sergio Romero, María A. Trenas, Emilio L. Zapata, Quantum computer simulation using the CUDA programming model., Computer Physics Communications 181(2): 283-300 (2010)
Eleftheria Katsiri, Jean Bacon, Alan Mycroft, Linking Temporal First Order Logic and Hidden Markov Models with Abstract Events., International Journal on Artificial Intelligence Tools 19(6): 857-893 (2010)
Elena Kakoulli, Vassos Soteriou, Theocharis Theocharides, An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs., ISVLSI 2010: 339-344
Elias Athanasopoulos, Antonis Krithinakis, Evangelos P. Markatos, An Architecture for Enforcing JavaScript Randomization in Web2.0 Applications., ISC 2010: 203-209
Elias Baaklini, Hassan Sbeity, Smaïl Niar, Nouhad Amaneddine, H.264 Color Components Video Decoding Parallelization on Multi-core Processors., DSD 2010: 785-790
Emilio J. Padrón, Margarita Amor, Montserrat Bóo, Ramon Doallo, Hierarchical Radiosity for Multiresolution Systems Based on Normal Tests., Comput. J. 53(6): 741-752 (2010)
Emilio Volpi, Luca Fanucci, Adolfo Giambastiani, Alessandro Rocchi, Francesco D'Ascoli, Marco Tonarelli, Massimiliano Melani, Corrado Marino, A Mixed-Signal Embedded Platform for Automotive Sensor Conditioning., EURASIP J. Emb. Sys. 2010: (2010)
Enno Lübbers, Marco Platzner, Christian Plessl, Ariane Keller, Bernhard Plattner, Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware., ERSA 2010: 225-231
Enric Tejedor, Rosa M. Badia, Romina Royo, Josep Lluis Gelpí, Enabling HMMER for the Grid with COMP Superscalar., Procedia CS 1(1): 2629-2638 (2010)
Enrique Vallejo, Ramón Beivide, Adrián Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero, Architectural Support for Fair Reader-Writer Locking., MICRO 2010: 275-286
Erik Larsson, Bart Vermeulen, Kees Goossens, A distributed architecture to check global properties for post-silicon debug., European Test Symposium 2010: 182-187
Ernst Gunnar Gran, Sven-Arne Reinemo, Tor Skeie, Olav Lysne, Lars Paul Huse, Gilad Shainer, First Experiences with Congestion Control in InfiniBand Hardware., 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), IEEE Computer Society, 2010.
Erven Rohou, Andrea C. Ornstein, Marco Cornero, CLI-based compilation flows for the C language., ICSAMOS 2010: 162-169
Esteban Stafford, José Luis Bosque, Carmen Martínez, Fernando Vallejo, Ramón Beivide, Cristobal Camarero, A First Approach to King Topologies for On-Chip Networks., Euro-Par (2) 2010: 428-439
Evangelos Koukis, Anastassios Nanos, Nectarios Koziris, GMBlock: Optimizing data movement in a block-level storage sharing system over Myrinet., Cluster Computing 13(4): 349-372 (2010)
Evangelos Vlachos, Michelle L. Goodstein, Michael A. Kozuch, Shimin Chen, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, ParaLog: enabling and accelerating online parallel monitoring of multithreaded applications., ASPLOS 2010: 271-284
F. Sironi, M. Triverio, Henry Hoffmann, Martina Maggio, Marco D. Santambrogio, Self-Aware Adaptation in FPGA-based Systems., FPL 2010: 187-192
Fabian Nowak, Rainer Buchty, A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics., ARCS 2010: 222-233
Fabio Arlati, Francesco Bruschi, Donatella Sciuto, Designing and validating access policies to reconfigurable resources in Multiprocessor Systems on chip., ICSAMOS 2010: 365-371
Fabio Cancare, Marco D. Santambrogio, Donatella Sciuto, A direct bitstream manipulation approach for Virtex4-based evolvable systems., ISCAS 2010: 853-856
Fabio Garzia, Roberto Airoldi, Jari Nurmi, Implementation of FFT on General-Purpose Architectures for FPGA., IJERTCS 1(3): 24-43 (2010)
Fabio Garzia, Waqar Hussain, Jari Nurmi, Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC Core., FPL 2010: 5-9
Fabrizio Ferrandi, Christian Pilato, Donatella Sciuto, Antonino Tumeo, Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs., ASP-DAC 2010: 799-804
Fabrizio Ferrandi, Pier Luca Lanzi, Christian Pilato, Donatella Sciuto, Antonino Tumeo, Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems., IEEE Trans. on CAD of Integrated Circuits and Systems 29(6): 911-924 (2010)
Fadi J. Kurdahi, Jarmo Takala, Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (IC-SAMOS 2010) Samos Greece July 19-22 2010, IEEE 2010
Faith Ellen, Panagiota Fatourou, Eric Ruppert, Franck van Breugel, Non-blocking binary search trees., PODC 2010: 131-140
Fakhar Anjam, Stephan Wong, Faisal Nadeem, A shared reconfigurable VLIW multiprocessor system., IPDPS Workshops 2010: 1-8
Fakhri Alam Khan, Yuzhang Han, Sabri Pllana, Peter Brezany, An Ant-Colony-Optimization Based Approach for Determination of Parameter Significance of Scientific Workflows., AINA 2010: 1241-1248
Faruk Bagci, Julian Wolf, Benjamin Satzger, Theo Ungerer, UbiMASS., SUTC/UMC 2010: 245-252
Fatma Abouelella, Karel Bruneel, Dirk Stroobandt, Efficiently Generating FPGA Configurations through a Stack Machine., FPL 2010: 35-39
Fatos Xhafa, Sabri Pllana, Leonard Barolli, Grid and P2P Middleware for Scientific Computing Systems., CISIS 2010: 409-414
Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramírez, Interleaving granularity on high bandwidth memory architecture for CMPs., ICSAMOS 2010: 250-257
Felix Reimann, Michael Glaß, Christian Haubelt, Michael Eberl, Jürgen Teich, Improving platform-based system synthesis by satisfiability modulo theories solving., CODES+ISSS 2010: 135-144
Ferad Zyulkyarov, Tim Harris, Osman S. Unsal, Adrián Cristal, Mateo Valero, Debugging programs that use atomic blocks and transactional memory., PPOPP 2010: 57-66
Fernando Royo, Miguel López-Guerrero, Teresa Olivares, Luis Orozco-Barbosa, A Fast Network Configuration Algorithm for TDMA Wireless Sensor Networks., EURASIP J. Wireless Comm. and Networking 2010: (2010)
Filipa Duarte, Stephan Wong, Cache-Based Memory Copy Hardware Accelerator for Multicore Systems., IEEE Trans. Computers 59(11): 1494-1507 (2010)
Florian Kluge, Sascha Uhrig, Jörg Mische, Benjamin Satzger, Theo Ungerer, Dynamic Workload Prediction for Soft Real-Time Applications., CIT 2010: 1841-1848
Florin Isaila, Francisco Javier García Blas, Jesús Carretero, Wei-keng Liao, Alok N. Choudhary, A Scalable Message Passing Interface Implementation of an Ad-Hoc Parallel I/o system., IJHPCA 24(2): 164-184 (2010)
François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski, 21st IEEE International Conference on Application-specific Systems Architectures and Processors ASAP 2010 Rennes France 7-9 July 2010, IEEE 2010
Francesc Aràndiga, Albert Cohen, Rosa Donat, Basarab Matei, Edge detection insensitive to changes of illumination in the image., Image Vision Comput. 28(4): 553-562 (2010)
Francesco Battini, Emilio Volpi, Eleonora Marchetti, Tommaso Cecchini, Francesco Sechi, Luca Fanucci, Ulrich Hofmann, A fast-developing and low-cost characterization and test environment for a double axis resonating micromirror., Microelectronics Journal 41(11): 778-788 (2010)
Francesco Bruschi, Marco Paolieri, Vincenzo Rana, A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching., FPL 2010: 44-49
Francesco Paterna, Andrea Acquaviva , Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini, Variability-tolerant run-time workload allocation for MPSoC energy minimization under real-time constraints, Proceedings of the 7th ACM international conference on Computing frontiers
Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini, Variability-tolerant run-time workload allocation for MPSoC energy minimization under real-time constraints., Conf. Computing Frontiers 2010: 109-110
Francesco Zanini, Colin N. Jones, David Atienza, Giovanni De Micheli, Multicore thermal management using approximate explicit model predictive control., ISCAS 2010: 3321-3324
Francesco Zanini, David Atienza, Colin N. Jones, Giovanni De Micheli, Temperature sensor placement in thermal management systems for MPSoCs., ISCAS 2010: 1065-1068
Francesco Zanini, David Atienza, Giovanni De Micheli, Stephen P. Boyd, Online convex optimization-based algorithm for thermal management of MPSoCs., ACM Great Lakes Symposium on VLSI 2010: 203-208
Francisco Gilabert Villamón, María Engracia Gómez, Simone Medardoni, Davide Bertozzi, Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip., NOCS 2010: 165-172
Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero, On the Problem of Evaluating the Performance of Multiprogrammed Workloads., IEEE Trans. Computers 59(12): 1722-1728 (2010)
Frank Eichinger, David Kramer, Klemens Böhm, Wolfgang Karl, From source code to runtime behaviour: Software metrics help to select the computer architecture., Knowl.-Based Syst. 23(4): 343-349 (2010)
Frederick Ryckbosch, Stijn Polfliet, Lieven Eeckhout, Fast Accurate and Validated Full-System Software Simulation of x86 Hardware., IEEE Micro 30(6): 46-56 (2010)
Frederico Pratas, Ricardo A. Mata, Leonel Sousa, Iterative induced dipoles computation for molecular mechanics on GPUs., GPGPU 2010: 111-120
Friman Sánchez, Felipe Cabarcas, Alex Ramírez, Mateo Valero, Long DNA Sequence Comparison on Multicore Architectures., Euro-Par (2) 2010: 247-259
Görkem Asilioglu, Emine Merve Kaya, Oguz Ergin, Complexity-Effective Rename Table Design for Rapid Speculation Recovery., ARCS 2010: 15-24
Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva, Embedded multicore architectures for LDPC decoding., ICSAMOS 2010: 349-356
Gabriel Luca Nazar, Christina Gimmler, Norbert Wehn, Implementation comparisons of the QR decomposition for MIMO detection., SBCCI 2010: 210-214
Gabriel Rodríguez, María J. Martín, Patricia González, Juan Touriño, Ramon Doallo, CPPC: a compiler-assisted tool for portable checkpointing of message-passing applications., Concurrency and Computation: Practice and Experience 22(6): 749-766 (2010)
Gabriel Rodríguez, Xoán C. Pardo, María J. Martín, Patricia González, Performance evaluation of an application-level checkpointing solution on grids., Future Generation Comp. Syst. 26(7): 1012-1023 (2010)
Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip Leong, A Karatsuba-Based Montgomery Multiplier., FPL 2010: 434-437
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge, Krisztián Flautner, Evolution of thread-level parallelism in desktop applications., ISCA 2010: 302-313
George Economakos, Sotirios Xydis, Ioannis Koutras, Dimitrios Soudris, Construction of dual mode components for reconfiguration aware high-level synthesis., DATE 2010: 1357-1360
George Tzenakis, Konstantinos Kapelonis, Michail Alvanos, Konstantinos Koukos, Dimitrios S. Nikolopoulos, Angelos Bilas, Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor., HiPEAC 2010: 307-321
Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Where replacement algorithms fail: a thorough analysis., Conf. Computing Frontiers 2010: 141-150
Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras, Interval-based models for run-time DVFS orchestration in superscalar processors., Conf. Computing Frontiers 2010: 287-296
Georgios Rokos, Gerassimos Peteinatos, Georgia Kouveli, Georgios I. Goumas, Kornilios Kourtis, Nectarios Koziris, Solving the advection PDE on the cell broadband engine., IPDPS Workshops 2010: 1-8
Georgios Tournavitis, Björn Franke, Semi-automatic extraction and exploitation of hierarchical pipeline parallelism using profiling information., PACT 2010: 377-388
Gerardo Fernández-Escribano, Hari Kalva, José Luis Martínez, Pedro Cuenca, Luis Orozco-Barbosa, Antonio Garrido, An MPEG-2 to H.264 Video Transcoder in the Baseline Profile., IEEE Trans. Circuits Syst. Video Techn. 20(5): 763-768 (2010)
Germán Llort, Juan Gonzalez, Harald Servat, Judit Gimenez, Jesús Labarta, On-line detection of large-scale parallel application's structure., IPDPS 2010: 1-10
Gert-Jan van den Braak, Bart Mesman, Henk Corporaal, Compile-time GPU memory access optimizations., ICSAMOS 2010: 200-207
Giorgos Passas, Manolis Katevenis, Dionisios N. Pnevmatikatos, A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6% of Their Area., NOCS 2010: 87-95
Giovanni Agosta, Alessandro Barenghi, Fabrizio De Santis, Gerardo Pelosi, Record Setting Software Implementation of DES Using CUDA., ITNG 2010: 748-755
Giovanni Beltrame, Luca Fossati, Donatella Sciuto, Decision-Theoretic Design Space Exploration of Multiprocessor Platforms., IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1083-1095 (2010)
Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini, Networks on Chips: from research to products., DAC 2010: 300-305
Giovanni Mariani, Aleksandar Brankovic, Gianluca Palermo, Jovana Jovic, Vittorio Zaccaria, Cristina Silvano, A correlation-based design space exploration methodology for multi-processor systems-on-chip., DAC 2010: 120-125
Giovanni Mariani, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, An industrial design space exploration framework for supporting run-time resource management on multi-core systems., DATE 2010: 196-201
Giuseppe Pasetti, Luca Fanucci, R. Serventi, A High-Voltage Low-Power DC-DC buck regulator for automotive applications., DATE 2010: 937-940
Gonzalo Zarza, Diego Lugones, Daniel Franco, Emilio Luque, FT-DRB: A Method for Tolerating Dynamic Faults in High-Speed Interconnection Networks., PDP 2010: 77-84
Gonzalo Zarza, Diego Lugones, Daniel Franco, Emilio Luque, Deadlock Avoidance for Interconnection Networks with Multiple Dynamic Faults., PDP 2010: 276-280
Gonzalo Zarza, Diego Lugones, Daniel Franco, Emilio Luque, Fault-tolerant Routing for Multiple Permanent and Non-permanent Faults in HPC Systems., PDPTA 2010: 144-150
Graham R. Markall, David A. Ham, Paul H. J. Kelly, Towards generating optimised finite element solvers for GPUs from high-level specifications., Procedia CS 1(1): 1815-1823 (2010)
Grigori Fursin, Olivier Temam, Collective optimization: A practical collaborative approach., TACO 7(4): 20 (2010)
Guillermo Vigueras, Juan M. Orduña, Miguel Lozano, A GPU-Based Multi-agent System for Real-Time Simulations., PAAMS 2010: 15-24
Guillermo Vigueras, Miguel Lozano, Juan Manuel Orduña, Francisco Grimaldo, A comparative study of partitioning methods for crowd simulations., Appl. Soft Comput. 10(1): 225-235 (2010)
Guochun Shi, Volodymyr V. Kindratenko, Frederico Pratas, Pedro Trancoso, Michael Gschwind, Application Acceleration with the Cell Broadband Engine., Computing in Science and Engineering 12(1): 76-81 (2010)
Guy Sagy, Daniel Keren, Izchak Sharfman, Assaf Schuster, Distributed Threshold Querying of General Functions by a Difference of Monotonic Representation., PVLDB 4(2): 46-57 (2010)
Héctor Montaner, Federico Silla, José Duato, A practical way to extend shared memory support beyond a motherboard at low cost., HPDC 2010: 155-166
Héctor Pettenghi, Ricardo Chaves, Leonel Sousa, Maria J. Avedillo, An improved RNS generator 2n +/- k based on threshold logic., VLSI-SoC 2010: 119-124
Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Paolo Ienne, Improving FPGA Performance for Carry-Save Arithmetic., IEEE Trans. VLSI Syst. 18(4): 578-590 (2010)
Hagit Attiya, David Hay, Isaac Keslassy, Packet-Mode Emulation of Output-Queued Switches., IEEE Trans. Computers 59(10): 1378-1391 (2010)
Hai Ngoc Pham, Yan Zhang, Paal E. Engelstad, Tor Skeie, Frank Eliassen, Energy Minimization Approach for Optimal Cooperative Spectrum Sensing in Sensor-aided Cognitive Radio Networks., WICON 2010: 1-9
Hai-Xiang Lin, Michael Alexander, Martti Forsell, Andreas Knüpfer, Radu Prodan, Leonel Sousa, Achim Streit, Euro-Par 2009 - Parallel Processing Workshops HPPC HeteroPar PROPER ROIA UNICORE VHPC Delft The Netherlands August 25-28 2009 Revised Selected Papers, Springer 2010
Hans Vandierendonck, Sean Rul, Koen De Bosschere, Accelerating Multiple Sequence Alignment with the Cell BE Processor., Comput. J. 53(6): 814-826 (2010)
Hans Vandierendonck, Sean Rul, Koen De Bosschere, The Paralax infrastructure: automatic parallelization with a helping hand., PACT 2010: 389-400
Haohuan Fu, Oskar Mencer, Wayne Luk, FPGA Designs with Optimized Logarithmic Arithmetic., IEEE Trans. Computers 59(7): 1000-1006 (2010)
Harald Devos, Wim Meeus, Dirk Stroobandt, Towards a Tighter Integration of Generated and Custom-Made Hardware., ARC 2010: 426-434
Hatem Ltaief, Jakub Kurzak, Jack Dongarra, Rosa M. Badia, Scheduling two-sided transformations using tile algorithms on multicore architectures., Scientific Programming 18(1): 35-50 (2010)
Hayden Stainsby, Manel Taboada, Emilio Luque, Agent-based Simulation to Support Decision Making in Healthcare Management Planning., HEALTHINF 2010: 436-441
Hector Pettenghi, Maria Jose Avedillo, Jose Maria Quintana, Improved Nanopipelined RTD Adders Using Generalized Threshold Gates, IEEE Transactions on Nanotechnology, (in press)
Heiner Giefers, Marco Platzner, A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh NoC and Barrier., FPL 2010: 223-228
Heiner Giefers, Marco Platzner, A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics., ERSA 2010: 251-254
Henry Hoffmann, Jonathan Eastep, Marco D. Santambrogio, Jason E. Miller, Anant Agarwal, Application heartbeats for software performance and health., PPOPP 2010: 347-348
Herbert Jordan, Radu Prodan, Vlad Nae, Thomas Fahringer, Dynamic load management for MMOGs in distributed environments., Conf. Computing Frontiers 2010: 337-346
Hritam Dutta, Frank Hannig, Moritz Schmid, Joachim Keinert, Modeling and synthesis of communication subsystems for loop accelerator pipelines., ASAP 2010: 125-132
Hugues Cassé, Pascal Sainrat, Clément Ballabriga, Marianne De Michiel, Experimentation of WCET computation on both ends of automotive processor range., EDCC-CARS 2010: 67-70
Hung Manh La, Weihua Sheng, Flocking control of multiple agents in noisy environments., ICRA 2010: 4964-4969
Iasonas Filippopoulos, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, George Economakos, Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures., ISVLSI 2010: 133-138
Iasonas Polakis, Georgios Kontaxis, Spyros Antonatos, Eleni Gessiou, Thanasis Petsas, Evangelos P. Markatos, Using social networks to harvest email addresses., WPES 2010: 11-20
Ignacio Bravo, Marco D. Santambrogio, Design flows and system architectures for adaptive computing on reconfigurable platforms., Journal of Systems Architecture - Embedded Systems Design 56(11): 543-544 (2010)
Igor Böhm, Björn Franke, Nigel P. Topham, Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator., ICSAMOS 2010: 1-10
Igor Loi, Luca Benini, An efficient distributed memory interface for many-core platform with 3D stacked DRAM., DATE 2010: 99-104
Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini, 3D NoCs - Unifying inter & intra chip communication., ISCAS 2010: 3337-3340
Ilknur Cansu Kaynak, Yusuf Onur Koçberber, Oguz Ergin, Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands., Journal of Circuits Systems and Computers 19(8): 1689-1709 (2010)
Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser, Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation., DASIP 2010: 68-75
Isaac Gelado, Javier Cabezas, Nacho Navarro, John E. Stone, Sanjay J. Patel, Wen-mei W. Hwu, An asymmetric distributed shared memory model for heterogeneous parallel systems., ASPLOS 2010: 347-358
Isidoros Sideris, Nikos K. Moshopoulos, Kiamal Z. Pekmestzi, A hardware peripheral for Java bytecodes translation acceleration., SAC 2010: 552-553
Ismo Hänninen, Jarmo Takala, Binary Adders on Quantum-Dot Cellular Automata., Signal Processing Systems 58(1): 87-103 (2010)
Itamar Cohen, Ori Rottenstreich, Isaac Keslassy, Statistical Approach to Networks-on-Chip., IEEE Trans. Computers 59(6): 748-761 (2010)
Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto, Run-time mapping of applications on FPGA-based reconfigurable systems., ISCAS 2010: 3329-3332
Jörg Mische, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer, How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT., ARCS 2010: 2-14
Jürgen Becker, Eli Bozorgzadeh, João M. P. Cardoso, Aravind Dasu, Welcome message., IPDPS Workshops 2010: 1-2
J. Escudero, P. Garcia, F. J. Quiles, Jose Flich, J. Duato, Cost-Effective Congestion Management for Interconnection Networks Using Distributed Deterministic Routing, ICPADS
J. Flich, D. Bertozzi, Designing Networks On-Chip Architectures in the Nanoscale Era, CRC Taylor & Francis
J. Luna, Marios D. Dikaiakos, Manolis Marazakis, Theodoros Kyprianou, Data-Centric Privacy Protocol for Intensive Care Grids., IEEE Transactions on Information Technology in Biomedicine 14(6): 1327-1337 (2010)
J. Merino, V. Puente, J.A. Gregorio, ESP-NUCA: A Low-Cost Adaptive Non-Uniform Cache Architecture, The 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Jae Young Hur, Stephan Wong, Todor Stefanov, Design Trade-offs in Customized On-chip Crossbar Schedulers., Signal Processing Systems 58(1): 69-85 (2010)
Jae-Seung Yeom, Dimitrios S. Nikolopoulos, Strider: Runtime Support for Optimizing Strided Data Accesses on Multi-Cores with Explicitly Managed Memories., SC 2010: 1-11
Jakub Kurzak, Hatem Ltaief, Jack Dongarra, Rosa M. Badia, Scheduling dense linear algebra operations on multicore processors., Concurrency and Computation: Practice and Experience 22(1): 15-44 (2010)
Jamin Naghmouchi, Daniele Paolo Scarpazza, Mladen Berekovic, Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization., ICS 2010: 337-348
Jan-Philipp Steghöfer, Rolf Kiefhaber, Karin Leichtenstern, Yvonne Bernard, Lukas Klejnowski, Wolfgang Reif, Theo Ungerer, Elisabeth André, Jörg Hähner, Christian Müller-Sch, Trustworthy Organic Computing Systems: Challenges and Perspectives., ATC 2010: 62-76
Jaume Joven, Andrea Marongiu, Federico Angiolini, Luca Benini, Giovanni De Micheli, Exploring programming model-driven QoS support for NoC-based platforms., CODES+ISSS 2010: 65-74
Javier Bueno, Xavier Martorell, Juan José Costa, Toni Cortes, Eduard Ayguadé, Guansong Zhang, Christopher Barton, Raúl Silvera, Reducing data access latency in SDSM systems using runtime optimizations., CASCON 2010: 160-173
Javier Díaz, Sebastián Reyes, Rosa M. Badia, Alfonso Niño, Camelia Muñoz-Caro, A general model for the generation and scheduling of parameter sweep experiments in computational grid environments., Procedia CS 1(1): 565-572 (2010)
Javier García Blas, Florin Isaila, Jesús Carretero, David E. Singh, Félix García Carballeira, Implementation and Evaluation of File Write-Back and Prefetching for MPI-IO Over GPFS., IJHPCA 24(1): 78-92 (2010)
Javier Navaridas, José Miguel-Alonso, Francisco Javier Ridruejo, Wolfgang Denzel, Reducing complexity in tree-like computer interconnection networks., Parallel Computing 36(2-3): 71-85 (2010)
Javier Navaridas, Luis A. Plana, José Miguel-Alonso, Mikel Luján, Stephen B. Furber, SpiNNaker: impact of traffic locality causality and burstiness on the performance of the interconnection network., Conf. Computing Frontiers 2010: 11-20
Jayanth Gummaraju, Ben Sander, Laurent Morichetti, Benedict R. Gaster, Lee W. Howes, Efficient implementation of GPGPU synchronization primitives on CPUs., Conf. Computing Frontiers 2010: 85-86
Jean-Marie Mirebeau, Albert Cohen, Anisotropic Smoothness Classes: From Finite Element Approximation to Image Models., Journal of Mathematical Imaging and Vision 38(1): 52-69 (2010)
Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich, A system-level synthesis approach from formal application models to generic bus-based MPSoCs., ICSAMOS 2010: 118-125
Jens Knoop, Wolf Zimmermann, On the Role of Non-functional Properties in Compiler Verification., ISoLA (2) 2010: 491-495
Jerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms., DATE 2010: 753-758
Jeremy Singer, Gavin Brown, Mikel Luján, Adam Pocock, Paraskevas Yiapanis, Fundamental Nano-Patterns to Characterize and Classify Java Methods., Electr. Notes Theor. Comput. Sci. 253(7): 191-204 (2010)
Jeremy Singer, Richard E. Jones, Gavin Brown, Mikel Luján, The economics of garbage collection., ISMM 2010: 103-112
Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre, SDR platform for 802.11n and 3-GPP LTE., ICSAMOS 2010: 318-323
Jesús Carretero, J. Daniel Garcia, Scalable Storage Systems and High-Perfomance Applications., The Journal of Supercomputing 51(1): 1-2 (2010)
Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Duato, An Efficient Strategy for Reducing Head-of-Line Blocking in Fat-Trees., Euro-Par (2) 2010: 413-427
Jie Xiang, Yan Zhang, Tor Skeie, Medium access control protocols in cognitive radio networks., Wireless Communications and Mobile Computing 10(1): 31-49 (2010)
Jie Xiang, Yan Zhang, Tor Skeie, L. Xie, Downlink Spectrum Sharing for Cognitive Radio Femtocell Networks., IEEE Systems Journal 4(4): 524-534 (2010)
João Bispo, João M. P. Cardoso, On Identifying Segments of Traces for Dynamic Compilation., FPL 2010: 263-266
João M. P. Cardoso, Pedro C. Diniz, Markus Weinhardt, Compiling for reconfigurable computing: A survey., ACM Comput. Surv. 42(4): (2010)
Joachim Falk, Christian Zebelein, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya, Analysis of SystemC actor networks for efficient synthesis., ACM Trans. Embedded Comput. Syst. 10(2): 18 (2010)
Joan Aracil, Carlos Domínguez, Houcine Hassan, Alfons Crespo, Real-Time Linux Framework for Designing Parallel Mobile Robotic Applications., ICA3PP (2) 2010: 454-463
Joan-Lluís Ferrer, Elvira Baydal, Antonio Robles, Pedro López, José Duato, A Scalable and Early Congestion Management Mechanism for MINs., PDP 2010: 43-50
John Corredor, Juan C. Moure, Dolores Rexachs, Daniel Franco, Emilio Luque, Active learning processes to study memory hierarchy on Multicore systems., Procedia CS 1(1): 921-930 (2010)
John Corredor, Juan C. Moure, Dolores Rexachs, Daniel Franco, Emilio Luque, Selecting a Suitable Multicore System for Shared-memory Parallel Applications., PDPTA 2010: 228-234
Jonathan Barre, Christine Rochange, Pascal Sainrat, Architecture d'un processeur multiflot orienté temps-réel., Technique et Science Informatiques 29(2): 157-178 (2010)
Jonathan Mak, Karl-Filip Faxén, Sverker Janson, Alan Mycroft, Estimating and Exploiting Potential Parallelism by Source-Level Dependence Profiling., Euro-Par (1) 2010: 26-37
Jonathan Rubin, Ian Watson, Similarity-Based Retrieval and Solution Re-use Policies in the Game of Texas Hold'em., ICCBR 2010: 465-479
Jons-Tobias Wamhoff, Torvald Riegel, Christof Fetzer, Pascal Felber, RobuSTM: A Robust Software Transactional Memory., SSS 2010: 388-404
Jorda Polo, David Carrera, Yolanda Becerra, Malgorzata Steinder, Ian Whalley, Performance-driven task co-scheduling for MapReduce environments., NOMS 2010: 373-380
Jordi Guitart, Jordi Torres, Eduard Ayguadé, A survey on performance management for internet applications., Concurrency and Computation: Practice and Experience 22(1): 68-106 (2010)
Jorge Ejarque, Marc de Palol, Iñigo Goiri, Ferran Julià, Jordi Guitart, Rosa M. Badia, Jordi Torres, Exploiting semantics and virtualization for SLA-driven resource allocation in service providers., Concurrency and Computation: Practice and Experience 22(5): 541-572 (2010)
Jorge Ejarque, Raúl Sirvent, Rosa M. Badia, A Multi-agent Approach for Semantic Resource Allocation., CloudCom 2010: 335-342
Jorge González-Domínguez, Guillermo L. Taboada, Basilio B. Fraguela, María J. Martín, Juan Touriño, Servet: A benchmark suite for autotuning on multicore clusters., IPDPS 2010: 1-9
José M. Pérez, Félix García-Carballeira, Jesús Carretero, Alejandro Calderón, Javier Fernández, Branch replication scheme: A new model for data replication in large scale data grids, Future Generation Computer Systems , Volume 26 Issue 1, Elsevier Science Publishers B. V., January 2010
José Duato, Antonio J. Peña, Federico Silla, Rafael Mayo, Enrique S. Quintana-Ortí, rCUDA: Reducing the number of GPU-based accelerators in high performance clusters., HPCS 2010: 224-231
José Flich, Alfonso Urso, Ulrich Bruening, Giuseppe Di Fatta, High Performance Networks., Euro-Par (2) 2010: 412
José L. Abellán, Juan Fernández, Manuel E. Acacio, Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats., The Journal of Supercomputing 53(2): 247-268 (2010)
José L. Abellán, Juan Fernández, Manuel E. Acacio, Efficient and scalable barrier synchronization for many-core CMPs., Conf. Computing Frontiers 2010: 73-74
José L. Ayala, Arvind Sridhar, David Cuesta, Thermal modeling and analysis of 3D multi-processor chips., Integration 43(4): 327-341 (2010)
José L. Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares, Parallel and Distributed Optimization of Dynamic Data Structures for Multimedia Embedded Systems., Parallel and Distributed Computational Intelligence 2010: 263-290
José L. Risco-Martín, David Atienza, José Manuel Colmenar, Oscar Garnica, A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems., Parallel Computing 36(10-11): 572-590 (2010)
José Luis Ayala, Cándido Méndez, Marisa López-Vallejo, Thermal analysis and modeling of embedded processors., Computers & Electrical Engineering 36(1): 142-154 (2010)
José Luis March, Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Duato, Extending a Multicore Multithread Simulator to Model Power-Aware Hard Real-Time Systems., ICA3PP (2) 2010: 444-453
José Luis Risco-Martín, José Manuel Colmenar, David Atienza, José Ignacio Hidalgo, Simulation of High-Performance Memory Allocators., DSD 2010: 275-282
José M. Cecilia, José M. García, Ginés D. Guerrero, Miguel A. Martínez-del-Amor, Ignacio Pérez-Hurtado, Mario J. Pérez-Jiménez, Simulation of P systems with active membranes on CUDA., Briefings in Bioinformatics 11(3): 313-322 (2010)
José M. Claver, P. Agustí, Miguel Arevalillo-Herráez, G. León, Manel Canseco, A reconfigurable platform for evaluating the performance of QoS networks., Journal of Systems Architecture - Embedded Systems Design 56(4-6): 191-207 (2010)
José Manuel Colmenar, José L. Risco-Martín, David Atienza, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution., GECCO 2010: 1227-1234
José Villalón, Francisco Micó, Pedro Cuenca, Luis Orozco-Barbosa, Multiservice unicast/multicast communications over IEEE 802.11e networks., Telecommunication Systems 43(1-2): 59-72 (2010)
Jose Alexander Guevara, Eduardo César, Joan Sorribes, Andreu Moreno, Tomàs Margalef, Emilio Luque, A Performance Tuning Strategy for Complex Parallel Application., PDP 2010: 103-110
Jose Gonzalez-Mora, Fernando De la Torre, Nicolas Guil, Emilio L. Zapata, Learning a generic 3D face model from 2D image databases using incremental Structure-from-Motion., Image Vision Comput. 28(7): 1117-1129 (2010)
Jose Rodrigo Sanjurjo, Margarita Amor, Emilio J. Padrón, Ramon Doallo, Montserrat Bóo, Uniform partitioning of Monte Carlo radiosity on GPUs., HPCS 2010: 477-483
Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich, Virtual area management: Multitasking on dynamically partially reconfigurable devices., IPDPS Workshops 2010: 1-4
Josep Domènech, José A. Gil, Julio Sahuquillo, Ana Pont, Speculative Validation of Web Objects for Further Reducing the User-Perceived Latency., Networking 2010: 239-250
Josep Domènech, José A. Gil, Julio Sahuquillo, Ana Pont, Using current web page structure to improve prefetching performance., Computer Networks 54(9): 1404-1417 (2010)
Josep M. Pérez, Rosa M. Badia, Jesús Labarta, Handling task dependencies under strided and aliased references., ICS 2010: 263-274
Juan Angel Lorenzo, Juan Carlos Pichel, David LaFrance-Linden, Francisco Fernandez Rivera, David Exposito Singh, Lessons Learnt Porting Parallelisation Techniques for Irregular Codes to NUMA Systems., PDP 2010: 213-217
Juan Carlos Pichel, Dora Blanco Heras, José Carlos Cabaleiro, A. J. García-Loureiro, Francisco F. Rivera, Increasing the Locality of Iterative Methods and Its Application to the Simulation of Semiconductor Devices., IJHPCA 24(2): 136-153 (2010)
Juan Carlos Saez, Alexandra Fedorova, Manuel Prieto, Hugo Vegas, Operating system support for mitigating software scalability bottlenecks on asymmetric multicore processors., Conf. Computing Frontiers 2010: 31-40
Juan Carlos Saez, Manuel Prieto, Alexandra Fedorova, Sergey Blagodurov, A comprehensive scheduler for asymmetric multicore systems., EuroSys 2010: 139-152
Juan Gonzalez, Judit Gimenez, Jesús Labarta, Performance Data Extrapolation in Parallel Codes., ICPADS 2010: 155-163
Juan Hamers, Lieven Eeckhout, Scenario-Based Resource Prediction for QoS-Aware Media Processing., IEEE Computer 43(10): 56-63 (2010)
Juan M. Tirado, Daniel Higuero, Florin Isaila, Jesús Carretero, Adriana Iamnitchi, Affinity P2P: A self-organizing content-based locality-aware collaborative peer-to-peer network., Computer Networks 54(12): 2056-2070 (2010)
Kamana Sigdel, Mark Thompson, Carlo Galuzzi, Andy D. Pimentel, Koen Bertels, Evaluation of runtime task mapping heuristics with rSesame - a case study., DATE 2010: 831-836
Kamil Kedzierski, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Adapting cache partitioning algorithms to pseudo-LRU replacement policies., IPDPS 2010: 1-12
Karan Singh, Matthew Curtis-Maury, Sally A. McKee, Filip Blagojevic, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz, Comparing Scalability Prediction Strategies on an SMP of CMPs., Euro-Par (1) 2010: 143-155
Karel Bruneel, Dirk Stroobandt, TROUTE: A Reconfigurability-Aware FPGA Router., ARC 2010: 207-218
Kassian Plankensteiner, Radu Prodan, Thomas Fahringer, Scheduling Scientific Workflows to Meet Soft Deadlines in the Absence of Failure Models., Euro-Par (1) 2010: 367-378
Katerina Doka, Dimitrios Tsoumakos, Nectarios Koziris, Distributing the power of OLAP., HPDC 2010: 324-327
Katerina Doka, Dimitrios Tsoumakos, Nectarios Koziris, Brown dwarf: a P2P data-warehousing system., CIKM 2010: 1945-1946
Kazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Dan Cotofana, Memoryless RNS-to-binary converters for the {2n+1 - 1 2n 2n - 1} moduli set., ASAP 2010: 301-304
Kees G. W. Goossens, Dongrui She, Aleksandar Milutinovic, Anca Mariana Molnos, Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications., DSD 2010: 107-114
Kees Goossens, Andreas Hansson, The aethereal network on chip after ten years: goals evolution lessons and future., DAC 2010: 306-311
Kenneth Hoste, Andy Georges, Lieven Eeckhout, Automated just-in-time compiler tuning., CGO 2010: 62-72
Kevin Williams, Jason McCandless, David Gregg, Dynamic interpretation for dynamic scripting languages., CGO 2010: 278-287
Kleopatra Konstanteli, Tommaso Cucinotta, Theodora A. Varvarigou, Optimum allocation of distributed service workflows with probabilistic real-time guarantees., Service Oriented Computing and Applications 4(4): 229-243 (2010)
Koen Bertels, Vlad Mihai Sima, Yana Yankova, Georgi Kuzmanov, Wayne Luk, José Gabriel F. Coutinho, Fabrizio Ferrandi, Christian Pilato, Marco Lattuada, Donatella Sciuto, Andrea Michelotti, HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms., IEEE Micro 30(5): 88-97 (2010)
Konstantinos Krikellas, Stratis Viglas, Marcelo Cintra, Generating code for holistic query evaluation., ICDE 2010: 613-624
Kornilios Kourtis, Georgios I. Goumas, Nectarios Koziris, Exploiting compression opportunities to improve SpMxV performance on shared memory systems., TACO 7(3): 16 (2010)
Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis, A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures., Journal of Circuits Systems and Computers 19(3): 701-717 (2010)
Kostas Siozios, Dimitrios Soudris, Dionisios N. Pnevmatikatos, A Framework for Enabling Fault Tolerance in Reconfigurable Architectures., ARC 2010: 257-268
Kostas Siozios, Iraklis Anagnostopoulos, Dimitrios Soudris, A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd., ISVLSI 2010: 444-445
Krisztián Flautner, Optimize your power and performance yields and regain those sleepless nights., DATE 2010: 1006
Kuen Hung Tsoi, Anson H. T. Tse, Peter Pietzuch, Wayne Luk, Programming framework for clusters with heterogeneous accelerators., SIGARCH Computer Architecture News 38(4): 53-59 (2010)
Kuen Hung Tsoi, Wayne Luk, Axel: a heterogeneous cluster with FPGAs and GPUs., FPGA 2010: 115-124
L. C. Aparicio, J. Segarra, C. Rodríguez, J. L. Villarroel, V. Viñals, Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems, RTCSA 2010 319;328
Lara G. Villanueva, Gustavo Marrero Callicó, Félix Tobajas, Sebastián López, Valentin de Armas, José Francisco López, Roberto Sarmiento, Medical Diagnosis Improvement Through Image Quality Enhancement Based on Super-Resolution., DSD 2010: 259-262
Larbi Boubchir, Amine Naït-Ali, Eric Petit, Multivariate statistical modeling of images in sparse multiscale transforms domain., ICIP 2010: 1877-1880
Lars J. Svensson, Johnny Pihl, Daniel A. Andersson, Per Larsson-Edefors, On-chip power supply noise and its implications on timing., ACM Great Lakes Symposium on VLSI 2010: 389-392
Laura Prada, José Daniel García, Jesús Carretero, Using write Buffering and Read Prefetching Between Flash and Disk Drives to Save Energy in a Hybrid System., PDPTA 2010: 332-338
Leandro Fiorin, Alberto Ferrante, Konstantinos Padarnitsas, Stefano Carucci, Hardware-assisted security enhanced Linux in embedded systems: a proposal., WESS 2010: 3
Leandro Fiorin, Gianluca Palermo, Cristina Silvano, A Monitoring System for NoCs, ACM
Lei Gao, Atakelty Hailu, Integrating Recreational Fishing Behaviour within a Reef Ecosystem as a Platform for Evaluating Management Strategies., AINA 2010: 1286-1291
Lei Gao, Jeff Durkin, Atakelty Hailu, An Agent-based Model for Recreational Fishing Management Evaluation in a Coral Reef Environment., ICAART (2) 2010: 200-205
Lei Gao, Lin Qi, Enqing Chen, Xiaomin Mu, Ling Guan, Recognizing Human Emotional State Based on the Phase Information of the Two Dimensional Fractional Fourier Transform., PCM (2) 2010: 694-704
Leian Liu, Zhiqiang Chen, Dashun Yan, Yi Lu, Hongjiang Wang, RFID in Supply Chain Management., ICEE 2010: 3279-3282
Leian Liu, Zhiqiang Chen, Ling Yang, Yi Lu, Hongjiang Wang, Research on the Security Issues of RFID-Based Supply Chain., ICEE 2010: 3267-3270
Li Su, Philip Barnard, Howard Bowman, On the Fringe of Awareness: The Glance-Look Model of Attention-Emotion Interactions., ICANN (3) 2010: 504-509
Lian Li, Jingling Xue, Jens Knoop, Scratchpad memory allocation for data aggregates via interval coloring in superperfect graphs., ACM Trans. Embedded Comput. Syst. 10(2): 28 (2010)
Lieven Eeckhout, Computer Architecture Performance Evaluation Methods, Morgan & Claypool Publishers 2010
Lincoln Gray, Jennifer A. McCabe, David Bernstein, Constructed charts of vaccination strategies., Health Informatics Journal 16(1): 25-34 (2010)
Lionel Lacassagne, Bertrand Zavidovique, Light Speed Labeling: Efficient Connected Component Labeling on RISC architectures, Journal of Real-Time Image Processing
Lotfi Mhamdi, Kees Goossens, Iria Varela Senin, Buffered Crossbar Fabrics Based on Networks on Chip., CNSR 2010: 74-79
Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan, Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework., SC 2010: 1-11
Luca Amati, Cristiana Bolchini, Fabio Salice, Federico Franzoso, A Formal Condition to Stop an Incremental Automatic Functional Diagnosis., DSD 2010: 637-643
Luca Benini, Alberto Bocca, Alberto Bonanno, Alberto Macii, Enrico Macii, Jean-Luc Nagel, Christian Piguet, Massimo Poncino, A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits., J. Low Power Electronics 6(1): 44-55 (2010)
Luca Benini, Davide Brunelli, Chiara Petrioli, Simone Silvestri, GENESI: Green sEnsor NEtworks for Structural monItoring., SECON 2010: 1-3
Luca Fanucci, Giuseppe Pasetti, P. D'Abramo, R. Serventi, F. Tinfena, P. Chassard, L. Labiste, P. Tisserand, An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability., DATE 2010: 526-531
Lucia D'Acunto, Michel Meulpolder, Rameez Rahman, Johan A. Pouwelse, Henk J. Sips, Modeling and analyzing the effects of firewalls and NATs in P2P swarming systems., IPDPS Workshops 2010: 1-8
Luigi Carro, Georgi Gaydadjiev, Challenges for embedded multicore architecture., CASES 2010: 259-260
Luigi Carro, Stephan Wong, Special session on multicore architectures for embedded systems., ICSAMOS 2010: 332
Luis Albert, Víctor Planes, Carlos Domínguez, Houcine Hassan, Embedded GPS Path Planning for Mobile Robots., ESA 2010: 199-
Luiz F. Bittencourt, Rizos Sakellariou, Edmundo R. M. Madeira, DAG Scheduling Using a Lookahead Variant of the Heterogeneous Earliest Finish Time Algorithm., PDP 2010: 27-34
Luk Van Ertvelde, Lieven Eeckhout, Workload Reduction and Generation Techniques., IEEE Micro 30(6): 57-65 (2010)
M. B. C. Alioto, P. Bennati, R. Giorgi, Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed, IEEE Int.l Symp. on Circuits and Systems (ISCAS), ISBN:978-1-4244-5309-2, Paris, France, May 2010, pp. 37-40
M. Mustafa Rafique, Ali Raza Butt, Dimitrios S. Nikolopoulos, Designing Accelerator-Based Distributed Systems for High Performance., CCGRID 2010: 165-174
M. Porta, K. Maillet, Marisa Gil, Dec-CS: The Computer Science Declining Phenomenon, World Congress on Engineering and Computer Science 2010 (WCECS 2010), October 20-22, San Francisco, USA
Mafijul Md Islam, Per Stenström, Characterization and exploitation of narrow-width loads: the narrow-width cache approach., CASES 2010: 227-236
Magnus Jahre, Lasse Natvig, Computational Computer Architecture Research at NTNU., ERCIM News 2010(81): 0 (2010)
Magnus Jahre, Marius Grannæs, Lasse Natvig, DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems., HiPEAC 2010: 292-306
Maha Idrissi-Aouad, René Schott, Olivier Zendra, Genetic Heuristics for Reducing Memory Energy Consumption in Embedded Systems., ICSOFT (2) 2010: 394-402
Mahmood Ahmadi, Asadollah Shahbahrami, Stephan Wong, Collaboration of Reconfigurable Processors in Grid Computing for Multimedia Kernels., GPC 2010: 5-14
Mahmood Fazlali, Ali Zakerolhosseini, Georgi Gaydadjiev, A Modified Merging Approach for Datapath Configuration Time Reduction., ARC 2010: 318-328
Mahmood Fazlali, Mojtaba Sabeghi, Ali Zakerolhosseini, Koen Bertels, Efficient task scheduling for runtime reconfigurable systems., Journal of Systems Architecture - Embedded Systems Design 56(11): 623-632 (2010)
Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero, Utilization driven power-aware parallel job scheduling., Computer Science - R&D 25(3-4): 207-216 (2010)
Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki, A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization., ISSPIT 2010: 528-531
Majed Chatti, Sami Yehia, Claude Timsit, Soraya Zertal, A hypercube-based NoC routing algorithm for efficient all-to-all communications in embedded image and signal processing applications., HPCS 2010: 623-630
Manoj Gupta, Fermín Sánchez, Josep Llosa, A low cost split-issue technique to improve performance of SMT clustered VLIW processors., IPDPS 2010: 1-12
Manoj Gupta, Fermín Sánchez, Josep Llosa, CSMT: Simultaneous Multithreading for Clustered VLIW Processors., IEEE Trans. Computers 59(3): 385-399 (2010)
Manolis Katevenis, Vassilis Papaefstathiou, Stamatis Kavadias, Dionisios Pnevmatikatos, Federico Silla, Dimitrios Nikolopoulos, Explicit Communication and Synchronization in SARC, IEEE Computer Society (IEEE Micro, vol. 30)
Manuel F. Dolz, Juan C. Fernández, Rafael Mayo, Enrique S. Quintana-Ortí, EnergySaving Cluster Roll: Power Saving System for Clusters., ARCS 2010: 162-173
Manuel Fogue, Francisco D. Igual, Enrique S. Quintana-Ortí, Robert A. van de Geijn, Retargeting PLAPACK to clusters with hardware accelerators., HPCS 2010: 444-451
Marc Casas, Rosa M. Badia, Jesús Labarta, Automatic Phase Detection and Structure Extraction of MPI Applications., IJHPCA 24(3): 335-360 (2010)
Marc Daumas, David Lester, Érik Martin-Dorel, Annick Truffert, Improved bound for stochastic formal correctness of numerical algorithms., ISSE 6(3): 173-179 (2010)
Marc Duranton, Jan Hoogerbrugge, Ghiath Al-kadi, Surendra Guntur, Andrei Terechko, Rapid Technology-Aware Design Space Exploration for Embedded Heterogeneous Multiprocessorsrnin "Processor and System-on-Chip Simulation" ed. Leupers, Rainer and Temam, Olivier, Springer
Marcel Medwed, François-Xavier Standaert, Johann Großschädl, Francesco Regazzoni, Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices., AFRICACRYPT 2010: 279-296
Marcela Zuluaga, Nigel P. Topham, Exploring the unified design-space of custom-instruction selection and resource sharing., ICSAMOS 2010: 282-291
Marco Aldinucci, Massimiliano Meneghin, Massimo Torquati, Efficient Smith-Waterman on Multi-core with FastFlow., PDP 2010: 195-199
Marco Aldinucci, Salvatore Ruggieri, Massimo Torquati, Porting Decision Tree Algorithms to Multicore Using FastFlow., ECML/PKDD (1) 2010: 7-23
Marco Benocci, Carlo Tacconi, Elisabetta Farella, Luca Benini, Lorenzo Chiari, Laura Vanzago, Accelerometer-based fall detection using optimized ZigBee data streaming., Microelectronics Journal 41(11): 703-710 (2010)
Marco Ceriani, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, Antonino Tumeo, Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation., GECCO 2010: 1267-1274
Marco D. Santambrogio, Paolo Roberto Grassi, Davide Candiloro, Donatella Sciuto, Analysis and validation of partially dynamically reconfigurable architecture based on Xilinx FPGAs., IPDPS Workshops 2010: 1-4
Marco Lattuada, Fabrizio Ferrandi, Performance modeling of embedded applications with zero architectural knowledge., CODES+ISSS 2010: 277-286
Marco Lattuada, Fabrizio Ferrandi, Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP., CIT 2010: 1895-1901
Marina Alonso, Salvador Coll, Juan Miguel Martínez, Vicente Santonja, Pedro López, José Duato, Power saving in regular interconnection networks., Parallel Computing 36(12): 696-712 (2010)
Mario Lassnig, Thomas Fahringer, Vincent Garonne, Angelos Molfetas, Miguel Branco, Identification Modelling and Prediction of Non-periodic Bursts in Workloads., CCGRID 2010: 485-494
Marisa Gil, M-J. Fernandez, R. Cusso, C. Crusafon, Real projects to involve undergraduate students in CS degrees, IEEE EDUCON Education Engineering 2010 – The Future of Global Learning Engineering Education, April 14-16, Madrid, SPAIN
Marisa Gil, Roser Cusso, Carlota Crusafon, Maria Jose Fernandez-Mostaza, Real Projects to involve undergraduate students in CS degrees. IEEE EDUCON - Education Engineering 2010, Madrid,Spain, IEEE
Marius Grannæs, Magnus Jahre, Lasse Natvig, Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching., HiPEAC 2010: 247-261
Mariusz Grad, Christian Plessl, PivPav: An Open source Circuit Library with Benchmarking Facilities., ERSA 2010 144-150
Mariusz Grad, Christian Plessl, Pruning the Design Space for Just-in-time Processor Customization, ReConFig 2010
Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner, AnySP: Anytime Anywhere Anyway Signal Processing., IEEE Micro 30(1): 81-91 (2010)
Markos Fountoulakis, Manolis Marazakis, Michail Flouris, Angelos Bilas, DARC: design and evaluation of an I/O controller for data protection., SYSTOR 2010
Marouane Belaoucha, Denis Barthou, Adrien Eliche, Sid Ahmed Ali Touati, FADAlib: an open source C++ library for fuzzy array dataflow analysis., Procedia CS 1(1): 2075-2084 (2010)
Martín Abadi, Tim Harris, Katherine F. Moore, A model of dynamic separation for transactional memory., Inf. Comput. 208(10): 1093-1117 (2010)
Martijn Briejer, Cor Meenderinck, Ben H. H. Juurlink, Extending the Cell SPE with Energy Efficient Branch Prediction., Euro-Par (1) 2010: 304-315
Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Robust design of embedded systems., DATE 2010: 1578-1583
Martin Schindewolf, David Kramer, Marcelo Cintra, Compiler-Directed Performance Model Construction for Parallel Programs., ARCS 2010: 187-198
Martin Schoeberl, Thomas B. Preußer, Sascha Uhrig, The embedded Java benchmark suite JemBench., JTRES 2010: 120-127
Martina Maggio, Henry Hoffmann, Marco D. Santambrogio, Anant Agarwal, Alberto Leva, Controlling software applications via resource allocation within the heartbeats framework., CDC 2010: 3736-3741
Mateo Valero, Nacho Navarro, Multicore: The View from Europe., IEEE Micro 30(5): 2-4 (2010)
Matteo Pusceddu, Simone Ceccolini, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo, A Compact Transactional Memory Multiprocessor System on FPGA., FPL 2010: 578-581
Matthias Braun, Christoph Mallon, Sebastian Hack, Preference-Guided Register Assignment., CC 2010: 205-223
Matthias Hartmann, Vasileios (Vassilis) Pantazis, Tom Vander Aa, Mladen Berekovic, Christian Hochberger, Still Image Processing on Coarse-Grained Reconfigurable Array Architectures., Signal Processing Systems 60(2): 225-237 (2010)
Matthias Hauswirth, Peter F. Sweeney, Amer Diwan, Temporal vertical profiling., Softw. Pract. Exper. 40(8): 627-654 (2010)
Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich, A rapid prototyping system for error-resilient multi-processor systems-on-chip., DATE 2010: 375-380
Matthias May, Thomas Ilnseher, Norbert Wehn, Wolfgang Raab, A 150Mbit/s 3GPP LTE Turbo code decoder., DATE 2010: 1420-1425
Matthias S. Müller, Eduard Ayguadé, Guest Editors' Introduction., International Journal of Parallel Programming 38(5-6): 339-340 (2010)
Mauricio Alvarez, David Luengo, Michalis Titsias, Neil D. Lawrence, Efficient Multioutput Gaussian Processes through Variational Inducing Kernels., Journal of Machine Learning Research - Proceedings Track 9: 25-32 (2010)
Maurizio Palesi, Rickard Holsmark, Xiahoang Wang, Shashi Kumar, Mai Yang, Y. Jiang, Vincenzo Catania, M. Palesi, R. Holsmark, X. Wang, S. Kumar, M. Yang, Y. Jiang, V. Catania. A Novel Mechanism to Guarantee In-Order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip, 13th Euromicro Conference On Digital System Design Architectures, Methods and Tools
Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania, An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip., DSD 2010: 37-44
Maurizio Palesi, Shashi Kumar, Vincenzo Catania, Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Maurizio Palesi, Shashi Kumar, Vincenzo Catania, Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip., IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 426-440 (2010)
Maury Bramson, Yi Lu, Balaji Prabhakar, Randomized load balancing with general service time distributions., SIGMETRICS 2010: 275-286
Maximilian Berger, Thomas Fahringer, Practical Experience from Porting and Executing the Wien2k Application on the EGEE Production Grid Infrastructure., J. Grid Comput. 8(2): 261-279 (2010)
Mehmet Kayaalp, Oguz Ergin, Osman S. Ünsal, Mateo Valero, Exploiting Inactive Rename Slots for Detecting Soft Errors., ARCS 2010: 126-137
Miao Wang, Nicolas Benoit, François Bodin, Zhiying Wang, Model Driven Iterative Multi-dimensional Parallelization of Multi-task Programs for the Cell BE: A Genetic Algorithm-Based Approach., PDP 2010: 218-222
Michèle Gouiffès, Florence Laguzet, Lionel Lacassagne, Projection-histograms for mean-shift tracking., ICIP 2010: 4617-4620
Michael A. Hicks, Michiel W. van Tol, Chris R. Jesshope, Towards scalable I/O on a many-core architecture., ICSAMOS 2010: 341-348
Michael Bauer, Mathias Pacher, Uwe Brinkschulte, Chip-Size Evaluation of a Multithreaded Processor Enhanced with a PID Controller., SEUS 2010: 3-12
Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich, Towards scalable system-level reliability analysis., DAC 2010: 234-239
Michael Gopshtein, Dror G. Feitelson, Empirical quantification of opportunities for content adaptation in web servers., SYSTOR 2010
Michael Maurer, Ivona Brandic, Rizos Sakellariou, Simulating Autonomic SLA Enactment in Clouds Using Case Based Reasoning., ServiceWave 2010: 25-36
Michael Merrett, Yangang Wang, Mark Zwolinski, Koushik Maharatna, Massimo Alioto, Design metrics for RTL level estimation of delay variability due to intradie (random) variations., ISCAS 2010: 2498-2501
Michail D. Flouris, Renaud Lachaize, Konstantinos Chasapis, Angelos Bilas, Extensible block-level storage virtualization in cluster-based systems., J. Parallel Distrib. Comput. 70(8): 800-824 (2010)
Michalis Polychronakis, Kostas G. Anagnostakis, Evangelos P. Markatos, Comprehensive shellcode detection using runtime heuristics., ACSAC 2010: 287-296
Michele Lombardi, Luca Benini, Abhishek Garg, Giovanni De Micheli, Methods for Designing Reliable Probe Arrays., BIBE 2010: 306-307
Michele Lombardi, Michela Milano, Martino Ruggiero, Luca Benini, Stochastic allocation and scheduling for conditional task graphs in multi-processor systems-on-chip., J. Scheduling 13(4): 315-345 (2010)
Michele Magno, Alessandro Lanza, Davide Brunelli, Luigi di Stefano, Luca Benini, Energy aware multimodal embedded video surveillance., VLSI-SoC 2010: 264-269
Michele Magno, Davide Brunelli, Piero Zappi, Luca Benini, Energy Efficient Cooperative Multimodal Ambient Monitoring., EuroSSC 2010: 56-70
Miguel Vázquez, Rubén Nogales-Cadenas, Javier Arroyo, Pedro Botías, Raul García, José María Carazo, Francisco Tirado, Alberto D. Pascual-Montano, Pedro Carmon, MARQ: an online tool to mine GEO for experiments with similar or opposite gene expression signatures., Nucleic Acids Research 38(Web-Server-Issue): 228-232 (2010)
Mikel Sanchez, Javier Del Ser, Pablo Prieto, David Dominguez, Design and implementation of a direct RF-to-digital UHF-TV multichannel transceiver., ISCAS 2010: 3925-3928
Mikko Kohvakka, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen, Energy-Efficient Reservation-Based Medium Access Control Protocol for Wireless Sensor Networks., EURASIP J. Wireless Comm. and Networking 2010: (2010)
Milan Tichý, Jan Schier, David Gregg, GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems., ACM Trans. Embedded Comput. Syst. 9(3): (2010)
Miquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero, Load balancing using dynamic cache allocation., Conf. Computing Frontiers 2010: 153-164
Miquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero, Load balancing using dynamic cache allocation, ACM Computing Frontiers
Mircea Namolaru, Albert Cohen, Grigori Fursin, Ayal Zaks, Ari Freund, Practical aggregation of semantical program properties for machine learning based optimization., CASES 2010: 197-206
Mladen Berekovic, Andy D. Pimentel, Editorial., Signal Processing Systems 60(2): 147-148 (2010)
Mohamed M. Sabry, Ayse Kivilcim Coskun, David Atienza, Fuzzy control for enforcing energy efficiency in high-performance 3D systems., ICCAD 2010: 642-648
Mohamed M. Sabry, José L. Ayala, David Atienza, Thermal-aware compilation for system-on-chip processing architectures., ACM Great Lakes Symposium on VLSI 2010: 221-226
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia Del Valle, Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs., ACM Great Lakes Symposium on VLSI 2010: 305-310
Mohamed-Walid Benabderrahmane, Louis-Noël Pouchet, Albert Cohen, Cédric Bastoul, The Polyhedral Model Is More Widely Applicable Than You Think., CC 2010: 283-303
Mohammad Ansari, Behram Khan, Mikel Luján, Christos Kotselidis, Chris C. Kirkham, Ian Watson, Improving Performance by Reducing Aborts in Hardware Transactional Memory., HiPEAC 2010: 35-49
Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini, Automatic synthesis of near-threshold circuits with fine-grained performance tunability., ISLPED 2010: 401-406
Mohammad Reza Kakoee, Igor Loi, Luca Benini, A new physical routing approach for robust bundled signaling on NoC links., ACM Great Lakes Symposium on VLSI 2010: 3-8
Mohammed A. Abutheraa, David Lester, Machine-efficient Chebyshev approximation for exact arithmetic: their use with first-order ordinary differential equations., SpringSim 2010: 84
Mojtaba Sabeghi, Hamid Mushtaq, Koen Bertels, Runtime multitasking support on polymorphic platforms., SIGARCH Computer Architecture News 38(4): 46-52 (2010)
Monica Serrano, Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Duato, A Scheduling Heuristic to Handle Local and Remote Memory in Cluster Computers., HPCC 2010: 35-42
Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen, Test Cost Analysis for 3D Die-to-Wafer Stacking., Asian Test Symposium 2010: 435-441
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser, IP Based Configurable SIMD Massively Parallel SoC., FPL 2010: 247-250
Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid, Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip., ARC 2010: 110-121
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid, Scalable mpNoC for massively parallel systems - Design and implementation on FPGA., Journal of Systems Architecture - Embedded Systems Design 56(7): 278-292 (2010)
Muhammad Aleem, Radu Prodan, Thomas Fahringer, JavaSymphony: A Programming and Execution Environment for Parallel and Distributed Many-Core Architectures., Euro-Par (2) 2010: 139-150
Muhammad Anis, Maurits Ortmanns, Norbert Wehn, Fully integrated UWB impulse transmitter and 402-to-405MHz super-regenerative receiver for medical implant devices., ISCAS 2010: 1213-1215
Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov, An efficient realization of forward integer transform in H.264/AVC intra-frame encoder., ICSAMOS 2010: 71-78
Muhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé, FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators., FPL 2010: 568-573
Muhammad Shafiq, Miquel Pericas, Nacho Navarro, Eduard Ayguade, FEM : A Step Towards a Common Memory Layout for FPGA Based Acceleratorsrn, IEEE FPL
Muhammad Shafiq, Miquel Pericas, Nacho Navarro, Eduard Ayguade, HLL Containers as a Way of Efficient Data Representation for Translation to FPGA Based Accelerators, HiPEAC - ACACES
Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors, Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor., DSD 2010: 675-680
Mujahed Eleyat, Lasse Natvig, Implementation of a linear programming solver on the Cell BE processor., Procedia CS 1(1): 1055-1064 (2010)
Mumtaz Siddiqui, Thomas Fahringer, Grid Resource Management: On-demand Provisioning Advance Reservation and Capacity Planning of Grid Resources, Springer 2010
Mustafa Imran Ali, Bashir M. Al-Hashimi, Joaquín Recas, David Atienza, Evaluation and design exploration of solar harvested-energy prediction algorithm., DATE 2010: 142-147
N. Puzovic, S. McKee, R. Eres, A. Zaks, P. Gai, S. Wong, R. Giorgi, A Multi-Pronged Approach to Benchmark Characterization, IEEE International Conference on Cluster Computing (CLUSTER2010) Poster Session, ISBN: 978-1-4244-8396-9, Heraclion (Greece)
Nadav Levison, Shlomo Weiss, Low power branch prediction for embedded application processors., ISLPED 2010: 67-72
Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul, A high-level synthesis flow for custom instruction set extensions for application-specific processors., ASP-DAC 2010: 707-712
Nancy M. Amato, Hubertus Franke, Paul H. J. Kelly, Proceedings of the 7th Conference on Computing Frontiers 2010 Bertinoro Italy May 17-19 2010, ACM 2010
Nicholas Nash, David Gregg, An output sensitive algorithm for computing a maximum independent set of a circle graph., Inf. Process. Lett. 110(16): 630-634 (2010)
Nicholas Nash, David Gregg, Comparing integer data structures for 32- and 64-bit keys., ACM Journal of Experimental Algorithmics 15: (2010)
Nick Barrow-Williams, Christian Fensch, Simon W. Moore, Proximity coherence for chip multiprocessors., PACT 2010: 123-134
Niels Penneman, Luc Perneel, Martin Timmerman, Bjorn De Sutter, An FPGA-Based Real-Time Event Sampler., ARC 2010: 364-371
Nikola Vujic, Marc González, Felipe Cabarcas, Alex Ramírez, Xavier Martorell, Eduard Ayguadé, DMA++: on the fly data realignment for on-chip memories., HPCA 2010: 1-12
Nikola Vujic, Marc González, Xavier Martorell, Eduard Ayguadé, Automatic Prefetch and Modulo Scheduling Transformations for the Cell BE Architecture., IEEE Trans. Parallel Distrib. Syst. 21(4): 494-505 (2010)
Nikolaos Chrysos, Lydia Y. Chen, Cyriel Minkenberg, Christoforos Kachris, Manolis Katevenis, End-to-end congestion management for non-blocking multi-stage switching fabrics., ANCS 2010: 6
Nikolaos Skalis, Lotfi Mhamdi, Performance Guarantees in Partially Buffered Crossbar Switches., GLOBECOM 2010: 1-6
Nikolas Ladas, Yiannakis Sazeides, Veerle Desmet, Performance-effective operation below Vcc-min., ISPASS 2010: 223-234
Nikos Anastasiadis, Isidoros Sideris, Kiamal Z. Pekmestzi, A fast multiplier-less edge detection accelerator for FPGAs., SAC 2010: 510-515
Nikos Chrysos, Manolis Katevenis, Distributed WFQ scheduling converging to weighted max-min fairness, Computer Networks (Elsevier)
Nikos Foutris, Mihalis Psarakis, Dimitris Gizopoulos, Xavier Vera, Antonio Gonzalez, MT-SBST: Self-Test Optimization in Multithreaded Multicore Architectures, IEEE International Test Conference (ITC), 2010
Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki, Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures., IEEE Micro 30(1): 29 (2010)
Nuno Sebastiao, Tiago Dias, Nuno Roma, Paulo F. Flores, Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phase., HPCS 2010: 16-23
Olga Golovanevsky, Alon Dayan, Ayal Zaks, David Edelsohn, Trace-Based Data Layout Optimizations for Multi-core Processors., HiPEAC 2010: 81-95
Olivier Temam, The rebirth of neural networks., ISCA 2010: 349
Ori Rottenstreich, Isaac Keslassy, Worst-Case TCAM Rule Expansion., INFOCOM 2010: 456-460
Otto Esko, Pekka Jääskeläinen, Pablo Huerta, Carlos S. de La Lama, Jarmo Takala, José Ignacio Martínez, Customized Exposed Datapath Soft-Core Design Flow with Compiler Support., FPL 2010: 217-222
Ozcan Ozturk, Improving chip multiprocessor reliability through code replication., Computers & Electrical Engineering 36(3): 480-490 (2010)
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan, Compiler directed network-on-chip reliability enhancement for chip multiprocessors., LCTES 2010: 85-94
Ozcan Ozturk, Rohit Kapoor, Vinay Chande, Jilei Hou, Bibhu Mohanty, Circuit-Switched Voice Services Over HSPA., VTC Spring 2010: 1-5
P. Carazo, R. Apolloni, F. Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado, L1 Data Cache Power Reduction Using a Forwarding Predictor., PATMOS 2010: 116-125
P. Carazo, R. Apolloni, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado, L1 Data Cache Power Reduction Using a Forwarding Predictor., PATMOS 2010: 116-125
Pablo Cortés, José M. García, Jesús Muñuzuri, José Guadix, A viral system massive infection algorithm to solve the Steiner tree problem in graphs with medium terminal density., IJBIC 2(2): 71-77 (2010)
Paola Caymes-Scutari, Anna Morajko, Tomàs Margalef, Emilio Luque, Scalable dynamic Monitoring Analysis and Tuning Environment for parallel applications., J. Parallel Distrib. Comput. 70(4): 330-337 (2010)
Paolo Burgio, Martino Ruggiero, Francesco Esposito, Mauro Marinoni, Giorgio Buttazzo, Luca Benini, Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems, Computer Design (ICCD), 2010 IEEE International Conference on
Pascal Felber, Christof Fetzer, Patrick Marlier, Martin Nowack, Torvald Riegel, Brief Announcement: Hybrid Time-Based Transactional Memory., DISC 2010: 124-126
Pascal Felber, Martin Rajman, Etienne Riviere, Valerio Schiavoni, José Valerio, SPADS: Publisher Anonymization for DHT Storage., Peer-to-Peer Computing 2010: 1-10
Pascal Felber, Peter Kropf, Lorenzo Leonini, Toan Luu, Martin Rajman, Etienne Riviere, Collaborative Ranking and Profiling: Exploiting the Wisdom of Crowds in Tailored Web Search., DAIS 2010: 226-242
Pascal Felber, Ricardo Jiménez-Peris, Giovanni Schmid, Pierre Sens, Distributed Systems and Algorithms., Euro-Par (1) 2010: 510
Patrick Amestoy, Daniela di Serafino, Rob H. Bisseling, Enrique S. Quintana-Ortí, Marián Vajtersic, Parallel Numerical Algorithms., Euro-Par (2) 2010: 63-64
Patrick Bellasi, Adnan Faisal, William Fornaciari, Giuseppe Serazzi, Queueing Network Models for Performance Evaluation of ZigBee-Based WSNs., EPEW 2010: 147-159
Patrick Bellasi, Stefano Bosisio, Matteo Carnevali, William Fornaciari, David Siorpaes, Constrained Power Management: Application to a multimedia mobile platform., DATE 2010: 989-992
Patrick Bellasi, William Fornaciari, David Siorpaes, A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems., ARCS 2010: 37-48
Paul Brelet, Arnaud Grasset, Philippe Bonnot, Frank Ieromnimon, Dimitrios Kritharidis, Nikolaos S. Voros, System Level Design for Embedded Reconfigurable Systems Using MORPHEUS Platform., ISVLSI 2010: 500-505
Paul Feautrier, Laure Gonnord, Accelerated Invariant Generation for C Programs with Aspic and C2fsm., Electr. Notes Theor. Comput. Sci. 267(2): 3-13 (2010)
Paul Kaufmann, Tobias Knieper, Marco Platzner, A novel hybrid evolutionary strategy and its periodization with multi-objective genetic optimizers., IEEE Congress on Evolutionary Computation 2010: 1-8
Paul Lokuciejewski, Timon Kelter, Peter Marwedel, Superblock-Based Source Code Optimizations for WCET Reduction., CIT 2010: 1918-1925
Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé, Starsscheck: A Tool to Find Errors in Task-Based Parallel Programs., Euro-Par (1) 2010: 2-13
Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé, Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors., HiPEAC 2010: 96-110
Paul Timothy Furgale, Timothy D. Barfoot, Nadeem Ghafoor, Kevin Williams, Gordon Osinski, Field Testing of an Integrated Surface/Subsurface Modeling Technique for Planetary Exploration., I. J. Robotic Res. 29(12): 1529-1549 (2010)
Paula Cecilia Fritzsche, José-Jesús Fernández, Dolores Rexachs, Inmaculada García, Emilio Luque, Analytical Performance Prediction for Iterative Reconstruction Techniques in Electron Tomography of Biological Structures., IJHPCA 24(4): 457-468 (2010)
Paulo Alexandre Crisóstomo Lopes, José Germano, Teresa Mendes de Almeida, Leonel Augusto Sousa, Moisés Simões Piedade, F. A. Cardoso, H. A. Ferreira, P. P. Freitas, Measuring and Extraction of Biological Information on New Handheld Biochip-Based Microsystem., IEEE T. Instrumentation and Measurement 59(1): 56-62 (2010)
Pavlos Petoumenos, Georgia Psychou, Stefanos Kaxiras, Juan Manuel Cebrian Gonzalez, Juan L. Aragón, MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance., ARCS 2010: 113-125
Pedro C. Diniz, Marco Danelutto, Denis Barthou, Marc Gonzales, Michael Hübner, High Performance Architectures and Compilers., Euro-Par (1) 2010: 254-255
Pedro Miguel Matutino, Ricardo Chaves, Leonel Sousa, Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations., DSD 2010: 243-246
Pedro Morillo, Silvia Rueda, Juan Manuel Orduña, José Duato, Ensuring the performance and scalability of peer-to-peer distributed virtual environments., Future Generation Comp. Syst. 26(7): 905-915 (2010)
Pedro Tomás, Leonel Sousa, A quantitative analysis of firing rate estimators: Unveiling bias sources., Neurocomputing 73(16-18): 2944-2954 (2010)
Pedro Tomás, Aleksandar Ilic, Leonel Sousa, Biomedical Diagnostics and Clinical Technologies: Applying High-Performance Cluster and Grid Computing, chapter Massive Data Classification of Neural Responses, IGI Global
Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi, EDXY - A low cost congestion-aware routing algorithm for network-on-chips., Journal of Systems Architecture - Embedded Systems Design 56(7): 256-264 (2010)
Pejman Lotfi-Kamran, Michael Ferdman, Daniel Crisan, Babak Falsafi, TurboTag: lookup filtering to reduce coherence directory power., ISLPED 2010: 377-382
Pekka O. Jaskelainen, Carlos S. de La Lama, Pablo Huerta, Jarmo Takala, OpenCL-based design methodology for application-specific processors., ICSAMOS 2010: 223-230
Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero, Thread to strand binding of parallel network applications in massive multi-threaded systems., PPOPP 2010: 191-202
Pete Cooper, Uwe Dolinsky, Alastair F. Donaldson, Andrew Richards, Colin Riley, George Russell, Offload - Automating Code Migration to Heterogeneous Multicore Systems., HiPEAC 2010: 337-352
Peter Collingbourne, Paul H. J. Kelly, Inference of Session Types From Control Flow., Electr. Notes Theor. Comput. Sci. 238(6): 15-40 (2010)
Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen, Benchmarking and evaluating reconfigurable architectures targeting the mobile domain., ACM Trans. Design Autom. Electr. Syst. 15(2): (2010)
Peter Thoman, Hans Moritsch, Thomas Fahringer, Topology-Aware OpenMP Process Scheduling., IWOMP 2010: 96-108
Peter van Stralen, Andy D. Pimentel, A trace-based scenario database for high-level simulation of multimedia MP-SoCs., ICSAMOS 2010: 11-19
Peter van Stralen, Andy D. Pimentel, A High-level Microprocessor Power Modeling Technique Based on Event Signatures., Signal Processing Systems 60(2): 239-250 (2010)
Peter Y. K. Cheung, Process Variability and Degradation: New Frontier for Reconfigurable., ARC 2010: 2
Peter Y. K. Cheung, John Wawrzynek, Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays FPGA 2010 Monterey California USA February 21-23 2010, ACM 2010
Philip Brisk, Ajay K. Verma, Paolo Ienne, An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form., IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1096-1109 (2010)
Pierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas, Giovanna Monni, Re-NUCA: Boosting CMP Performance Through Block Replication., DSD 2010: 199-206
Piero Zappi, Clemens Lombriser, Luca Benini, Gerhard Tröster, Collecting Datasets from Ambient Intelligence Environments., IJACI 2(2): 42-56 (2010)
Pierre Michaud, Yiannakis Sazeides, André Seznec, Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses., Conf. Computing Frontiers 2010: 237-246
Pjotr Kourzanov, Orlando Moreira, Henk J. Sips, Disciplined Multi-core Programming in C., PDPTA 2010: 346-354
Polychronis Xekalakis, Marcelo Cintra, Handling branches in TLS systems with Multi-Path Execution., HPCA 2010: 1-12
Polychronis Xekalakis, Nikolas Ioannou, Salman Khan, Marcelo Cintra, Profitability-based power allocation for speculative multithreaded systems., IPDPS 2010: 1-11
Pratyush Kumar, David Atienza, Neural network based on-chip thermal simulator., ISCAS 2010: 1599-1602
Qiang Liu, Tim Todman, Wayne Luk, Combining optimizations in automated low power design., DATE 2010: 1791-1796
R. Concheiro, Margarita Amor, Montserrat Bóo, Synthesis of Bézier Surfaces on the GPU., GRAPP 2010: 110-115
R. Grottesi, S. Morigi, Martino Ruggiero, Luca Benini, Parallel subdivision surface rendering and animation on the Cell BE processor., DATE 2010: 178-183
R. Iris Bahar, Fabrizio Lombardi, David Atienza, Erik Brunvand, Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009 Providence Rhode Island USA May 16-18 2010, ACM 2010
Radu Stefan, Jason de Windt, Kees G. W. Goossens, On-chip network interfaces supporting automatic burst write creation posted writes and read prefetch., ICSAMOS 2010: 185-192
Rafael Tornero, Juan M. Orduña, Improving topological mapping on NoCs., IPDPS Workshops 2010: 1-4
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato, Exploiting subtrace-level parallelism in clustered processors., PACT 2010: 555-556
Rainer Leupers, Jerónimo Castrillón, MPSoC programming using the MAPS compiler., ASP-DAC 2010: 897-902
Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki, Cool MPSoC programming., DATE 2010: 1488-1493
Ralf Karrenberg, Dmitri Rubinstein, Philipp Slusallek, Sebastian Hack, AnySL: efficient and portable shading for ray tracing., High Performance Graphics 2010: 97-105
Rameez Rahman, David Hales, Tamas Vinko, Johan A. Pouwelse, Henk J. Sips, No more crash or crunch: Sustainable credit dynamics in a P2P community., HPCS 2010: 332-340
Ramon Bertran, Marc González, Xavier Martorell, Nacho Navarro, Eduard Ayguadé, Decomposable and responsive power models for multicore processors using performance counters., ICS 2010: 147-158
Ramon Bertran, Marc Gonzalez, Xavier Martorell, Nacho Navarro, Eduard Ayguade, Decomposable and responsive power models for multicore processors using performance counters. In ICS '10: Proceedings of the 24th ACM International Conference on Supercomputing., ACM
Ramon Bertran, Marc Gonzalez, Xavier Martorell, Nacho Navarro, Eduard Ayguade, Local Memory Design Space Exploration for High-Performance Computing. The Computer Journal., Oxford University Press
Ramon Bertran, Marc Gonzalez, Yolanda Becerra, David Carrera, Jordi Torres, Eduard Ayguade, Towards Accurate Accounting of Energy Consumption in Shared Virtualized Environments. Poster Session in First International Conference on Energy Efficient Computing and Networking (e-Energy 2010), Passau, Germany, April 2010., e-Energy 2010
Ramon Bertran, Yolanda Becerra, David Carrera, Vincenc Beltran, Marc Gonzalez, Xavier Martorell, Jordi Torres, Eduard Ayguade, Accurate Energy Accounting for Shared Virtualized Environments using PMC-based Power Modeling Techniques. In The 11th IEEE/ACM International Conference on Grid Computing (GRID-2010)., IEEE
Raphaël Couturier, Yi Pan, Enrique S. Quintana-Ortí, Thomas Rauber, Gudula Rünger, Laurence Tianruo Yang, Message from the PDSEC-10 workshop chairs., IPDPS Workshops 2010: 1-2
Raymond Manley, David Gregg, A Program Generator for Intel AES-NI Instructions., INDOCRYPT 2010: 311-327
Raymond Manley, Paul Magrath, David Gregg, Code generation for hardware accelerated AES., ASAP 2010: 345-348
Riadh Ben Abdallah, Tanguy Risset, Antoine Fraboulet, Jerome Martin, Virtual Machine for Software Defined Radio: Evaluating the Software VM Approach., CIT 2010: 1970-1977
Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato, Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level., IEEE Trans. Parallel Distrib. Syst. 21(8): 1117-1131 (2010)
Ricardo Quislant, Eladio Gutiérrez, Oscar G. Plata, Emilio L. Zapata, Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification., IDEAL 2010: 162-169
Rickard Holsmark, Shashi Kumar, Maurizio Palesi, A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms, 4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010)
Rikard Hultén, Christoph W. Kessler, Jörg Keller, Optimized On-Chip-Pipelined Mergesort on the Cell/B.E., Euro-Par (2) 2010: 187-198
Rizos Sakellariou, Salvatore Orlando, Josep-Lluis Larriba-Pey, Srinivasan Parthasarathy, Demetrios Zeinalipour-Yazti, Parallel and Distributed Data Management., Euro-Par (1) 2010: 316
Robert Pyka, Felipe Klein, Peter Marwedel, Stylianos Mamagkakis, Versatile system-level memory-aware platform description approach for embedded MPSoCs., LCTES 2010: 9-16
Roberto Airoldi, Omer Anjum, Fabio Garzia, Alexander M. Wyglinski, Jari Nurmi, Energy-Efficient Fast Fourier Transforms for Cognitive Radio Systems., IEEE Micro 30(6): 66-76 (2010)
Roberto Gioiosa, Towards sustainable exascale computing., VLSI-SoC 2010: 270-275
Roberto Giorgi, Stephan Wong, WRC'10: Proc. 2019 Workshop on Reconfigurable Computing, TU-Delft / EWI Computer Enginnering Laboratory, ISBN:978-90-72298-05-8, Delft, The Netherlands, Jan. 2010, pp. 1-116
Roberto Solar, Remo Suppi, Emilio Luque, High performance individual-oriented simulation using complex models., Procedia CS 1(1): 447-456 (2010)
Rodrígo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado, Stack filter: Reducing L1 data cache power consumption., Journal of Systems Architecture - Embedded Systems Design 56(12): 685-695 (2010)
Roger Ferrer, Vicenç Beltran, Marc González, Xavier Martorell, Eduard Ayguadé, Analysis of Task Offloading for Accelerators., HiPEAC 2010: 322-336
Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin, Li-Shiuan Peh, Design of a High-Throughput Distributed Shared-Buffer NoC Router., NOCS 2010: 69-78
Ronal Muresano, Dolores Rexachs, Emilio Luque, Learning parallel programming: a challenge for university students., Procedia CS 1(1): 875-883 (2010)
Ronal Muresano, Dolores Rexachs, Emilio Luque, Methodology for Efficient Execution of SPMD Applications on Multicore Environments., CCGRID 2010: 185-195
Rosilde Corvino, Abdoulaye Gamatié, Pierre Boulet, Architecture Exploration for Efficient Data Transfer and Storage in Data-Parallel Applications., Euro-Par (1) 2010: 101-116
Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar, Asynchronous Current Mode Serial Communication., IEEE Trans. VLSI Syst. 18(7): 1107-1117 (2010)
Rui Ramalho, Pedro Tomás, Leonel Sousa, Efficient Independent Component Analysis on a GPU., CIT 2010: 1128-1133
S. Arash Ostadzadeh, Roel Meeuws, Carlo Galuzzi, Koen Bertels, QUAD - A Memory Access Pattern Analyser., ARC 2010: 269-281
S. Lopez, R. Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung, Exploration of hardware sharing for image encoders., DATE 2010: 1737-1742
S. Reyes, Camelia Muñoz-Caro, Alfonso Niño, Raúl Sirvent, Rosa M. Badia, Monitoring and steering Grid applications with GRID superscalar., Future Generation Comp. Syst. 26(4): 645-653 (2010)
Saad Mubeen, Shashi Kumar, Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms., Euro-Micro DSD 2010: 181-188, IEEE Computer Society
Sacha Loitz, Markus Wedler, Dominik Stoffel, Christian Brehm, Norbert Wehn, Wolfgang Kunz, Complete Verification of Weakly Programmable IPs against Their Operational ISA Model., FDL 2010: 29-36
Samarjit Chakraborty, S. Ramesh, Jürgen Teich, Model-based analysis synthesis and testing of automotive hardware/software architectures., EMSOFT 2010: 299-300
Samer Arandi, Paraskevas Evripidou, Programming multi-core architectures using Data-Flow techniques., ICSAMOS 2010: 152-161
Samira Manabi Khan, Daniel A. Jiménez, Doug Burger, Babak Falsafi, Using dead blocks as a virtual victim cache., PACT 2010: 489-500
Samuel Antao, Jean-Claude Bajard, Leonel Sousa, Elliptic Curve point multiplication on GPUs., ASAP 2010: 192-199
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, J. Camacho, Federico Silla, José Duato, Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing., NOCS 2010: 25-32
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser, Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis., DSD 2010: 706-713
Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Bit line coupling memory tests for single-cell fails in SRAMs., VTS 2010: 27-32
Sandro Carrara, Andrea Cavallini, Yusuf Leblebici, Giovanni De Micheli, Vijayender Bhalla, Francesco Valle, Bruno Samorì, Luca Benini, Bruno Riccò, Inger Vikholm-Lundin, Tony Munter, Capacitance DNA bio-chips improved by new probe immobilization strategies., Microelectronics Journal 41(11): 711-717 (2010)
Sang Lyul Min, Robert G. Pettit IV, Peter P. Puschner, Theo Ungerer, Software Technologies for Embedded and Ubiquitous Systems - 8th IFIP WG 10.2 International Workshop SEUS 2010 Waidhofen/Ybbs Austria October 13-15 2010. Proceedings, Springer 2010
Sanna Määttä, Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Manfred Glesner, Jari Nurmi, Fernando Moraes, Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms., IJERTCS 1(1): 86-101 (2010)
Sascha Uhrig, The MANy JAva Core processor (MANJAC)., HPCS 2010: 188
Scott Pakin, Craig B. Stunkel, Jose Flich, Henrique Andrade, Vibhore Kumar, Deepak S. Turaga, Welcome to CAC/SSPS 2010., IPDPS Workshops 2010: 1
Scott Schneider, Henrique Andrade, Bugra Gedik, Kun-Lung Wu, Dimitrios S. Nikolopoulos, Evaluation of streaming aggregation on parallel hardware architectures., DEBS 2010: 248-257
Sean Rul, Hans Vandierendonck, Koen De Bosschere, A profile-based tool for finding pipeline parallelism in sequential programs., Parallel Computing 36(9): 531-551 (2010)
Sebastián López, 13th Euromicro Conference on Digital System Design Architectures Methods and Tools DSD 2010 1-3 September 2010 Lille France, IEEE 2010
Sebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero, Scalability Analysis of Progressive Alignment on a Multicore., CISIS 2010: 889-894
Sergio Saponara, Maurizio Martina, Michele Casula, Luca Fanucci, Guido Masera, Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding., Microprocessors and Microsystems - Embedded Hardware Design 34(7-8): 316-328 (2010)
Sergio Saponara, Pierangelo Terreni, Mixed-Signal Architectures for High-Efficiency and Low-Distortion Digital Audio Processing and Power Amplification., EURASIP J. Emb. Sys. 2010: (2010)
Sergio Saponara, Pierluigi Nuzzo, Paolo D'Abramo, Luca Fanucci, Design Methodologies and Innovative Architectures for Mixed-Signal Embedded Systems., EURASIP J. Emb. Sys. 2010: (2010)
Sergio Saponara, Tommaso Baldetti, Luca Fanucci, A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation., VLSI Design 2010: (2010)
Seyab, Said Hamdioui, NBTI modeling in the framework of temperature variation., DATE 2010: 283-286
Shivani Raghav, Martino Ruggiero, David Atienza, Christian Pinto, Andrea Marongiu, Luca Benini, Scalable instruction set simulator for thousand-core architectures running on GPGPUs., HPCS 2010: 459-466
Silvia Alayón, José L. Sánchez, José F. Sigut, Jorge Marrero, Manuel González, An Automated Approach for Preprocessing Retinographies., BIOSIGNALS 2010: 381-384
Silvia Bianchi, Pascal Felber, Maria Gradinariu Potop-Butucaru, Stabilizing Distributed R-Trees for Peer-to-Peer Content Routing., IEEE Trans. Parallel Distrib. Syst. 21(8): 1175-1187 (2010)
Simone Campanoni, Giovanni Agosta, Stefano Crespi Reghizzi, Andrea Di Biagio, A highly flexible, parallel virtual machine: design and experience of ILDJIT, Software Practice and Experience
Simone Pellegrini, Thomas Fahringer, Herbert Jordan, Hans Moritsch, Automatic tuning of MPI runtime parameter settings by using machine learning., Conf. Computing Frontiers 2010: 115-116
Slobodan Lukovic, Igor Kaitovic, Marcello Mura, Umberto Bondi, Virtual Power Plant As a Bridge between Distributed Energy Resources and Smart Grid., HICSS 2010: 1-8
Slobodan Lukovic, Nikolaos Christianos, Enhancing network-on-chip components to support security of processing elements., WESS 2010: 12
Slobodan Lukovic, Paolo Pezzino, Leandro Fiorin, Stack protection unit as a step towards securing MPSoCs., IPDPS Workshops 2010: 1-4
Slobodan Lukovic, Velimir Congradac, Filip Kulic, A System Level Model of Possible Integration of Building Management System in SmartGrid., COMPENG 2010: 58-60
Soledad Escolar Díaz, Florin Isaila, Alejandro Calderón Mateos, Luis Miguel Sánchez García, David E. Singh, SENFIS: a Sensor Node File System for increasing the scalability and reliability of Wireless Sensor Networks applications., The Journal of Supercomputing 51(1): 76-93 (2010)
Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Z. Pekmestzi, Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms., ICSAMOS 2010: 102-109
Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos, Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching., ISVLSI 2010: 104-109
Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos, High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures., ISVLSI 2010: 486-487
Srinivasan Murali, Luca Benini, Giovanni De Micheli, Design of networks on chips for 3D ICs., ASP-DAC 2010: 167-168
Stamatis G. Kavadias, Manolis Katevenis, Michail Zampetakis, Dimitrios S. Nikolopoulos, On-chip communication and synchronization mechanisms with cache-integrated network interfaces., Conf. Computing Frontiers 2010: 217-226
Stamatis Kavadias, Manolis Katevenis, Dionisios Pnevmatikatos, Chapter “Network Interface Design for Explicit Communication in Chip Multiprocessors,” in book Designing Network-on-Chip Architectures in the Nanoscale Era,, CRC press
Stamatis Kavadias, Manolis Katevenis, Michail Zampetakis, Dimitrios Nikolopoulos, On-chip communication and synchronization mechanisms with cache-integrated network interfaces, ACM, 7th ACM international Conference on Computing Frontiers (CF'2010)
Stefan Wildermann, Andreas Oetken, Jürgen Teich, Zoran A. Salcic, Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras., ATC 2010: 1-16
Stefano Marsi, Sergio Saponara, Integrated video motion estimator with Retinex-like pre-processing for robust motion analysis in automotive scenarios: algorithmic and real-time architecture design., J. Real-Time Image Processing 5(4): 275-289 (2010)
Stefanos Kaxiras, Georgios Keramidas, SARC Coherence: Scaling Directory Cache Coherence in Performance and Power., IEEE Micro 30(5): 54-65 (2010)
Stephan Wong, Fakhar Anjam, Faisal Nadeem, Dynamically reconfigurable register file for a softcore VLIW processor., DATE 2010: 969-972
Stephen Wray, Wayne Luk, Peter Pietzuch, Exploring algorithmic trading in reconfigurable hardware., ASAP 2010: 325-328
Stephen Wray, Wayne Luk, Peter Pietzuch, Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine., FPL 2010: 163-166
Steven M. Blackburn, Amer Diwan, Matthias Hauswirth, Atif M. Memon, Peter F. Sweeney, Workshop on experimental evaluation of software and systems in computer science (Evaluate 2010)., SPLASH/OOPSLA Companion 2010: 291-292
Stijn Eyerman, Lieven Eeckhout, A Counter Architecture for Online DVFS Profitability Estimation., IEEE Trans. Computers 59(11): 1576-1583 (2010)
Stijn Eyerman, Lieven Eeckhout, Per-Thread Cycle Accounting., IEEE Micro 30(1): 71-80 (2010)
Stijn Eyerman, Lieven Eeckhout, Modeling critical sections in Amdahl's law and its implications for multicore design., ISCA 2010: 362-370
Stijn Eyerman, Lieven Eeckhout, Probabilistic job symbiosis modeling for SMT processor scheduling., ASPLOS 2010: 91-102
Subayal Khan, Kari Tiensyrjä, Jari Nurmi, Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE Profile., DSD 2010: 251-254
Sven-Arne Reinemo, Tor Skeie, M. K. Wadekar, Ethernet for High-Performance Data centers: On the New IEEE Datacenter Bridging Standards., IEEE Micro 30(4): 42-51 (2010)
Sven-Arne Reinemo, Tor Skeie, Manoj K. Wadekar, Ethernet for High Performance Data Centers - on the New IEEE Data Center Bridging Standards, IEEE Micro 30(4):42-51, 2010. IEEE Computer Society.
Sylvain Girbal, Olivier Temam, Sami Yehia, Hugues Berry, Zheng Li, A memory interface for multi-purpose multi-stream accelerators., CASES 2010: 107-116
Taisuke Boku, Hiroshi Nakashima, Avi Mendelson, Proceedings of the 24th International Conference on Supercomputing 2010 Tsukuba Ibaraki Japan June 2-4 2010, ACM 2010
Taj Muhammad Khan, Daniel Gracia Pérez, Olivier Temam, Transparent sampling., ICSAMOS 2010: 28-36
Tal Ben-Nun, Yoav Etsion, Dror G. Feitelson, Design and implementation of a generic resource sharing virtual time dispatcher., SYSTOR 2010
Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Onur Mutlu, Mateo Valero, Efficient runahead threads., PACT 2010: 443-452
Tarek Nechma, Mark Zwolinski, Jeff S. Reeve, Parallel sparse matrix solver for direct circuit simulations on FPGAs., ISCAS 2010: 2358-2361
Tariq Abdullah, Koen Bertels, Luc Onana Alima, Zubair Nawaz, Effect of the Degree of Neighborhood on Resource Discovery in Ad Hoc Grids., ARCS 2010: 174-186
Taylan Yemliha, Mahmut T. Kandemir, Ozcan Ozturk, Emre Kultursay, Sai Prashanth Muralidhara, Code Scheduling for Optimizing Parallelism and Data Locality., Euro-Par (1) 2010: 204-216
Teresa Mendes de Almeida, Moisés Simões Piedade, Leonel Augusto Sousa, J. Germano, Paulo Alexandre Crisóstomo Lopes, F. A. Cardoso, P. P. Freitas, On the Modeling of New Tunnel Junction Magnetoresistive Biosensors., IEEE T. Instrumentation and Measurement 59(1): 92-100 (2010)
Teresa Nachiondo Frinós, Jose Flich, José Duato, Buffer Management Strategies to Reduce HoL Blocking., IEEE Trans. Parallel Distrib. Syst. 21(6): 739-753 (2010)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Wave-pipelined intra-chip signaling for on-FPGA communications., Integration 43(2): 188-201 (2010)
Thanos Makatos, Yannis Klonatos, Manolis Marazakis, Michail D. Flouris, Angelos Bilas, Using transparent compression to improve SSD-based I/O caches., EuroSys 2010: 1-14
Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne, Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions., HiPEAC 2010: 126-140
Theo Ungerer, The Multi-Core Challenge (Die Herausforderung Mehrkernprozessoren)., it - Information Technology 52(3): 142-146 (2010)
Theo Ungerer, Francisco J. Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quiñones, Mike Gerdes, Marco Paolieri, Julian Wolf, Hugues Cassé, Sascha Uh, Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability., IEEE Micro 30(5): 66-75 (2010)
Thomas A. M. Bernard, Clemens Grelck, Chris R. Jesshope, On the Compilation of a Language for General Concurrent Target Architectures., Parallel Processing Letters 20(1): 51-69 (2010)
Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos, Making Address-Correlated Prefetching Practical., IEEE Micro 30(1): 50-59 (2010)
Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev, 3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices., ARC 2010: 194-206
Thomas van Noort, Alexey Rodriguez Yakushev, Stefan Holdermans, Johan Jeuring, Bastiaan Heeren, José Pedro Magalhães, A lightweight approach to datatype-generic rewriting., J. Funct. Program. 20(3-4): 375-413 (2010)
Thomas Wahl, Alastair F. Donaldson, Replication and Abstraction: Symmetry in Automated Formal Verification., Symmetry 2(2): 799-847 (2010)
Tiago Dias, Nuno Roma, Leonel Sousa, Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems., DASIP 2010: 242-249
Tiago Jose Barreiros Martins de Almeida, Nuno Filipe Valentim Roma, A Parallel Programming Framework for Multi-core DNA Sequence Alignment., CISIS 2010: 907-912
Tim Drijvers, Carlos A. Alba Pinto, Henk Corporaal, Bart Mesman, Gert-Jan van den Braak, Fast Huffman decoding by exploiting data level parallelism., ICSAMOS 2010: 86-92
Tim Harris, James R. Larus, Ravi Rajwar, Transactional Memory 2nd edition, Morgan & Claypool Publishers 2010
Tim Harris, Sasa Tomic, Adrián Cristal, Osman S. Unsal, Dynamic filtering: multi-purpose architecture support for language runtime systems., ASPLOS 2010: 39-52
Tim Kranich, Mladen Berekovic, NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems., DSD 2010: 53-59
Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides, Customizable Composition and Parameterization of Hardware Design Transformations., DSD 2010: 595-602
Timo Hämäläinen, Seppo Pohjolainen, Robust Regulation of Distributed Parameter Systems with Infinite-Dimensional Exosystems., SIAM J. Control and Optimization 48(8): 4846-4873 (2010)
Tobias Becker, Markus Koester, Wayne Luk, Automated placement of reconfigurable regions for relocatable modules., ISCAS 2010: 3341-3344
Tobias Beisel, Manuel Niekamp, Christian Plessl, Using shared library interposing for transparent application acceleration in systems with heterogeneous hardware accelerators., ASAP 2010: 65-72
Tobias J. K. Edler von Koch, Igor Böhm, Björn Franke, Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions., CGO 2010: 180-189
Tobias Knieper, Paul Kaufmann, Kyrre Glette, Marco Platzner, Jim Torresen, Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture., ICES 2010: 250-261
Tobias Lange, Naim Harb, Haisheng Liu, Smaïl Niar, Rabie Ben Atitallah, An Improved Automotive Multiple Target Tracking System Design., DSD 2010: 255-258
Tobias Ziermann, Jürgen Teich, Adaptive traffic scheduling techniques for mixed real-time and streaming applications on reconfigurable hardware., IPDPS Workshops 2010: 1-4
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney, The Effect of Omitted-Variable Bias on the Evaluation of Compiler Optimizations., IEEE Computer 43(9): 62-67 (2010)
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney, Evaluating the accuracy of Java profilers., PLDI 2010: 187-197
Toktam Taghavi, Andy D. Pimentel, Visualization of Multi-objective Design Space Exploration for Embedded Systems., DSD 2010: 11-20
Tom Schrijvers, Alan Mycroft, Strictness Meets Data Flow., SAS 2010: 439-454
Tom Vander Aa, Praveen Raghavan, Scott A. Mahlke, Bjorn De Sutter, Aviral Shrivastava, Frank Hannig, Compilation techniques for CGRAs: exploring all parallelization approaches., CODES+ISSS 2010: 185-186
Tommaso Cucinotta, Dario Faggioli, An Exception Based Approach to Timing Constraints Violations in Real-Time and Multimedia Applications., SIES 2010: 136-145
Tommaso Cucinotta, Fabio Checconi, Luca Abeni, Luigi Palopoli, Self-tuning schedulers for legacy real-time applications., EuroSys 2010: 55-68
Tommaso Cucinotta, Fabio Checconi, Zlatko Zlatev, Juri Papay, Mike J. Boniface, George Kousiouris, Dimosthenis Kyriazis, Theodora A. Varvarigou, Soeren Berger, Dominik Lamp, Alessandro Mazzetti, Thoma, Virtualised e-Learning with real-time guarantees on the IRMOS platform., SOCA 2010: 1-8
Tommaso Cucinotta, Luigi Palopoli, QoS Control for Pipelines of Tasks Using Multiple Resources., IEEE Trans. Computers 59(3): 416-430 (2010)
Tommaso Cucinotta, Luigi Palopoli, Luca Abeni, Dario Faggioli, Giuseppe Lipari, On the Integration of Application Level and Resource Level QoS Control for Real-time Applications., IEEE Trans. Industrial Informatics 5(4): 479-491 (2010)
Toomas P. Plaks, David Andrews, Ronald F. DeMara, Herman Lam, Jooheung Lee, Christian Plessl, Greg Stitt, Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms ERSA 2010 July 12-15 2010 Las Vegas Nevada USA, CSREA Press 2010
Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Analytical and Simulation-based Design Space Exploration of Software Defined Radios., International Journal of Parallel Programming 38(3-4): 303-321 (2010)
Tron A. Darvann, Nuno V. Hermann, Per Larsen, Hildur Ólafsdóttir, Izabella V. Hansen, Hanne D. Hove, Leif Christensen, Daniel Rueckert, Sven Kreiborg, Automated quantification and analysis of mandibular asymmetry., ISBI 2010: 416-419
Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors, Design space exploration for an embedded processor with flexible datapath interconnect., ASAP 2010: 55-62
Uwe Brinkschulte, The Grand Challenges in Computer Engineering - Facing the Future (Die großen Herausforderungen der Technischen Informatik)., it - Information Technology 52(3): 131-134 (2010)
Uwe Schwiegelshohn, Rosa M. Badia, Marian Bubak, Marco Danelutto, Schahram Dustdar, Fabrizio Gagliardi, Alfred Geiger, Ladislav Hluchý, Dieter Kranzlmüller, Erwin Laure, Thierry Priol, Ale, Perspectives on grid computing., Future Generation Comp. Syst. 26(8): 1104-1115 (2010)
Valentin Dallmeier, Nikolai Knopp, Christoph Mallon, Sebastian Hack, Andreas Zeller, Generating test cases for specification mining., ISSTA 2010: 85-96
Valentin Kravtsov, Pavel Bar, David Carmeli, Assaf Schuster, Martin T. Swain, A scheduling framework for large-scale parallel and topology-aware applications., J. Parallel Distrib. Comput. 70(9): 983-992 (2010)
Valentina Salapura, Michael Gschwind, Jens Knoop, 19th International Conference on Parallel Architecture and Compilation Techniques (PACT 2010) Vienna Austria September 11-15 2010, ACM 2010
Veerle Desmet, Sylvain Girbal, Alex Ramírez, Olivier Temam, Augusto Vega, ArchExplorer for Automatic Design Space Exploration., IEEE Micro 30(5): 5-15 (2010)
Veerle Desmet, Sylvain Girbal, Olivier Temam, ArchExplorer.org: A methodology for facilitating a fair Comparison of research ideas., ISPASS 2010: 45-54
Victor Fernández, Francisco Grimaldo, Miguel Lozano, Juan M. Orduña, Evaluating Jason for Distributed Crowd Simulations., ICAART (2) 2010: 206-211
Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Power and thermal characterization of POWER6 system., PACT 2010: 7-18
Victor Jimenez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero, Trends and techniques for energy efficient architectures., VLSI-SoC 2010: 276-279
Vijay Janapa Reddi, Simone Campanoni, Meeta Sharma Gupta, Michael D. Smith, Gu-Yeon Wei, David Brooks, Kim M. Hazelwood, Eliminating voltage emergencies via software-guided code transformations., TACO 7(2): (2010)
Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks, Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling., MICRO 2010: 77-88
Vincent Gramoli, Derin Harmanci, Pascal Felber, On the Input Acceptance of Transactional Memory., Parallel Processing Letters 20(1): 31-50 (2010)
Vincent Nollet, Diederik Verkest, Henk Corporaal, A Safari Through the MPSoC Run-Time Management Jungle., Signal Processing Systems 60(2): 251-268 (2010)
Vincenzo Rana, Donatella Sciuto, A novel design framework for the design of reconfigurable systems based on NoCs., ACM Great Lakes Symposium on VLSI 2010: 1-2
Vladimir Marjanovic, Jesús Labarta, Eduard Ayguadé, Mateo Valero, Overlapping communication and computation by using a hybrid MPI/SMPSs approach., ICS 2010: 5-16
Vladimir Subotic, Jesús Labarta, Mateo Valero, Simulation environment for studying overlap of communication and computation., ISPASS 2010: 115-116
Volker Gierenz, Christian Panis, Jari Nurmi, Parameterized MAC unit generation for a scalable embedded DSP core., Microprocessors and Microsystems - Embedded Hardware Design 34(5): 138-150 (2010)
Waheed Iqbal, Matthew N. Dailey, David Carrera, SLA-Driven Dynamic Resource Management for Multi-tier Web Applications in a Cloud., CCGRID 2010: 832-837
Waheed Iqbal, Matthew N. Dailey, David Carrera, Paul Janecek, SLA-Driven Automatic Bottleneck Detection and Resolution for Read Intensive Multi-tier Applications Hosted on a Cloud., GPC 2010: 37-46
Walther Maldonado, Patrick Marlier, Pascal Felber, Adi Suissa, Danny Hendler, Alexandra Fedorova, Julia L. Lawall, Gilles Muller, Scheduling support for transactional memory contention management., PPOPP 2010: 79-90
Wei Lin Guay, Sven-Arne Reinemo, Olav Lysne, Tor Skeie, Bjørn Dag Johnsen, Line Holen, Host Side Dynamic Reconfiguration with InfiniBand, In: , ed. by Xiaohui Gu and Xiaosong Ma, pp. 126-135, IEEE Computer Society (ISBN: 978-0-7695-4220-1), 2010., 2010 IEEE International Conference on Cluster Computing, pp. 126-135, IEEE Computer Society, 2010.
Wenmiao Lu, Yi Lu, Message passing for in-vivo field map estimation in MRI., ISBI 2010: 740-743
Wilhelm Schäfer, Mauro Birattari, Johannes Blömer, Marco Dorigo, Gregor Engels, Rehan O'Grady, Marco Platzner, Franz-Josef Rammig, Wolfgang Reif, Ansgar Trächtler, Engineering self-coordinating software intensive systems., FoSER 2010: 321-324
Wim Heirman, Dirk Stroobandt, Narasinga Rao Miniskar, Roel Wuyts, Francky Catthoor, PinComm: Characterizing Intra-application Communication for the Many-Core Era., ICPADS 2010: 500-507
Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Imanol Martinez, Mikel Azkarate-askasua, Marco D. Santambrogio, A Roadmap for Autonomous Fault-Tolerant Systems., DASIP 2010: 311-321
Xiaochun Ye, Dongrui Fan, Wei Lin, Nan Yuan, Paolo Ienne, High performance comparison-based sorting algorithm on many-core GPUs., IPDPS 2010: 1-10
Xiaojun Yang, Christoforos Kachris, Manolis Katevenis, Efficient Implementation for CIOQ Switches with Sequential Iterative Matching Algorithms, IEEE International Conference on Field-Programmable Technology (FPT 2010)
Xiaoyuan Yang, Fernando Cores, Porfidio Hernández, Ana Ripoll, Emilio Luque, Designing an effective P2P system for a VoD system to exploit the multicast communication., J. Parallel Distrib. Comput. 70(12): 1175-1192 (2010)
Xin Jin, Mikel Luján, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Steve Furber, Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker., Conf. Computing Frontiers 2010: 89-90
Xin Jin, Mikel Luján, Muhammad Mukaram Khan, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Stephen B. Furber, Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware., ISPDC 2010: 9-16
Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell, High Performance Embedded Architectures and Compilers 5th International Conference HiPEAC 2010 Pisa Italy January 25-27 2010. Proceedings, Springer 2010
Yang Chen, Yuanjie Huang, Lieven Eeckhout, Grigori Fursin, Liang Peng, Olivier Temam, Chengyong Wu, Evaluating iterative optimization across 1000 datasets., PLDI 2010: 448-459
Yang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal, Automated bottleneck-driven design-space exploration of media processing systems., DATE 2010: 1041-1046
Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Riviere, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, , The Velox Transactional Memory Stack., IEEE Micro 30(5): 76-87 (2010)
Yi Lu, Bharat K. Bhargava, Congestion Avoidance Routing Protocol for Ad-Hoc Networks., IJNGC 1(1): (2010)
Yi Lu, Gloria C. Regisford, Identify Disease Related Genes by Differentiating Pooled Microarray Expression Data., CAINE 2010: 132-137
Yi Lu, Yan Shi, Jianping Yu, Determination of singularities of some 4-DOF parallel manipulators by translational/rotational Jacobian matrices., Robotica 28(6): 811-819 (2010)
Yi Lu, Yvo Desmedt, Improved Distinguishing Attack on Rabbit., ISC 2010: 17-23
Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy de Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor, A framework for automatic parallelization static and dynamic memory optimization in MPSoC platforms., DAC 2010: 549-554
Yifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, Anteneh A. Abbo, Sebastian M. Londono, Henk Corporaal, Xetal-Pro: an ultra-low energy and high throughput SIMD processor., DAC 2010: 543-548
Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Task Superscalar: An Out-of-Order Task Pipeline., MICRO 2010: 89-100
Zheng Li, Olivier Certner, Jose Duato, Olivier Temam, Scalable hardware support for conditional parallelization., PACT 2010: 157-168
Zheng Wang, Michael F. P. O'Boyle, Partitioning streaming parallelism for multi-cores: a machine learning based approach., PACT 2010: 307-318
Zsolt Németh, Thomas Fahringer, Péter Kacsuk, Special Section: DAPSYS workshop on distributed and parallel systems., Future Generation Comp. Syst. 26(3): 471-472 (2010)
Zubair Nawaz, Koen Bertels, Huseyin Ekin Sumbul, Fast Smith-Waterman hardware implementation., IPDPS Workshops 2010: 1-4

2011

Adrien Friggeri, Guillaume Chelius, Eric Fleury, Antoine Fraboulet, F. Mentré, J. C. Lucet, Reconstructing social interactions using an unreliable wireless sensor network., Computer Communications 34(5): 609-618 (2011)
Akash Kumar, Shakith Fernando, Manmohan Manoharan, Bringing Soccer to the Field of Real-Time Embedded Systems Education , Workshop on Embedded Systems Education - 2011
Alastair F. Donaldson, Daniel Kroening, Philipp Rümmer, SCRATCH: a tool for automatic analysis of dma races., PPOPP 2011: 311-312
Alastair F. Donaldson, Leopold Haller, Daniel Kroening, Strengthening Induction-Based Race Checking with Lightweight Static Analysis., VMCAI 2011: 169-183
Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, Jose Manuel Mendias, Román Hermida, A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis., IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 350-363 (2011)
Alejandra Segura, Christian Vidal-Castro, Víctor Menéndez-Domínguez, Pedro G. Campos, Manuel Prieto, Using data mining techniques for exploring learning object repositories., The Electronic Library 29(2): 162-180 (2011)
Aleksandar Dragojevic, Pascal Felber, Vincent Gramoli, Rachid Guerraoui, Why STM can be more than a research toy., Commun. ACM 54(4): 70-77 (2011)
Alessandro G. Di Nuovo, Missing data analysis with fuzzy C-Means: A study of its application in a psychological scenario., Expert Syst. Appl. 38(6): 6793-6797 (2011)
Alexander Sayenko, Olli Alanen, Henrik Martikainen, Vitaliy Tykhomyrov, Aleksandr Puchko, Vesa Hytönen, Timo Hämäläinen, WINSE: WiMAX NS-2 extension., Simulation 87(1-2): 24-44 (2011)
Alexander Shpiner, Isaac Keslassy, Modeling the interactions of congestion control and switch scheduling., Computer Networks 55(6): 1257-1275 (2011)
Amer Diwan, Matthias Hauswirth, Todd Mytkowicz, Peter F. Sweeney, TraceAnalyzer: a system for processing performance traces., Softw. Pract. Exper. 41(3): 267-282 (2011)
Amir Shahzad, Bryn Ll. Jones, Eric C. Kerrigan, George A. Constantinides, An efficient algorithm for the solution of a coupled Sylvester equation appearing in descriptor systems., Automatica 47(1): 244-248 (2011)
Andreas Hansson, Marcus Ekerhult, Anca Mariana Molnos, Aleksandar Milutinovic, Andrew Nelson, Jude Ambrose, Kees Goossens, Design and implementation of an operating system for composable processor sharing., Microprocessors and Microsystems - Embedded Hardware Design 35(2): 246-260 (2011)
Andreas Kern, Dominik Reinhard, Thilo Streichert, Jürgen Teich, Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice Versa., ARCS 2011: 259-270
Antonino Tumeo, Simone Secchi, Oreste Villa, Experiences with String Matching on the Fermi Architecture., ARCS 2011: 26-37
Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Efficient network management applied to source routed networks., Parallel Computing 37(3): 137-156 (2011)
Arash Ahmadi, Mark Zwolinski, Fixed-point multiplication: A probabilistic bit-pattern view., Microelectronics Reliability 51(4): 790-796 (2011)
Arnaldo Azevedo, Ben H. H. Juurlink, An Instruction to Accelerate Software Caches., ARCS 2011: 158-170
Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating., IEEE Trans. VLSI Syst. 19(1): 146-151 (2011)
Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits., IEEE Trans. VLSI Syst. 19(3): 469-482 (2011)
Cédric Hocquet, Dina Kamel, Francesco Regazzoni, Jean-Didier Legat, Denis Flandre, David Bol, François-Xavier Standaert, Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags., J. Cryptographic Engineering 1(1): 79-86 (2011)
C. Hernández, Antoni Roca, José Flich, Federico Silla, José Duato, Characterizing the impact of process variation on 45 nm NoC-based CMPs., J. Parallel Distrib. Comput. 71(5): 651-663 (2011)
Carlos Villavieja, Vasilis Karakostas, Lluis Vilanova, Yoav Etsion, Alex Ramirez, Avi Mendelson, Nacho Navarro, Adrian Cristal, Osman Unsal, DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB DirectoryrnCarlos Villavieja (UPC,BSC), Vasilis Karakostas (BSC), Lluis Vilanova (UPC,BSC), Yoav Etsion (BSC), Alex Ramirez (UPC, BSC), Avi Mendelson (Microsoft), Nacho Navarro (UPC, BSC) Adrian Cristal (BSC) and Osman Unsal, -
Carlos Villavieja, Yoav Etsion, Alex Ramirez, Nacho Navarro, FELI: HW/SW support for On-Chip Distributed Shared Memory in Multicores, Springer
Catalin Bogdan Ciobanu, Xavier Martorell, Georgi Kuzmanov, Alex Ramírez, Georgi Gaydadjiev, Scalability Evaluation of a Polymorphic Register File: A CG Case Study., ARCS 2011: 13-25
Chiraz Trabelsi, Rabie Ben Atitallah, Samy Meftali, Jean-Luc Dekeyser, Abderrazek Jemai, A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design., EURASIP J. Emb. Sys. 2011: (2011)
Christine Rochange, An Overview of Approaches Towards the Timing Analysability of Parallel Architecture., PPES 2011: 32-41
Christophe Le Lann, David Boland, George A. Constantinides, The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA., ARC 2011: 287-295
Crispín Gómez Requena, María Engracia Gómez, Pedro López, José Duato, How to reduce packet dropping in a bufferless NoC., Concurrency and Computation: Practice and Experience 23(1): 86-99 (2011)
David Kramer, Rainer Buchty, Wolfgang Karl, A Light-Weight Approach for Online State Classification of Self-organizing Parallel Systems., ARCS 2011: 183-194
Demetres Antoniades, Iasonas Polakis, Georgios Kontaxis, Elias Athanasopoulos, Sotiris Ioannidis, Evangelos P. Markatos, Thomas Karagiannis, we.b: the web of short urls., WWW 2011: 715-724
Diego Darriba, Guillermo L. Taboada, Ramon Doallo, David Posada, ProtTest 3: fast selection of best-fit models of protein evolution., Bioinformatics 27(8): 1164-1165 (2011)
Dimitris Gizopoulos, Mihalis Psarakis, Sarita Adve, P.Ramachandran, S.K.S.Hari, Dan.Sorin, Albert Meixner, Arijit Biswas, Xavier Vera, Architectures for Online Error Detection and Recovery in Multicore Processors, ACM/IEEE Design, Automation, and Test in Europe Conference (DATE), 2011
Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev, A Reconfigurable Audio Beamforming Multi-Core Processor., ARC 2011: 3-15
Dmitri Vainbrand, Ran Ginosar, Scalable network-on-chip architecture for configurable neural networks., Microprocessors and Microsystems - Embedded Hardware Design 35(2): 152-166 (2011)
Dominik Grewe, Michael F. P. O'Boyle, A Static Task Partitioning Approach for Heterogeneous Systems Using OpenCL., CC 2011: 286-305
Dorit Nuzman, Sergei Dyshel, Erven Rohou, Ira Rosen, Kevin Williams, David Yuste, Albert Cohen, Ayal Zaks, Vapor SIMD: Auto-Vectorize Once, Run Everywhere, ACM
Eleftheria Katsiri, Alan Mycroft, Linking temporal first-order logic with Bayesian networks for the simulation of pervasive computing systems., Simulation Modelling Practice and Theory 19(1): 161-180 (2011)
Ernst Gunnar Gran, Eitan Zahavi, Sven-Arne Reinemo, Tor Skeie, Gilad Shainer, Olav Lysne, On the Relation Between Congestion Control, Switch Arbitration and Fairness, 11th IEEE/ACM International Symposium on Cluster, Cloud, and Grid Computing (CCGrid 2011), 2011.
Ernst Gunnar Gran, Sven-Arne Reinemo, InfiniBand Congestion Control, Modelling and validation, 4th International ICST Conference on Simulation Tools and Techniques (SIMUTools2011, OMNeT++ 2011 Workshop), 2011.
Erven Rohou, Sergei Dyshel, Dorit Nuzman, Ira Rosen, Kevin Williams, Albert Cohen, Ayal Zaks, Speculatively Vectorized Bytecode, ACM
Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Mattan Erez, Static timing analysis for modeling QoS in networks-on-chip., J. Parallel Distrib. Comput. 71(5): 687-699 (2011)
Fabrizio Lamberti, Nikolaos Andrikos, Elisardo Antelo, Paolo Montuschi, Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers., IEEE Trans. Computers 60(2): 148-156 (2011)
Fahrettin Koc, Oguz Ergin, O. Seckin Simsek, Using content-aware bitcells to reduce static energy dissipation, Computer Design (ICCD), 2011 IEEE 29th International Conference on
Fatos Xhafa, Sabri Pllana, Leonard Barolli, Evjola Spaho, Grid and P2P middleware for wide-area parallel processing., Concurrency and Computation: Practice and Experience 23(5): 458-476 (2011)
Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini, An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platforms, Design, Automation & Test in Europe Conference & Exhibition, 2011 ,IEEE
Francis P. Russell, Michael R. Mellor, Paul H. J. Kelly, Olav Beckmann, DESOLA: An active linear algebra library using delayed evaluation and runtime code generation., Sci. Comput. Program. 76(4): 227-242 (2011)
Francisco J. Jaime, M. A. Sánchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata, High-Speed Algorithms and Architectures for Range Reduction Computation., IEEE Trans. VLSI Syst. 19(3): 512-516 (2011)
Francisco Triviño, José L. Sánchez, Francisco José Alfaro, José Flich, Virtualizing network-on-chip resources in chip-multiprocessors., Microprocessors and Microsystems - Embedded Hardware Design 35(2): 230-245 (2011)
Frank Olaf Sem-Jacobsen, Tor Skeie, Olav Lysne, José Duato, Dynamic Fault Tolerance in Fat Trees., IEEE Trans. Computers 60(4): 508-525 (2011)
George Theodorou, Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, A Software-Based Self-Test Methodology for On-Line Testing of Processor Caches, IEEE International Test Conference (ITC), 2011
Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis G.H. Katevenis, Víctor Viñals Yúfera, LP-NUCA: Networks-in-Cache for high-performance low-power embedded processors, IEEE Transactions on VLSI Systems
Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems., Appl. Soft Comput. 11(1): 382-398 (2011)
Grzegorz Danilewicz, Wojciech Kabacinski, Remigiusz Rajewski, The log_2{N-1} Optical Switching Fabrics., IEEE Transactions on Communications 59(1): 213-225 (2011)
Guillermo L. Taboada, Sabela Ramos, Juan Touriño, Ramon Doallo, Design of efficient Java message-passing collectives on multi-core clusters., The Journal of Supercomputing 55(2): 126-154 (2011)
Guy Sagy, Izchak Sharfman, Daniel Keren, Assaf Schuster, Top-k vectorial aggregation queries in a distributed environment., J. Parallel Distrib. Comput. 71(2): 302-315 (2011)
Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne, Reducing the pressure on routing resources of FPGAs with generic logic chains., FPGA 2011: 237-246
Hans Vandierendonck, Tom Mens, Averting the Next Software Crisis., IEEE Computer 44(4): 88-90 (2011)
Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini, Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip., IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 124-134 (2011)
J. Lobeiras, Margarita Amor, Ramon Doallo, FFT Implementation on a Streaming Architecture., PDP 2011: 119-126
Jack Dongarra, Peter H. Beckman, Terry Moore, Patrick Aerts, Giovanni Aloisio, Jean-Claude Andre, David Barkai, Jean-Yves Berthou, Taisuke Boku, Bertrand Braunschweig, Franck Cappello, Barbara M. Chap, The International Exascale Software Project roadmap., IJHPCA 25(1): 3-60 (2011)
Jan Vitek, Bjorn De Sutter, Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages compilers and tools for embedded systems LCTES 2011 Chicago IL USA April 11-14 2011, ACM 2011
Jaume Abella, Francisco Cazorla, Eduardo Quinones, Dimitris Gizopoulos, Arnaud Grasset, Sami Yehia, Philippe Bonnot, Riccardo Mariani, Guillem Bernat, Towards Improved Survivability in Safety-Critical Systems, IEEE International On-Line Testing Symposium (IOLTS), 2011
Javier D. Bruguera, Marius Cornea, Debjit Das Sarma, Guest Editors' Introduction: Special Section on Computer Arithmetic., IEEE Trans. Computers 60(2): 145-147 (2011)
Javier Fresno, Arturo González-Escribano, Diego R. Llanos Ferraris, Automatic Data Partitioning Applied to Multigrid PDE Solvers., PDP 2011: 239-246
Javier Navaridas, José Miguel-Alonso, Jose Antonio Pascual, Francisco Javier Ridruejo, Simulating and evaluating interconnection networks with INSEE., Simulation Modelling Practice and Theory 19(1): 494-515 (2011)
Jens Knoop, Compiler Construction - 20th International Conference CC 2011 Held as Part of the Joint European Conferences on Theory and Practice of Software ETAPS 2011 Saarbrücken Germany March 26-April 3 2011. Proceedings, Springer 2011
Jeroen Voeten, Oana Florescu, Jinfeng Huang, Henk Corporaal, Error computation for predictable real-time software synthesis., Simulation 87(4): 334-350 (2011)
Jonathan Rubin, Ian Watson, Computer poker: A review., Artif. Intell. 175(5-6): 958-987 (2011)
Jonghee M. Youn, Jongwon Lee, Yunheung Paek, Jongeun Lee, Hanno Scharwächter, Rainer Leupers, Fast graph-based instruction selection for multi-output instructions., Softw. Pract. Exper. 41(6): 717-736 (2011)
Jorge Ejarque, András Micsik, Raúl Sirvent, Peter Pallinger, László Kovács, Rosa M. Badia, Job Scheduling with License Reservation: A Semantic Approach., PDP 2011: 47-54
José Ignacio Aliaga, Matthias Bollhöfer, Alberto F. Martín, Enrique S. Quintana-Ortí, Exploiting thread-level parallelism in the iterative solution of sparse linear systems., Parallel Computing 37(3): 183-202 (2011)
José M. Badía, J. L. Movilla, J. I. Climente, Maribel Castillo, Mercedes Marqués, Rafael Mayo, Enrique S. Quintana-Ortí, J. Planelles, Large-scale linear system solver using secondary storage: Self-energy in hybrid nanostructures., Computer Physics Communications 182(2): 533-539 (2011)
José R. Herrero, Enrique S. Quintana-Ortí, Robert Strzodka, Special Issue: GPU computing., Concurrency and Computation: Practice and Experience 23(7): 667-668 (2011)
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung, Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only)., FPGA 2011: 284
Juan Carlos Saez, Daniel Shelepov, Alexandra Fedorova, Manuel Prieto, Leveraging workload diversity through OS scheduling to maximize performance on single-ISA heterogeneous multicore systems., J. Parallel Distrib. Comput. 71(1): 114-131 (2011)
Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan, An FPGA implementation of a sparse quadratic programming solver for constrained predictive control., FPGA 2011: 209-218
Juan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras, Leakage-efficient design of value predictors through state and non-state preserving techniques., The Journal of Supercomputing 55(1): 28-50 (2011)
Juan Miguel Campanario, Jesús Carretero, Vera Marangon, Antonio Molina, Germán Ros, Effect on the journal impact factor of the number and document type of citing records: a wide-scale study., Scientometrics 87(1): 75-84 (2011)
Katerina Doka, Dimitrios Tsoumakos, Nectarios Koziris, Online querying of d-dimensional hierarchies., J. Parallel Distrib. Comput. 71(3): 424-437 (2011)
Kevin Lee, Norman W. Paton, Rizos Sakellariou, Alvaro A. A. Fernandes, Utility functions for adaptively executing concurrent workflows., Concurrency and Computation: Practice and Experience 23(6): 646-666 (2011)
Kornilios Kourtis, Vasileios Karakasis, Georgios I. Goumas, Nectarios Koziris, CSX: an extended compression format for spmv on shared memory systems., PPOPP 2011: 247-256
Lei Gao, Theodore J. Mock, Rajendra P. Srivastava, An Evidential Reasoning Approach to Fraud Risk Assessment under Dempster-Shafer Theory: A General Framework., HICSS 2011: 1-10
Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan, Nicolas Vasilache, Loop transformations: convexity pruning and optimization., POPL 2011: 549-562
Luca Benini, Luca P. Carloni, Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2010., IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 492-493 (2011)
Luca Benini, Michele Lombardi, Michela Milano, Martino Ruggiero, Optimal resource allocation and scheduling for the CELL BE platform., Annals OR 184(1): 51-77 (2011)
M. B. Giles, Gihan R. Mudalige, Z. Sharif, Graham R. Markall, Paul H. J. Kelly, Performance analysis of the OP2 framework on many-core architectures., SIGMETRICS Performance Evaluation Review 38(4): 9-15 (2011)
M. Mustafa Rafique, Ali Raza Butt, Dimitrios S. Nikolopoulos, A capabilities-aware framework for using computational accelerators in data-intensive computing., J. Parallel Distrib. Comput. 71(2): 185-197 (2011)
Mahmood Ahmadi, Asadollah Shahbahrami, Stephan Wong, Collaboration of reconfigurable processors in grid computing: Theory and application., Future Generation Comp. Syst. 27(6): 850-859 (2011)
Manouk V. Manoukian, George A. Constantinides, Accurate Floating Point Arithmetic through Hardware Error-Free Transformations., ARC 2011: 94-101
Marco Aldinucci, Mario Coppo, Ferruccio Damiani, Maurizio Drocco, Massimo Torquati, Angelo Troina, On Designing Multicore-Aware Simulators for Biological Systems., PDP 2011: 318-325
Marco D. Santambrogio, Renato Stefanelli, A New Compact SD2 Positive Integer Triangular Array Division Circuit., IEEE Trans. VLSI Syst. 19(1): 42-51 (2011)
Marius Grannæs, Magnus Jahre, Lasse Natvig, Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy., ARCS 2011: 135-146
Mariusz Grad, Christian Plessl, Just-in-time Instruction Set Extension - Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture, Reconfigurable Architectures Workshop (RAW), Proceedings of the IPDPS, IEEE CS, Anchorage, Alaska, USA, May 2011
Martín Abadi, Andrew Birrell, Tim Harris, Michael Isard, Semantics of transactional memory and automatic mutual exclusion., ACM Trans. Program. Lang. Syst. 33(1): 2 (2011)
Martin Schindewolf, Alexander Esselson, Wolfgang Karl, Compiler-Assisted Selection of a Software Transactional Memory System., ARCS 2011: 147-157
Massimo Rovini, Giuseppe Gentile, Luca Fanucci, Fixed-Point MAP Decoding of Channel Codes., EURASIP J. Adv. Sig. Proc. 2011: (2011)
Matko Botincan, Mike Dodds, Alastair F. Donaldson, Matthew J. Parkinson, Automatic safety proofs for asynchronous memory operations., PPOPP 2011: 313-314
Matteo Pusceddu, Simone Ceccolini, Antonino Tumeo, Gianluca Palermo, Donatella Sciuto, Emulating Transactional Memory on FPGA Multiprocessors., ARCS 2011: 74-85
Mauricio Araya-Polo, Javier Cabezas, Mauricio Hanzich, Miquel Pericas, Felix Rubio, Isaac Gelado, Muhammad Shafiq, Enric Morancho, Nacho Navarro, Eduard Ayguade, Jose Mar?a Cela, Mateo Valero, Assessing Accelerator-Based HPC Reverse Time Migrationrn, IEEE TPDS
Maurizio Palesi , Giuseppe Ascia, Fabrizio Fazzino, Vincenzo Catania, Data Encoding Schemes in Networks on Chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Maurizio Palesi, Shashi Kumar, Radu Marculescu, Network-on-chip architectures and design methodologies., Microprocessors and Microsystems - Embedded Hardware Design 35(2): 83-84 (2011)
Miao Wang, François Bodin, Compiler-directed memory management for heterogeneous MPSoCs., Journal of Systems Architecture - Embedded Systems Design 57(1): 134-145 (2011)
Michal Sojka, Pavel Písa, Dario Faggioli, Tommaso Cucinotta, Fabio Checconi, Zdenek Hanzálek, Giuseppe Lipari, Modular software architecture for flexible reservation mechanisms on heterogeneous resources., Journal of Systems Architecture - Embedded Systems Design 57(4): 366-382 (2011)
Mladen Berekovic, William Fornaciari, Uwe Brinkschulte, Cristina Silvano, Architecture of Computing Systems - ARCS 2011 - 24th International Conference Como Italy February 24-25 2011. Proceedings, Springer 2011
Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini, ReliNoC: A Reliable Network for Priority-Based On-Chip Communication, ACM/IEEE
Muhammad Shafiq, Miquel Pericas, Eduard Ayguade, A Template System for the E?cient Compilation of Domain Abstractions onto Reconfigurable Computersrn, HiPEAC - WRC
Muhammad Shafiq, Miquel Pericas, Nacho Navarro , Eduard Ayguade, TARCAD : A Template Architecture for Reconfigurable Accelerator Designs, IEEE Symposium on Application Specific Processors (SASP)
Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero, From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype., ARC 2011: 350-362
Nikolaos Chrysos, Manolis Katevenis, Distributed WFQ scheduling converging to weighted max-min fairness., Computer Networks 55(3): 792-806 (2011)
Nikolas Kroupis, Dimitrios Soudris, FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer., Microprocessors and Microsystems - Embedded Hardware Design 35(3): 329-342 (2011)
Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio Gonzalez, Accelerating Microprocessor Silicon Validation by Exposing ISA Diversity, ACM/IEEE International Symposium on Microarchitecture (MICRO 2011), December, 2011.
Nor Zaidi Haron, Said Hamdioui, Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories., JETC 7(1): 4 (2011)
Onur Derin, Deniz Kabakci, Leandro Fiorin, Online Task Remapping Strategies for Fault-tolerant Network-on-Chip Multiprocessors Monitoring System for NoCs, IEEE/ACM
Oscar Almer, Nigel P. Topham, Björn Franke, A Learning-Based Approach to the Automated Design of MPSoC Networks., ARCS 2011: 243-258
Ozcan Ozturk, Data locality and parallelism optimization using a constraint-based approach., J. Parallel Distrib. Comput. 71(2): 280-287 (2011)
Pablo Ezzatti, Enrique S. Quintana-Ortí, Alfredo Remón, High Performance Matrix Inversion on a Multi-core Platform with Several GPUs., PDP 2011: 87-93
Pablo Garcia Del Valle, David Atienza, Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling., Microelectronics Journal 42(4): 564-571 (2011)
Paolo Bientinesi, Francisco D. Igual, Daniel Kressner, Matthias Petschow, Enrique S. Quintana-Ortí, Condensed forms for the symmetric eigenvalue problem on multi-threaded architectures., Concurrency and Computation: Practice and Experience 23(7): 694-707 (2011)
Paul Lokuciejewski, Peter Marwedel, Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems., Springer 2011: I-XVII 1-260
Pavel G. Zaykov, Georgi Kuzmanov, Architectural Support for Multithreading on Reconfigurable Hardware., ARC 2011: 363-374
Pedro Trancoso, Norbert Martínez-Bazan, Josep-Lluis Larriba-Pey, Memory- Bandwidth- and Power-Aware Multi-core for a Graph Database Workload., ARCS 2011: 171-182
Peter Collingbourne, Cristian Cadar, Paul H. J. Kelly, Symbolic crosschecking of floating-point and SIMD code., EuroSys 2011: 315-328
Philipp Lucas, Lothar Thiele, Benoit Triquet, Theo Ungerer, Reinhard Wilhelm, Bringing Theory to Practice: Predictability and Performance in Embedded Systems DATE Workshop PPES 2011 March 18 2011 Grenoble France., Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik Germany 2011
Pratyush Kumar, David Atienza, Run-time adaptable on-chip thermal triggers., ASP-DAC 2011: 255-260
Ramon Bertran, Yolanda Becerra, David Carrera, Vicenç Beltran, Marc Gonzàlez, Xavier Martorell, Nacho Navarro, Jordi Torres, Eduard Ayguadé, Energy accounting for shared virtualized environments under DVFS using PMC-based power models, Future Generation Computer Systems
Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert, Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration., ARCS 2011: 62-73
Roel Jordans, Firew Siyoum, Sander Stuijk, Akash Kumar, Henk Corporaal, An Automated Flow to Map Throughput Constrained Applications to a MPSoC, Dagstuhl publishing, Germany
Roel Jordans, Firew Siyoum, Sander Stuijk, Akash Kumar, Henk Corporaal, An Automated Flow to Map Throughput Constrained Applications to a MPSoC., PPES 2011: 47-58
Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin, Li-Shiuan Peh, Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers., IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 548-561 (2011)
Rosa Filgueira, David E. Singh, Jesús Carretero, Alejandro Calderón, Félix García, Adaptive-Compi: Enhancing Mpi-Based Applications' Performance and Scalability by using Adaptive Compression., IJHPCA 25(1): 93-114 (2011)
Sabina Serbu, Pascal Felber, Peter Kropf, HyPeer: Structured overlay with flexible-choice routing., Computer Networks 55(1): 300-313 (2011)
Samuel Bayliss, George A. Constantinides, Application Specific Memory Access Reuse and Reordering for SDRAM., ARC 2011: 41-52
Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesus Camacho, Federico Silla, José Duato, Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems., IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 534-547 (2011)
Sanida Omerovic, Zoran Babovic, Zhilbert Tafa, Veljko M. Milutinovic, Saso Tomazic, Concept modeling: From origins to multimedia., Multimedia Tools Appl. 51(3): 1175-1200 (2011)
Sebastian Schlingmann, Arne Garbade, Sebastian Weis, Theo Ungerer, Connectivity-Sensitive Algorithm for Task Placement on a Many-Core Considering Faulty Regions., PDP 2011: 417-422
Sergio Aldea, Diego R. Llanos Ferraris, Arturo González-Escribano, Towards a Compiler Framework for Thread-Level Speculation., PDP 2011: 267-271
Sergio Saponara, Esa Petri, Luca Fanucci, Pierangelo Terreni, Sensor Modeling Low-Complexity Fusion Algorithms and Mixed-Signal IC Prototyping for Gas Measures in Low-Emission Vehicles., IEEE T. Instrumentation and Measurement 60(2): 372-384 (2011)
Sergio Saponara, Gianluca Casarosa, Peter Hambloch, Francesco Ciuchi, Luca Fanucci, Bruno Sarti, Modeling Sensitivity Analysis and Prototyping of Low-g Acceleration Acquisition Systems for Spacecraft Testing and Environmental-Noise Measurements., IEEE T. Instrumentation and Measurement 60(2): 385-397 (2011)
Siegfried Benkner, Sabri Pllana, Jesper Larsson Träff, Philippas Tsigas, Uwe Dolinsky, Cèdric Augonnet, Beverly Bachmayer, Christoph Kessler, David Moloney, Vitaly Osipov, PEPPHER: Efficient and Productive Usage of Hybrid Computing Systems, IEEE Micro, vol. 31, no. 5, pp. 28-41, Sep./Oct. 2011, doi:10.1109/MM.2011.67
Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi, High Performance and Area Efficient Flexible DSP Datapath Synthesis., IEEE Trans. VLSI Syst. 19(3): 429-442 (2011)
Stefan Metzlaff, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer, A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware., ARCS 2011: 122-134
Stefano Montanelli, Devis Bianchini, Carola Aiello, Roberto Baldoni, Cristiana Bolchini, Silvia Bonomi, Silvana Castano, Tiziana Catarci, Valeria De Antonellis, Alfio Ferrara, Michele Melchiori, Elisa, The ESTEEM platform: enabling P2P semantic collaboration through emerging collective knowledge., J. Intell. Inf. Syst. 36(2): 167-195 (2011)
Svetislav Momcilovic, Leonel Sousa, Modeling and Evaluating Non-shared Memory CELL/BE Type Multi-core Architectures for Local Image and Video Processing., Signal Processing Systems 62(3): 301-318 (2011)
Tai-Hoon Kim, Omer F. Rana, Juan Touriño, Isaac Woungang, Special issue on "Theory and practice of high-performance computing communications and security"., The Journal of Supercomputing 55(2): 123-125 (2011)
Teemu Pitkänen, Jarmo Takala, Low-Power Application-Specific Processor for FFT Computations., Signal Processing Systems 63(1): 165-176 (2011)
Tero Arpinen, Timo D. Hämäläinen, Marko Hännikäinen, Meta-Model and UML Profile for Requirements Management of Software and Embedded Systems., EURASIP J. Emb. Sys. 2011: (2011)
Thomas J. Ashby, Pedro Diaz, Marcelo Cintra, Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters., IEEE Trans. Computers 60(4): 472-483 (2011)
Tobias Kenter, Christian Plessl, Marco Platzner, Michael Kauschke, Performance estimation framework for automated exploration of CPU-accelerator architectures., FPGA 2011: 177-180
Tomasz Szydzik, Gustavo M.Callico, Antonio Nunez, Efficient FPGA Implementation of a High-Quality Super-Resolution Algorithm with Real-Time Performance, IEEE Transaction on Consumer Electronics
Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks, Voltage Noise in Production Processors., IEEE Micro 31(1): 20-28 (2011)
Ville Kaseva, Timo D. Hämäläinen, Marko Hännikäinen, A Wireless Sensor Network for Hospital Security: From User Requirements to Pilot Deployment., EURASIP J. Wireless Comm. and Networking 2011: (2011)
Vladimir Subotic, José Carlos Sancho, Jesús Labarta, Mateo Valero, The Impact of Application's Micro-Imbalance on the Communication-Computation Overlap., PDP 2011: 191-198
Waheed Iqbal, Matthew N. Dailey, David Carrera, Paul Janecek, Adaptive resource provisioning for read intensive multi-tier applications in the cloud., Future Generation Comp. Syst. 27(6): 871-879 (2011)
Wei Lin Guay, Bartosz Bogdanski, Sven-Arne Reinemo, Olav Lysne, Tor Skeie, vFtree - A Fat-tree Routing Algorithm using Virtual Lanes to Alleviate Congestion, Proceedings of the 25th IEEE International Parallel & Distributed Processing Symposium, 2011.
Wei Lin Guay, Sven-Arne Reinemo, A Scalable Method for Signalling Dynamic Reconfiguration Events with OpenSM, 11th IEEE/ACM International Symposium on Cluster, Cloud, and Grid Computing (CCGrid 2011), 2011.
Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk, FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design., ARC 2011: 181-192
Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk, A comparison of FPGAs GPUS and CPUS for Smith-Waterman algorithm (abstract only)., FPGA 2011: 281
Yu Pu, Yifan He, Zhenyu Ye, Sebastian M. Londono, Anteneh A. Abbo, Richard P. Kleihorst, Henk Corporaal, From Xetal-II to Xetal-Pro: On the Road Toward an Ultralow-Energy and High-Throughput SIMD Processor., IEEE Trans. Circuits Syst. Video Techn. 21(4): 472-484 (2011)

2012

Martin Sandrieser, Siegfried Benkner, Sabri Pllana, Using explicit platform descriptions to support programming of heterogeneous many-core systems., Parallel Computing, Volume 38, Issues 1-2, January-February 2012, Pages 52-65, ISSN 0167-8191, 10.1016/j.parco.2011.10.008.