Report of research results

The convergence of the high-performance and embedded industry provides a unique opportunity for advancement since current high-performance multi-core processors (CMPs) will become tomorrow's embedded processors. Continuing advances in semiconductor technology will lead to more powerful cores in the future in order to support high performance demanding applications such as real-time media processing, high-speed networking, etc. Each core will be equipped with larger L1 private caches in order to tolerate the increasing distance to memory and the cache coherency problem must be addressed in this context. Additionally, increasing clock frequencies and deeper pipelines will result in higher energy consumption which will be a key issue in these designs.



The research interests of the University of Murcia (Prof. Garcia) are very related to the work that Prof. Kaxiras (Univ. of Patras) is currently carrying out. In this way, we are interested in applying for Seed Funding to establish a collaboration between our research group and the Patras� one.



1. Firstly, we will study energy-effective front-end and back-end designs in addition to low power I- and D-caches for future high-performance cores in the context of CMP architectures.



2. Secondly, we will develop coherence protocols adapted to the particularities of single-chip multiprocessor architectures that allow for high-performance, low power and fault tolerance features.

Budget:



Stefanos Kaxiras

- Stage: Murcia 3 days (450 Euros)

- Travel: 1 round trip Patras-Murcia (1550 Euros)



Juan L. Aragon

- Stage: Patras 3 days (450 Euros)

- Travel: 1 round trip Murcia-Patras (1550 Euros)

Juan Luis, ARAGON, jlaragon@ditec.um.es