Description:

The number of transistors available on a single chip continues to increase, although wires are not getting faster at same ratio. One possible solution to use all this transistors efficiently and hide wire delay as much as possible is clustering resources in some way. A proposal is creating tiled architectures or similar scalable on-chip solutions.

These issues are becoming very relevant into the embedded domain, because of the increased cost of deep sub-micron technologies, and push towards multi-purpose, flexible architectures. The desired solution would require tiled approaches for scalability and system retargetability aimed to different application domains where different performance metrics should be maximized.

Many proposals for tiled architectures have been explored recently like: Wavescalar, TRIPS, Raw, Smart Memories, Synchroscalar, CODE, SCALE. While this proposals present very interesting research ideas, there are several issues still not addressed, especially in the embedded domain.

In this research, we wish to explore a new paradigm that could allow to compose an architecture in a modular way, and in tiled fashion. We believe that such approach would allow for a smart usage of the available transistors while leaving open space to optimization of performance or low power or building specialized hardware accelerators.

We advocate that research efforts should further focus on striking the right balance between architecture, compiler and _user_ effort. Research in parallel/spatial programming paradigms has been addressing this issue and making significant progress which can now benefit micro-architectures in two ways: (1) by letting the user reasonably effortlessly pass information on program parallel properties to the architecture, thereby simplifying the task of the compiler and the architecture, and (2) by making the architecture "aware" of the running program and empowering it with the ability to dynamically allocate resources to the concurrently executing program parts, thereby better exploiting hardware resources, a task normally assigned to the compiler. We will illustrate the performance and scalability of this combined programming/architecture approach, called _Symbiotic Processing_, using SMTs and several appropriately written programs corresponding to a set of classic and non-trivial algorithms. Finally, we outline that, much like SIMD, this approach can be progressively adopted through hardware add-ons and C/C++ language extensions.

This cluster will therefore implement one major goal of HiPEAC network by integrating compiler and architecture research.

There will be two major research track with a common goal:

i) architectural track, aimed at defining the novel architecture based on a modular approach, while possibly keeping the same programming model and at the same time exposing the multi-microarchitecture as much as possible to the compiler;

ii) compiler track, aimed at exploring automatic parallelization technologies, thus allowing applications to easily run on the new architecture, and novel programming model to accommodate new applications or easy migration of known algorithm to fully exploit a scalable/modular architecture as defined in (i).

Nature:
Research cluster

Total funding:
Requested: € 32000
Granted: € 10000

Including fellowship funding:
Requested: € 15000
Granted: € 0

Description of how the funding will be used:

We re-worked the previous financial model (as requested by SC during last meeting in July 2005):

- we ask for 2500 EUROS per year and per institution (to reach annual 3 meetings and for 1 extra travel for direct contacts), interested instutions (NOT all): Edinburgh, INRIA, Patras, Pisa, Siena, STMicro.

This makes: 2500 x 6 = 15000 EURO.

 - we ask for co-support for a fellowship (15'000 including overhead) per 12 months for Zdravko Popovic (he is PhD student with no grant and already made some work: he was 3 months at UPC, and he prepared a survey on Tiled Architectures, available at http://www.dii.unisi.it/vispaper_brow.php ).

- we ask for some money for PhD students Zdravko Popovic or Daniele Mangano for a longer visit to Marcelo Cintra (Edinburgh) and Giuseppe Desoli atST Micro (we estimated 2000 EURO for 2 visits of 1 month).

Duration of the funding:
Requested: 12 month(s)
Granted: 12 month(s), starting on: Tue, January 1, 1980

Participating members:
BARTOLINI Sandro (University of Siena) (--member--)
FOGLIA Pierfrancesco (University of Pisa) (--member--)
GIORGI Roberto (University of Siena) (--member--)
KAXIRAS Stefanos (University of Patras) (--member--)
PRETE Antonio (University of Pisa) (--member--)
RAMIREZ Alex (UPC) (--member--)
TEMAM Olivier (INRIA) (--member--)
VALERO Mateo (UPC) (--member--)
CINTRA Marcelo (Edinburgh University) (--member--)
CORNERO Marco (STMicroelectronics) (--member--)

Other people collaborating:

Giuseppe Desoli (ST Microelectronics)
Daniele Mangano (PhD student, Pisa)
Zdravko Popovic (Postgraduate student, Siena)