The need for high performance computers has always been well established.

Since the early supercomputers, exploiting data level parallelism (DLP) has

been key to realizing the performance required by state-of-the-art

applications. Even today, the most performance demanding applications fall

into the data parallel range of applications: scientific codes, multimedia

applications, cryptographic codes, and life-science algorithms. They all

require extremely high performance, and all exhibit large amounts of data

level parallelism.



Vector architectures have been used in the past to exploit DLP, but they

prove ineffective for many application groups such as multimedia codes due

to the reduced vector lengths. A better solution to short vectors for DLP

is the use of SIMD instructions (Single Instruction Multiple Data) and wide

registers capable of holding 8 or more data elements, and perform the same

operation on all of them.



We foresee an interesting research opportunity in adding vector

capabilities to embedded processor, effectively adding classical or SIMD

(or a combination of both) vectors to the architecture. Also, adpating the

vector functionality to the target application and/or adjusting the number

and type of functional units is likely to provide significant performance

boosts without rquiring extensive changes to existing architectures.



The involved reseachers will meet to discuss their views on how to exploit

data level paralleism in high performance embedded architectures in roder

to detect common interests for further collaboration and complementary

efforts that lead to better research results.

The budget covers the travel and daily allowances for 2 meetings (1 in TU Delft and 1 in UPC) for all the participating researchers.

Esther Salam� (UPC), Francisco Cazorla (UPC)