1. Project Summary



RWTH Aachen University and Edinburgh University plan to establish a cooperation on HW/SW co-optimisation for embedded processor architectures. Within this project, the cooperation and mutual dependencies of high-level source code transformations, IR-level compiler optimisations, and applications specific processor ISAs (like

DSPs) will be investigated. At RWTH Aachen, focus will be on providing embedded processor models, compiler generation capabilities, and simulation platforms, based on the CoSy and LISATek tool suites.

Furthermore, Aachen will contribute source-level code transformations for optimising performance, code size, and energy consumption. At Edinburgh University, emphasis will be on adaptive high-level compiler optimisation based on machine-learning principles. The group at Edinburgh will provide their portable and currently SUIF-based source-level transformation tool for the automated adaptive performance and code size optimisation for embedded architectures such as DSPs and multimedia processors. In addition, Edinburgh will also contribute to the development of new and porting of existing SUIF-based code and data transformations using CoSy.



2. Goals



The goal of this collaboration is to integrate the results of both activities into a common software platform that will provide an advanced degree of automation in HW/SW co-optimisation. It will leverage the complementary areas of expertise from both partners, i.e.

processor architecture exploration, compiler generation, and code optimisation (Aachen) as well as advanced adaptive compiler optimisation (Edinburgh). The platform will be evaluated for different driver applications and architectures such as typical DSP and multimedia workloads from domain specific benchmark suites (e.g. UTDSP and MiBench) and high-performance embedded DSPs, respectively.



3. Collaboration



The collaboration between Aachen and Edinburgh will be established through a number of mutual visits of about two to four weeks duration after an initial meeting of the project leaders from both Universities. These fewer, but longer visits provide not only the opportunity to exchange and discuss ideas, but open up wider ranges of possibilities for an intensive and problem directed collaboration and work on detailed implementation issues.



4. Compiler Infrastructure



The compiler infrastructure development of this collaborative project will be based on the ACE CoSy compiler development system, which is already in use for several years at Aachen and has been recently introduced at Edinburgh. Both Universities, in particular Edinburgh, will evaluate and extend CoSy in the context of a future decision on a common European compiler platform.

Mutual visits for project set-up before year 1: 1500 EUR

Mid-term meeting for project review after year 1: 1500 EUR

Mutual visits for project wrap-up, reporting, publications etc.

after year 2: 1500 EUR

2-4 weeks Ph.D. student exchange at Aachen: 2000 EUR

2-4 weeks Ph.D. student exchange at Edinburgh: 2000 EUR

Conference attendence for presenting project results: 2000 EUR

All HiPEAC partners interested in embedded processor

compiler platforms based on Cosy.