Automatic Parallelization for Embedded Parallel Architectures


430 / Accepted / Finalized / Evaluated

Automatic parallelization is the ability for a compiler to generate parallel code from a high level programming language, achieving both high efficiency and scalability of an underlying parallel architecture. When the source is written in a parallel language, the compiler's task is to choose the most appropriate partitioning, mapping and scheduling parameters. The most ambitious approaches consider the automatic parallelization of languages with strictly sequential semantics (historically, Fortran or C). This cluster proposes to revisit the effectiveness and promises of both automatic parallelization technique (both state-of-the-art and new techniques), as motivated by the rise of massively parallel on-chip embedded architectures.

The goals of the cluster are:

  1. Define 2 sets of benchmarks for manual and automatic parallelization in the context of high-performance embedded systems: the first one being parallel programs to be automatically mapped and tuned to parallel architectures; the second being sequential codes to be automatically parallelized.
  2. Define a reference platform. We plan to focus on scalable platforms that are applicable to embedded systems. The reference platform should support realistic parallelism in HW, in terms of ILP, DLP, TLP, and speculation.
  3. Choose programming models appropriate for embedded system design and amenable to parallel programming with automatic mapping and tuning and/or automatic paralllelization. The former may include e.g. OpenMP, taskgraph or more exotic models; the latter may include plain C or higher level language.
  4. Identify main techniques that can be realistically applied to address the automatic tuning and/or extraction of parallelism from these benchmarks. This should cover various types of parallelism: static threads, dynamic inspection and dispatch, hybrid, ILP, SIMD, TLP, MicroTLP, speculative (w/ or w/o HW support).
  5. Propose innovative automatic parallelization methods, with or without programming model support. This should seed subsequent project proposals.

Research cluster

Requested: € 16000
Granted: € 16000

Requested: € 0
Granted: € 0

Travel: we plan to have meetings every 3 months, possibly in conjunction
with other Hipeac events. We anticipate about a dozen participants in each meeting, most of whom will be funded by other means, leaving about 4 people to fund per meeting.

   4 people traveling x 4 meetings x 1000 euros/trip = 16,000 euros


Requested: 12 month(s)
Granted: 12 month(s), starting on: Tue, January 1, 1980

MENDELSON Bilha (IBM) (--member--)
COHEN Albert (INRIA) (--member--)
TEMAM Olivier (INRIA) (--member--)
BERNSTEIN David (IBM) (--member--)
O'BOYLE Michael (Edinburgh University) (--member--)
ZAKS Ayal (IBM) (--member--)
DURANTON Marc (NXP) (--member--)
MARTORELL Xavier (UPC) (--member--)

Zbigniew Chamski, Philips

Harm Munk, Philips

Sebastian Pop, Ecole des Mines

Georges Silber, Ecole des Mines

Eduard Ayguade, UPC

Marc Gonzalez, UPC