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Automatic Parallelization for Embedded Parallel Architectures430 / Accepted / Finalized / Evaluated Automatic parallelization is the ability for a compiler to generate parallel code from a high level programming language, achieving both high efficiency and scalability of an underlying parallel architecture. When the source is written in a parallel language, the compiler's task is to choose the most appropriate partitioning, mapping and scheduling parameters. The most ambitious approaches consider the automatic parallelization of languages with strictly sequential semantics (historically, Fortran or C). This cluster proposes to revisit the effectiveness and promises of both automatic parallelization technique (both state-of-the-art and new techniques), as motivated by the rise of massively parallel on-chip embedded architectures. The goals of the cluster are:
Research cluster Requested: € 16000 Granted: € 16000 Requested: € 0 Granted: € 0 Travel: we plan to have meetings every 3 months, possibly in conjunction 4 people traveling x 4 meetings x 1000 euros/trip = 16,000 euros Requested: 12 month(s) Granted: 12 month(s), starting on: Tue, January 1, 1980 MENDELSON Bilha (IBM) (--member--) COHEN Albert (INRIA) (--member--) TEMAM Olivier (INRIA) (--member--) BERNSTEIN David (IBM) (--member--) O'BOYLE Michael (Edinburgh University) (--member--) ZAKS Ayal (IBM) (--member--) DURANTON Marc (NXP) (--member--) MARTORELL Xavier (UPC) (--member--) Zbigniew Chamski, Philips Harm Munk, Philips Sebastian Pop, Ecole des Mines Georges Silber, Ecole des Mines Eduard Ayguade, UPC Marc Gonzalez, UPC
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