Architecture-aware compiler solutions for energy issues in embedded systems.


Embedded systems become more and more widespread, especially autonomous ones, and clearly tend to be ubiquitous. In such systems, low-power and low-energy usage get ever more crucial.
The various problems faced pertain to autonomy, power supply possibilities, thermal dissipation, or even energy cost.
They can be addressed from different viewpoints, either in hardware or software. Although hardware solutions have been explored for a very long time, energy considerations are relatively recent in software approaches, especially in compilation which historically focused more on size and speed.
That is precisely in this domain that we want to make contributions with this cluster.

This cluster indeed aims at bringing together researchers and practitioners both from academia and industry in order to address energy issues in embedded systems from a compilation point of view. The various partners have not cooperated so far on such topics, although they share a common interest on energy usage reduction. This cluster is thus intended to foster, initiate and nurture new cooperations in the spirit of the HiPEAC European Network of Excellence.

We want not only to study one specific energy optimization, but also to take a holistic, broader view to explore interactions and synergies between several (compiler) optimizations at the same time. We are above all convinced that compiler optimizations should be "hardware-aware", and that more information exchanges between hardware and compiler are mandatory to be able to perform the best energy optimizations. On a longer term, we consider worth exploring
"co-optimizations" in which both hardware and software (compiler) cooperate and do a part of the job.

We thus gathered people whose expertise and background we believe are the most appropriate and balanced to reach these goals.

Academic partners at Edinburgh Univ. and INRIA are mainly intended to provide expertise and advances in software, more precisely in compilation, each with their specific backgrounds and knowledge (Edinburgh Univ.: machine learning; INRIA: memory management).
The Intel & Technion partner is mainly intended to provide software- and, above all, hardware-related expertise.
The Thalès industrial partner is mainly intended to provide integration and system level expertise and requirements.

This cluster agenda can be sketched in four non-strictly sequential phases.

First, knowing their common interest and their specific domains of expertise, the partners will meet to better understand each others works, abilities and needs. This is a phase where possible cooperations and synergies are explored.
Second, the cluster partners will define a common, concrete and industrial target application or class of applications.
Then, the cluster partners will seek to define a common evaluation platform. This phase may imply prototyping.
Finally, the partners will define their main target optimizations and will work to design and/or improve them. This phase is the research production phase itself.

One of our goal is to be able to launch --- probably at or after the end of this cluster --- a deeper, more integrated and more ambitious common project between academia and industry, including this cluster partners, and possibly others.


Research cluster

Requested: € 14400

Requested: € 0

The requested funding is mostly seed, with some collaboration, since all partners have been working to some extend and in their own way on energy issues in the past and now wish to more closely work together and join their efforts.

To ensure the success of this cluster between partners who do not have a long cooperation history together, a number of interactions between shall be necessary.
Some will be made electronically, either by email, phone or netmeetings. This includes conference calls for short standard 2-hours meetings and possibly for longer, 1-day, "virtual conferences".

However actual physical meetings are required for more concrete and comprehensive research work, papers, technical exchanges and hands-on work (prototyping or platforming).

We are thus asking HiPEAC to fund 12 short visits:
- eight "point-to-point" single-person visit (3 days + travel each) at another participating members'
- four short visits for a 4-participants "general meeting" (3 days + travel for each person)

Estimated averaged expenses for one short visit: 1200 €
- accommodation: 3 hotel nights & food * 120 € = 360 €
- round-trip flight/travel & local transportation: 840 €

Total funding requested for whole duration of cluster:
12 visits * 1200 = 14400 €


Requested: 12 month(s)

MENDELSON Avi (Intel) (--member--)
O'BOYLE Michael (Edinburgh University) (--member--)
ZENDRA Olivier (INRIA) (--colleague--)

SEIGNOLE Vincent, Thalès, France