Extends:
Adaptable Computers for Embedded Applications

Description:

In our initial research, we have realized that a promising area for applying reconfigurability is the memory subsystem. There is some initial work regarding reconfigurability of the caches (ISCA-2000, Ranganathan et el.) and several solutions both static (victim caches, column associative caches, skewed associative, assist caches) and adaptive (split temporal/spatial, dual data, configurable line-size, associativity and block size). Different functions during the encoding and decoding of multimedia content impose highly deviating (and sometimes contradictory to each other) requirements on the memory sub-system. Fully customizable mechanisms could improve the utilization of the external memory bus. For example, the cache prefetch algorithm can be "reprogrammed" on the fly to anticipate on changing memory access patterns of different computational kernels.

In terms of controlling the power consumption in memory hierarchies, works from Kaxiras et. al and works from Flautner et al. have considered to power down cache lines that are not expected to be accessed. Since typically a large amount of cache blocks are "dead" in the sense that they will not be accessed until the block is eventually evicted from the cache, they have shown great potential.

Moreover, cache and memory compression techniques have shown promise to free up 30% of the memory resources. For example, compression has the potential to also free up memory bandwidth and utilizing cache and scratch-pad memory resources more effectively

We wish to further explore, for the selected multimedia benchmarks (and in particular streaming and a superset of EEMBC suite):

- Techniques that exploit the fact that the operand size varies across applications and within an application as noted in previous work.

- Further develop ongoing work on compression technique so as to improve resource utilization for memory and interconnects.

- New approaches to phase detection and prediction techniques to control Adaptivity nature (for example, considering also wire-delay problem).

- Methods and designs to further reduce the power consumption in the memory sub-system through Adaptive behaviour.

- Identify mechanisms to trigger Adaptivity behaviour to be implemented in the Memory Controller and in the Run-Time System.

- Identify appropriate coherence mechanisms to allow a transparent interconnection of external cores that could be seen as "external resources": in this way the Adaptivity could be extended to multicore systems.

Nature:
Research cluster

Total funding:
Requested: € 57300
Granted: € 30000

Including fellowship funding:
Requested: € 24000
Granted: € 20000

Description of how the funding will be used:

FINANCIAL PLANNING

As the number of partners in this cluster is increasing, besides asking funds for the general meetings that will take place periodically, we wish to take advantage of some individual visits to exchange expertise in particular areas like simulation platforms, power reduction techniques, memory hierarchy design and multimedia streaming applications.

We wish to allow some internship at ST Microelectronics for most promising students in order to interact with professional working on actual projects. We several students interested into this and we wish to allow at least to three of them to be supported with an estimated cost of 3000 EURO per student for at least 3 months.

Also, some of us will need to buy communications equipment (like Polycom or other conference call equipment) to stay in touch more frequently. Let's assume 900 EURO per institution to buy this. Interested institutions: Siena, Patras.

The suggested period for continuing our research is 18 months.

Nevertheless, we foresee several trips (both to reach general meetings venues or individual partners) as we are spread out all over Europe. We assume a budget of 2500 EURO per year and per institution to travel. As we have 6 institution in this cluster and a period of 18 months, this makes a total of 22500 EURO.

FELLOWSHIP

As we activated one fellowship last year that was financed only for 12 months (due to HiPEAC budget restriction), we wish to apply for an extension for the remaining period (which is 24 months) being the total 24000 EURO for University of Pisa.

Therefore the total budget we are asking for this cluster is: 9000+22500+1800=33300.

Considering the fellowship extension (24000 EURO for Pisa) makes: 33300+24000=57300.

Duration of the funding:
Requested: 18 month(s)
Granted: 12 month(s), starting on: Tue, January 1, 1980

Participating members:
STENSTROM Per (Chalmers University of Technology) (--member--)
PRETE Antonio (University of Pisa) (--member--)
KAXIRAS Stefanos (University of Patras) (--member--)
GIORGI Roberto (University of Siena) (--member--)
GAYDADJIEV Georgi (Delft University of Technology) (--member--)
FOGLIA Pierfrancesco (University of Pisa) (--member--)
CORNERO Marco (STMicroelectronics) (--member--)
BARTOLINI Sandro (University of Siena) (--member--)

Other people collaborating:

Charlotta Baath, PhD student, Chalmers University

Alessandro Bardine, PhD student, University of Pisa

Paolo Bennati, PhD student, University of Siena

Pepijn De Langen, Delft University

Giuseppe Desoli, ST Microelectronics

Sandra Irobi, PhD student, Delft University

Daniele Mangano, PhD student, University of Pisa

Nikola Puzovic, PhD student, University of Siena

Martin Thuresson, PhD student, Chalmers University