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Statistical Simulation of Multicomputer Systems and Analytical Performance ModelingStatistical simulation techniques for uniprocessor and multiprocessor systems Computer system design is a very time-consuming process and simulation is essential to take decisions and verify designs. Simulation occurs at many levels, from circuit to system, and at different degrees of detail as the design evolves. Engineers have extensively used execution-driven and trace-driven simulation in order to obtain a reliable and accurate prediction of the final design. Nowadays, the cost of simulations is very high. However, multithreaded architectures and chip multiprocessors are becoming more and more popular and, as a consequence, simulation time and cost will need to increase even more in the upcoming years. With the objective of reducing simulation time without loosing accuracy, some interesting proposals have appeared in the last years. First, we have Sampled simulation, which chooses in an intelligent way a small portion of the program trace to simulate [Sher]. Second, using a reduced set of the inputs of a benchmark can be an interesting simplification [Klein]. Finally, we find Statistical simulation, which characterizes the behavior of the program and architecture with some probability distributions and builds a synthetic trace that is simulated in a cycle accurate trace-driven simulator [Nuss], [Eeck]. Section: Analytical Performance Modeling and its Practical Uses Another option is to develop analytical models, as they are fast methods that give insight of what is happening inside the processor. However, these methods are not as used as desirable because normally, some optimistic assumptions must be made in order to simplify the model. As a consequence, their accuracy is still low. However, some interesting recent approaches have been done to model processor's performance [Kark] or caches' performance [Berg]. This last publication demonstrates that the memory system can be accurately modeled, offering many possibilities for the next years. One of these applications consists in using these memory models in the algorithm that is in charge of scheduling the jobs in a Chip Multiprocessor (CMP) or a multithreaded processor. Normally, the scheduler of a real machine has to choose from a pool of N different processes, a small portion of them (for example 2 or 4). An interesting approach would consist in choosing the processes in order to avoid memory collisions in the shared levels of caches. This idea can be combined with a dynamic partitioning of the cache, which reserves a part of a cache for a concrete process (is free of collisions). Another option consists in trying to maximize the joined IPC (Instruction per Cycle) that is obtained or some other performance target. In that case, the previously mentioned models from [Kark] might be useful. Section: Statistical Simulation of Multicomputer Systems In [Nuss2] the authors present a statistical simulation model of an SMP system. They use statistical models for uniprocessor machines and combine them using statistical memory and interconnection models. Even though the accuracy obtained is poor, their model successfully manages to predict performance trends such as scalability. We are interested in the development of a statistical simulator focusing from the beginning to the multicomputer approach. We are confident that better accuracy can be achieved if the simulation framework is designed explicitly for multiprocessor configurations. Further ideas for accuracy improvement such as the inclusion of the operating system in the initial profiling phase and work in coarser granularity levels will be evaluated. Our initial objective is to be able to predict the real execution time of applications on multicomputer configurations and the effect that certain changes of the hardware would have on that time. Further developments would be to adapt the multicomputer model to heterogeneous multicomputer. The cluster would have a kick-off meeting during the summer school, where common research topics would be discussed. The students from UPC (Miquel Moretó and Nikolas Galanis) would carry out the work during a combined or two separate 3-month visits to Ghent. An additional support meeting in Ghent and follow-up meetings in HiPEAC Cluster days would be used to continue shaping the work and defining future collaborations. Research cluster Requested: € 20400 Granted: € 20400 Requested: € 0 Granted: € 0
Requested: 12 month(s) Granted: 0 month(s), starting on: Sun, November 30, 1980 GALANIS Nikolas (UPC) (--phd student--) LLOSA Josep (UPC) (--member--) RAMIREZ Alex (UPC) (--member--) VALERO Mateo (UPC) (--member--) EECKHOUT Lieven (Ghent University) (--member--) DE BOSSCHERE Koen (Ghent University) (--member--) MORETO Miquel
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