WHY



Current processor design trends are leading to the integration of several

processors on a single chip because this approach offers several benefits

like reducing the communication costs between the processors and allowing

the replication of a processor desing across the chip.



Moreover, in order to exploit the thread level parallelism available in

conventional workloads, processor design also trends to the use of

simultaneous multithreading (SMT). SMT processors are able to exploit both

the instruction level parallelism and the thread level parallelism.



Both trends may interact (for instance, Power 5 processor) and we believe

that next generation processors will exhibit both trends and may be applied to embedded systems. Also, new paradigms may be integrated to this scenario like kilo-instruction processors. Finally, we should foresee the aplications that will run on these processors.



Consequently, Computer Architects should focuss on this

scenario, detect its bottlenecks and propose solutions.



WHAT



To evaluate the proposals on this scenario, the computer architects must use a set of simulation tools designed for On Chip Multiprocessors. Moreover, we want to develop a set a simulation tools really modular where the exchange of

components can be performed easily.



This effort should of course provide modules to the common simulation platform under development within HiPEAC.



HOW



The proposal is structured in four parts:

- Study of the available simulation tools: all the participants will study

the avaialble simulation tools

- Design the simulation tools and decide which parts of the simulation tools

can be reused from existing ones and which parts must be implemented from

scratch. This decision will be taken in a meeting in Barcelona.

- Simulator implementation: This part will be developed mainly in Chalmers

between one studident form upc and another one from Chalmers.

- Workload selection and setting up benchmarks on the simulator platform. Workloads should reflect server usage apart from traditional, predominantly desktop applications used in current research.



HISTORY AND COMPLEMENTARINESS



We believe that the synergy between the experience of Chalmers group on Multiprocessors and the experience of Barcelona group on uniprocessor

simulator will lead us to a successful set of simulation tools.

Per Stenstrom & Fredrik Warg

- Stage: BCN 5 days (160*5*2 = 1600 euros)

- Travel: round trip GOT-BCN (800*2 = 1600 euros)



Adrian Cristal:

- Stage: GOT 30 days (2000 euros)

- Stage: GOT 30 days (2000 euros)

- Travel: 2 round trips BCN-GOT (2*800 = 1600 euros)



Alex Ramirez:

- Stage: GOT 5 days (160*5 = 800 euros)

- Travel: round trip GOT-BCN (800 euros)



Enric Morancho:

- Stage: GOT 5 days (160*5 = 800 euros)

- Travel: round trip GOT-BCN (800 euros)



Josep Llosa:

- Stage: GOT 5 days (160*5 = 800 euros)

- Travel: round trip GOT-BCN (800 euros)

Adrian, Cristal, adrian@ac.upc.edu

Jose Maria, Llaberia, llaberia@ac.upc.edu (already a HIPEAC member but not yet registered in the intranet)

Fredrik, Warg, warg@ce.chalmers.se