Extends:
Scalable System Architectures

Description:

(0) Proposal/Revision History:

1. Dec. 2004: initial SSA cluster proposal, requesting travel funds for initial meetings, to get to know each other and plan collaborations; 11 participants; 10 KEuro approved for first one or two meetings.
2. June 2005: additional funding requested for summer/fall '05 meetings: 5 KEuro; approved.
3. Dec. 2005: this proposal - reporting on 2005, planning for 2006, requesting funds for 2006.

(1) General Area of the Cluster:

Embedded systems will increasingly consist of multiple, cooperating processors and specialized computing engines, at all scales: on-chip (CMP's), multiple-chip enclosures (e.g. cell phone), multiple-enclosure systems (e.g. across a car, an airplane, a hospital, etc).  It is a challenge to architect such "scalable" systems, i.e. systems that can efficiently scale to a large number of processors.  A key to the success of Scalable Systems are the interprocessor communication mechanisms supported and the interconnection networks used, both on-chip and across chips. These are the general topics of the cluster; see below for specific topics for 2006.

(2) Report of Activities in 2005:

Members of the cluster met in February (Brussels, with SC), May (Ghent Cl.Mtgs), July (Summer School), and October (Ghent Cl.Mtgs).  Besides exchanging views and research results and topics, these meetings produced the following concrete results:

• Influenced, helped shape, and contributed to the "SCALA" FET-ACA IP proposal, both in content and in name.
• Produced the ideas for the "RECOMEC" Call-5 STREP proposal (Embedded Systems, September 2005), proposing a specific prototype chip design to demonstrate and test the ideas that came out of the cluster discussions.  Unfortunately, RECOMEC was not approved for EC funding, but it helped us put in writing and give specific shape to our ideas --the benefit remains, regardless of the (temporary) loss....
• Gave birth to the specific plans for 2006, below.

(3) Plans and Topics for 2006:

A lot of the work will be carried out in SCALA, but HiPEAC will be essential (a) in communicating the results and (b) in getting HiPEAC members who are not funded by SCALA to work together with the other cluster members.  Topics of particular interest are:

1. Initiation and completion notification: Remote DMA and remote enqueue must be initiated very efficiently; an even harder problem is to deliver completion notifications, promptly but without the high overhead of interrupts.  Completion notification is particularly challenging in the presence of multi-path routing (out-of-order delivery).
2. Coherence misses handled in software:  Non-snooping coherence protocols are quite complex, and their hardware implementation is costly and inflexible, while their performance is limited mostly by network latencies.  By executing the coherence protocol in software (like TLB miss handlers) on some of the idle processors in a CMP, the drawbacks are addressed, while performance does not suffer much because network latencies remain the same.  It is particularly crucial to ensure the collaboration of U. Uppsala on this topic.
3. On-chip scalability: with the progress in CMP's (Intel, in its last academic forum, was discussing 100s of cores on-chip), interconnection and network interface issues are now very crucial on-chip as well.  All topics on this list refer to both off-chip and on-chip, but it is particularly crucial to ensure the collaboration of KTH on networks-on-chip and multi-core issues in general.
   
4. Reliability and reconfiguration of interconnection networks: Fault tolerance is of paramount importance, especially in large embedded systems, and has to be supported via reconfiguration at the network level.  It is particularly crucial to ensure the collaboration of Simula on this topic. 
   
5. Congestion management: it is a central, very hard problem in multi-processor communication, to be solved by the joint efforts of network switches and network endpoint interfaces. 
   
6. Security issues: besides reliability in the face of hardware failures, security in the presence of unreliable software is a major concern.  Network interface hardware plays a major role in filtering traffic and isolating misbehaving components.

Nature:
Research cluster

Total funding:
Requested: € 30000
Granted: € 30000

Including fellowship funding:
Requested: € 0
Granted: € 0

Description of how the funding will be used:

An average of 5 members  are estimated to participate in each of the 4 cluster meetings of 2006, plus 2 members that are not funded by SCALA are estimated to travel to 3 SCALA events in 2006, for a total of 26 trips.  At approximately 1100 Euro per trip, this yields an estimated yearly cost of 30 KEuro funds to be requested from HiPEAC.

Additional funding may be needed because of the quite large number of people interested.  If so, additional application will be made around mid-year.

Duration of the funding:
Requested: 12 month(s)
Granted: 12 month(s), starting on: Tue, January 1, 1980

Participating members:
LYSNE Olav (Simula Research Laboratory) (--member--)
BRORSSON Mats (Royal Institute of Technology) (--colleague--)
HAGERSTEN Erik (Uppsala University) (--colleague--)
JOHNSON Ian (XYRATEX) (--member--)
KATEVENIS Manolis (FORTH) (--member--)
DUATO Jose (University Politecnica de Valencia) (--member--)
GIL Marisa (UPC) (--member--)
GAYDADJIEV Georgi (Delft University of Technology) (--member--)
VASSILIADIS Stamatis (Delft University of Technology) (--member--)
MARTORELL Xavier (UPC) (--member--)
NAVARRO Nacho (UPC) (--member--)
BEIVIDE Ramon (University of Cantabria) (--member--)
BILAS Angelos (FORTH) (--member--)
PNEVMATIKATOS Dionisios (FORTH) (--member--)

Other people collaborating:

Giuseppe Desoli, of ST Microelectronics (Switzerland) will also participate. 

Furthermore, the Cluster will consider the following people and organizations for potential collaborations: Ulrich Bruning(U.Mannheim; VLSI design, NI's), Rafael Casado (U.Castilla-La Mancha; network reconfiguration), Tor Skeie (SIMULA), Ben Juurlink (TUDelft), V. Puente and J-A. Gregorio (U.Cantabria), Sven Karlsson (FORTH), several researchers from UPV, members of Dolphin Interconnect Solutions (Norway), and members of SUN Microsystems (Oslo).