Description:

The SSS group at RWTH Aachen has comprehensive experience and tooling in C compiler construction for application specific processors (ASIPs) and fast simulation technology for single and multi-processor systems. One of the most visible results is the LISATek platform for ASIP design that has been conceived at RWTH and is now commercially available from CoWare Inc (www.coware.com). Recently, SSS contributed a retargetable C compiler to the LISATek platform, which is already in industrial use by different semiconductor and system houses.



As a new member of HiPEAC, SSS would like to make contributions to the compiler and simulation platforms needed for the Network. For this purpose, SSS would like to intensify contacts to, and share experiences with, relevant HiPEAC groups, e.g. at INRIA, U Edinburgh, U Dortmund and TU Delft.



Ongoing research activities at SSS in this context include retargetable code optimization, ASIP architecture optimization, source-level code optimization, and compilation for MPSoC.

Nature:
Research cluster

Total funding:
Requested: € 3000
Granted: € 3000

Including fellowship funding:
Requested: € 0
Granted: € 0

Description of how the funding will be used:

The funding will be used for initial visits to the abovementioned HiPEAC groups, in order to set up new collaborations w.r.t. compiler and simulation platforms, as well as potential new research cluster formations.

Duration of the funding:
Requested: 6 month(s)
Granted: 6 month(s), starting on: Fri, November 30, 1979

Participating members:
BODIN François (INRIA) (--colleague--)
EISENBEIS Christine (INRIA) (--member--)
LEUPERS Rainer (RWTH Aachen) (--member--)
MARWEDEL Peter (University of Dortmund) (--member--)
O'BOYLE Michael (Edinburgh University) (--member--)
VASSILIADIS Stamatis (Delft University of Technology) (--member--)

Other people collaborating:

Further HiPEAC members active in compiler and simulation platforms.