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Research on High Performance Interconnection Networks for Embedded Applications (extra funding for meetings)Research on High Performance Interconnection Networks for Embedded Applications Title: Research on High Performance Interconnection Networks for Embedded Applications (extension) HiPEAC categories: interconnects Extends cluster: Research on High Performance Interconnection Networks for Embedded Applications Description: This cluster aims to extend the funding for the cluster "Research on High Performance Interconnection Networks for Embedded Applications". The cluster helped to establish good collaborations among the different participants. Indeed, members from UNICT, UPV, UV, Simula, and Jonkoping have started several joined projects related to on-chip networks. Collaboration is advancing at a good step with different fellowships that are being taken (cluster #965 at Jonkoping) or will be taken (clusters #963, #964). Additionaly, collaborations are being held between UNIBO/UNIFE and UPV also with a fellowship (cluster #966), and between FORTH and UPV with a fellowship being done at UPV (cluster #969). Although HiPEAC is funding this initiative with several fellowships, some of the participants in the cluster are new members to HiPEAC (UV, Jonkoping, UCLM) or have little funding support (UNIFE). Thus, this cluster aims to cover expenses for meeting purposes of those new participants. Meetings constitute an essential part of the cluster. They represent an irreplaceable way to promote the cooperation and the exchangement of ideas between the cluster participants. In the ongoing cluster we are experimenting the effectiveness of cluster meetings as they have opened new research links between the cluster participants. A proof of this is confirmed by the set of interesting research activities started by some of the cluster participants and born during the cluster meetings (see below new projects). Many of these ideas will constitute the research activities that this cluster intends to pursue. The presence of industrial partners is extremely important for the success of the cluster. The possibility to test and validate the proposed techniques on real systems increases the value of the research. For this reason an important industrial actor now appear in the "other people collaborating" section of this proposal. People from STMicroelectronics involved in the clusters are from the On Chip Communication Systems (OCCS) group which is currently focusing on physical layer and back-end aspects of Networks-on-Chip. The strong correlation between the specialty which characterizes the OCCS group and the topic of the projects collected in this cluster is promising for the good results of the cluster. In addition to the three projects identified in the previous cluster, in this cluster (together with the different cluster fellowship) we challenge four new projects (identified in previous meetings): ------------------------------------------------------------------------------ The yield of a manufactured SoC device decreases with the size and complexity of logic it contains. It is expected that the yield of "fully fault free" NoC chips incorporating larger than sixteen resources will be very small. Manufacturing defects at micro-level can manifest themselves in faulty behavior of some system component. Therefore, there is a need to develop methodologies and tools to efficiently use NoC systems in which some resources, routers, links or resource network interfaces (RNIs) have manufacturing defects rendering them functionally unusable. We assume the NoC testing process can identify which "components" of the chip are faulty and others which are non-faulty. It is expected that only a very small percentage of total components (less than 10%) will be faulty. This context opens up many new research questions. a) Identification of useable subnet: An interesting problem will be to find the "best" useable fault free subnet on the chip. Subnet using all the working "components" of the network may not be the best choice in many situations. In some situations it may be better to leave out some working components unused to get a good resulting topology or to get good traffic distribution or to get good performance for the application. It is also possible that the performance of useable subnet may not suffice for the required application. Characterization of available subnet(s) for computational performance and communication performance will be very useful for the user and will also be interesting research topic. b) Mapping applications to the NoC System with known static faults with a goal to meet application's performance requirements or to maximize application's performance will also be interesting. The original network topology is changed but amount of irregularity in the network is very limited. It is possible to select a subnet which is regular with the same topology as the original network. c) Routing: Development of efficient routing algorithms for NoC System with known static faults or for the selected subnet. APSRA and SR can easily handle (or can be adapted to handle) faulty NoCs subset. The first two research areas are new in NoC context. We will define concrete research problems in these areas and develop initial solutions. ------------------------------------------------------------------------------ Networks-on-Chip (NoCs) have been proposed as a promising solution to the complex on-chip communication problems derived from the increasing number of processor cores. The design of NoCs involves several key issues, such as the network topology, the routing algorithm and an efficient task mapping, among other factors. Several proposals have been focused on task mapping last years. In the same way, some of our previous research was focused on developing a communication-aware mapping technique for irregular networks. Taking into account the particular features of NoCs, the same methodology can be applied to develop a communication-aware task mapping technique for NoCs. The main goal of this project is the characterization of network-on-chip resources, as the first step to develop an efficient communication-aware task mapping technique for NoCs. The overall objective is to define a novel task mapping technique which requires less computation effort than the other techniques that are based on exploring the entire design space with the objective to optimize of both latency and power consumption. ------------------------------------------------------------------------------ Virtualization of computing resources is becoming increasingly important both for multi-core CPUs and high-end servers. In a virtualized system, the set of resources that constitute a virtual compute entity should be spatially separated from each other. Dividing the cores on a NoC, or the CPUs in a high end server into disjoint sets for each task is a trivial problem. Ensuring that they use disjoint parts of the NoC is, however, complex, and in existing methods the requirement of routing-containment of each virtual partition severely degrades the utilization of the system. Routing-containment in resource allocation is important for a series of reasons. Most importantly, each task should be guaranteed a fraction of the interconnect capacity regardless of the properties of concurrent tasks. Thus, if one task introduces severe congestion within the interconnection network, other tasks should not be affected. In previous works the notion of routing-containment is often only hinted at. Even so, many strategies, like those that allocate sub-meshes in meshes, will be routing-contained whenever the predominant Dimension Order routing algorithm (DOR) is used. Although In this project we aim to propose flexible, predictable, and effective virtualization strategies that will increase the utilization and reliability of multi-core systems that lend on recent advances in routing algorithms as well as QoS and task mapping methodologies. -------------------------------------------------------------------------------- Multistage network topologies are the only viable solution to interconnect large numbers of hardware blocks, e.g. processors and memory units. However, their performance suffers heavily under stressing traffic conditions that overload links capacity, thus causing the formation of congestion trees. In his Phd thesis at FORTH, Nikolaos Chrysos proposed a request-grant scheduling scheme that eliminates the performance degradatation caused by overloaded (congested) links. The main benefit of this scheme is that it operates effeciently for any number of parallel congestion trees, without requiring per-flow queues inside the network; however, a significant drawback of this scheme is that it penalizes traffic with a "cold-start" request-grant latency overhead. On the other hand, UPV has proposed an alternative congestion management scheme, RECN, that dynamically detects congested links, and allocates separate (per-flow) "set-aside" queues (SAQ) for the traffic segments that traverse these congested links. RECN does not impose any latency overheads, but the number of parallel congestion trees that it can handle is limited by the number of available SAQ's. This research proposal aims to combine the two aforementioned schemes. Request-grant scheduling is more effective when there are many parallel congestion trees in the network, while RECN has delay benefits when the network load is low, or when there are up to a few congestion trees present. FORTH, in collaboration with UPV and UCLM will investigate how to combine request-grant scheduling and RECN, in order to get what is best from each scheme. Our current plan is the following. RECN will be used for as long as traffic is light, until the formation of a congestion tree; in this way, light traffic can experience very low delays. When a congestion tree becomes persistent, the traffic segment that flows through the congestion tree will need to request forwarding "permits"; in this way, many parallel congestion trees can be efficiently supported. Research cluster Requested: € 23000 Granted: € 14000 Requested: € 0 Granted: € 4000 The funding will be divided as follows: UNICT: 5000 euros (5 persons-trip * 1000 Euros/person-trip) Total amount: 23.000 euros Requested: 12 month(s) Granted: 0 month(s), starting on: Tue, October 9, 2007 MORA PORTA Gaspar (University Politecnica de Valencia) (--phd student--) FLICH José (University Politecnica de Valencia) (--colleague--) MEJIA Andres (University Politecnica de Valencia) (--phd student--) DUATO Jose (University Politecnica de Valencia) (--member--) CATANIA Vincenzo (University of Catania) (--member--) KATEVENIS Manolis (FORTH) (--member--) PNEVMATIKATOS Dionisios (FORTH) (--member--) LYSNE Olav (Simula Research Laboratory) (--member--) PALESI Maurizio (University of Catania) (--colleague--) SKEIE Tor (Simula Research Laboratory) (--colleague--) SøDRING Thomas (Simula Research Laboratory) (--colleague--) GILABERT VILLAMON Francisco (University Politecnica de Valencia) (--phd student--) LóPEZ Pedro (University Politecnica de Valencia) (--colleague--) GOMEZ Maria (University Politecnica de Valencia) (--colleague--) CHRYSOS Nikolaos (FORTH) (--colleague--) ORDUñA Juan Manuel (University of Valencia (Estudi General)) (--member--) KUMAR Shashi (Jönköping University) (--member--) BENINI Luca (University of Bologna) (--member--) TORNERO GAVILá Rafael (University of Valencia (Estudi General)) (--phd student--) SáNCHEZ José Luis (University of Castilla-La Mancha) (--colleague--) HOLSMARK Rickard (Jönköping University) (--phd student--) ALFARO Francisco (University of Castilla-La Mancha) (--colleague--) PASSAS Georgios (FORTH) (--phd student--) GRAN Ernst Gunnar (Simula Research Laboratory) (--phd student--) GARCíA Pedro Javier (University of Castilla-La Mancha) (--colleague--) BERTOZZI Davide (University of Ferrara) (--member--) KABACINSKI Wojciech (Poznan University of Technology) (--member--) Federico Silla (UPV)
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