Description:

With the emerging number of available resources on a single chip, standard architectural paradigms are becoming less and less effective and the performance is not following technology improvements as before. Therefore, research area is moving towards multi-core and many-core architectural solutions that tend to be less complex but still offer lots of computing power. A possible architectural paradigm that can efficiently use all these available resources is a multithreaded paradigm. Since a lot of cores on a single chip will be feasible [1] [2], dataflow (data-driven) paradigm for communicating between the running threads becomes interesting also. Past implementations easily mapped dataflow languages (such as Sisal), but not most popular languages like c/c++. This proposal regards these types of architectures, in particular compiling and mapping programs for them.

In this research, a first objective is to deal with a problem of compiling programs written in conventional programming languages (like c, c++) for some specific multithreaded and/or dataflow architecture. One of the goals is to implement a set of language extensions/pragmas that would enable obtaining intermediate form suitable for these types of parallel multithreaded architectures. A second objective is to find a way to tailor this form for some specific architecture (e.g. DTA [3] [4], DDM [5] [6]).

There will be two major research tracks:
i) compiler track, with a goal to create a tool that will, with a help of language extensions/pragmas in the source code, extract threads in a form that will be easily mapped to a parallel multithreaded architecture, such as DTA and DDM;
ii) architectural track, with a goal to define and implement support in the architecture for efficient scheduling and execution of these threads based on the existing underlying architecture (in particular DTA and DDM), with the end goal to obtain high performance execution.

This cluster will therefore implement one major goal of HiPEAC network by integrating compiler and architecture research.

Phases in the research:
• Propose one common set of language extensions/pragmas that will best suit parallel multithreaded architectures that we are targeting.
• Select a set of benchmarks from the embedded world and modify them with the proposed language extensions/pragmas for further testing of the architectures.
• Next step will be adapting specific architectures in the way that the threads obtained using language extensions/pragmas can be effectively mapped and executed.
• Including adaptive NUCA (Non-Uniform Cache Access) memories in our environments in order to check the behavior of the architectures with a wire-delay dominated chip multiprocessor.

References:
[1] O. Kunle and H. Lance, "The future of microprocessors," Queue, vol. 3, pp. 26-29, 2005.
[2] K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang, "The case for a single-chip multiprocessor," in Proceedings of the seventh international conference on Architectural support for programming languages and operating systems. Cambridge, Massachusetts, United States: ACM Press, pp. 2-11, 1996.
[3] R. Giorgi and Z. Popovic, "Core Design and Scalability of Tiled SDF Architecture," presented at HiPEAC ACACES-2006, L'Aquila, Italy, 2006.
[4] K. M. Kavi, R. Giorgi, and J. Arul, "Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation," IEEE Transaction on Computers, vol. 50, pp. 834-846, 2001.
[5] T. Pedro, E. Paraskevas, S. Kyriakos, and K. Costas, "A case for chip multiprocessors based on the data-driven multithreading model," Int. J. Parallel Program., vol. 34, pp. 213-235, 2006.
[6] C. Kyriacou, P. Evripidou, and P. Trancoso, "Data-Driven Multithreading Using Conventional Microprocessors.," IEEE Trans. Parallel Distrib. Syst., vol. 17, pp. 1176-1188, 2006.

Nature:
Research cluster

Total funding:
Requested: € 10240
Granted: € 10240

Including fellowship funding:
Requested: € 0
Granted: € 0

Description of how the funding will be used:

We ask for some money for PhD students Zdravko Popovic or Kyriakos Stavrou (maybe some other for a longer visit to collaborating institutions (we estimated 2500€ for 2 mutual visits of 1 month).
We also ask for the travelling money for short visits (3 days) in order to reach at least 2 annual meetings. Interested institutions are Pisa/Siena and Cyprus. In details:
• Pisa/Siena
o Two short trips to a cluster meeting (3 days each)
- Accommodation: 3 hotel nights (360€)
- Travelling: 1 round trip flight (700€)
- Total – 1060€
• Cyprus
o Two short trips to a cluster meeting (3 days each)
- Accommodation: 3 hotel nights (360€)
- Travelling: 1 round trip flight (1200€)
- Total – 1560€

This makes the budget for short trips: 2tripsx1060€+2tripsx1560€=5240€.

Together with planed long visits, the total amount we are asking for this cluster is: 5240€+5000€=10240€.

Duration of the funding:
Requested: 12 month(s)
Granted: 0 month(s), starting on: Thu, September 27, 2007

Participating members:
EVRIPIDOU Paraskevas (University of Cyprus) (--member--)
FOGLIA Pierfrancesco (University of Pisa) (--member--)
GIORGI Roberto (University of Siena) (--member--)
PRETE Antonio (University of Pisa) (--member--)
TRANCOSO Pedro (University of Cyprus) (--member--)

Other people collaborating:

• ARANDI Samer, PhD student, University of Cyprus
• BARDINE Alessandro, PhD student, University of Pisa
• POPOVIC Zdravko, PhD student, University of Siena
• PUZOVIC Nikola, PhD student, University of Siena
• STAVROU Kyriakos, PhD student, University of Cyprus