In order to benefit from multicore architectures, the programmer/compiler must detect and run multiple parallel tasks. In order for a task to be worth executing in a separate processor, the overhead of spawning the task, and sending it to the remote processor must be as low as possible, otherwise it is simply faster to execute the task locally.

This cluster will explore the required hardware and compiler support for a very low overhead task spawning mechanism for embedded multicore processors. The idea is based on a hardware implementation of the remote procedure call interface, in which procedures on a remote processor are identified by a stub (integer ID) rather than their memory address. The mechanism should implement fire & forget semantics, so that the calling block does not have to immediately wait for the remote procedure to complete.

This also allows the accelerators/processors to manage their instruction memory in any way the want, and relocate/replace code if/when necessary improving efficiency. A pure software implementation is possible, but requires a high overhead that we will solve by adding the appropriate support.

The student, Alejandro Rico, will be based at UPC where most of the work will be developed. The techniques will be implemented and tested on the UNISIM / Cell simulator developed at UPC. This is only a test platform for which we have an available compiler and simulator, the proposed techniques are agnostic to the actual processor architecture and rely only on the added hardware support.

The work plan for the first year involves:
- define the ISA semantics for calling a remote procedure, passing arguments, synchronizing with its completion, and getting the results
- developing the required hardware support in the simulated platform
- modifying the target applications so that they use the new RPC mechanism instead of the regular task creation/offloading mechanism

The ISA semantics will be defined in collaboration with NXP. Later on, an extended visit to NXP is planned in order to map the proposed techniques from the Cell simulated environment into the actual constraints of the embedded platforms.

3 short (2 day) meetings for 4 people:

3 x 4 x 1000 EUR = 12.000 EUR

1 year fellowship for Alejandro Rico:

12 months x 1200 EUR = 14.400 EUR

1 month extended visit by Alejandro Rico to NXP:

150 EUR x 30 days + 400 EUR transport = 4.900 EUR

Zbigniew Chamsky, NXP
Andrei Terechko, NXP
Alejandro Rico, UPC (student)