IMEC PhD: Low power Embedded Compilers and Architectures for Multimedia and Wireless Applications
Applications are invited for a PhD Research in low power embedded systems design in IMEC vzw, Belgium (http://www.imec.be), starting as soon as possible. An overview of the PhD program (requirements, funding, application forms..etc) is described in the following link:
http://www.imec.be/wwwinter/microsystems/phd/phd.shtml
Candidates with a background in computer engineering or computer science are preferred, but candidates with other backgrounds (electrical engineering with strong interest in embedded compiler optimizations and architectures) are also encouraged to apply.
Topic description:
The fast growing market for embedded devices has large implications on design and technology. Shorter time-to-market requires programmable platforms with sufficient tool-support. Inherent complexity of the application demands high performance throughputs from these platforms. Realistic peak performances are expected to be around 100-1000 GOPs. Additionally, the battery oriented and portable nature of these systems implies stringent power requirements for the platforms. Power consumption of these platforms running these applications is expected to be in the order of around 100-1000 mW. Rephrasing power and performance requirements, we see that the computational efficiency has to be around 1000 MOPS/mw, combined with high peak performances. In addition, as a consequence of technology scaling into the nano-dimensions, deep sub-micron effects cannot be contained at lower levels of system abstraction, but counter measures has to be taken at higher abstraction levels namely in processor architecture and compilers. Finally, with the growth of multimedia and wireless applications that are becoming more complex (dynamic, heterogeneous and memory dominated) mapping such applications onto processor architectures in an efficient manner is a non-trivial task.
The challenges in this domain are in developing solutions in compilers and architectural extensions that are scalable to complex applications/algorithms, resilient to variability and reliability in scaled technologies. Due to the context of embedded systems where battery operation is de facto, energy efficiency is of utmost importance. In addition, due to real-time constraints, high-performance is highly desirable. 100-1000GOPs In order to evaluate many of the solutions (architecture and compilers) design space exploration is becoming very important. Design tools like retargetable compilers, simulators, power and performance estimation engines and architectural exploration frameworks are some of the relevant tools that are becoming indispensable in this context.
Among different types of parallelisms, compiler and architectural solutions for data-parallel and thread-level parallelism seems to be more promising for achieving higher energy efficiency. Furthermore such solutions need to be resilient to scaled technologies and also be scalable to complex applications.
One of the important topics that we want to address is to evaluate the current solutions for data-memory management. For data-parallelism and thread-level parallelism, we believe the current solutions for data-management and inefficient, especially for software controlled memories like scratch-pads. The memory organization that is both resilient to scaled technologies and energy efficient for data-parallelism, need to be evaluated. In addition, compilation and estimation techniques need to be evaluated for the resulting organization.
Another important topic is the data-path management and architectures. In many of wireless and multimedia applications the granularity (sizes) of data-types, vary significantly. Energy efficient SIMD/sub-word like architectures are needed to exploit this varying sizes of data-types. Architectural support is needed to group and ungroup sub-words, computational units and the instruction set should be sub-word aware. In addition, efficient mapping/compiler techniques are needed to map the data-parallel aspects in the application on to the sub-word aware architecture. These issues will be addressed in this research topic.