5th HiPEAC Industrial Workshop

Tools and Methodology for Parallel Programming

June 4th, 2008. Organized by: HP Labs, Exascale Computing Lab, Barcelona Research Office Hewlett-Packard, Sant Cugat del Valles, Barcelona, Spain

We live exciting times in the field of parallel architectures. The diminishing IPC returns caused by power and frequency walls have forced a radical change in CPU design. Multicore is here to stay and has become pervasive throughout the computer industry. In high-performance computing, three out of four "TOP 500" systems are clusters of industry-standard multicore nodes. In embedded computing, heterogeneous multicore System-on-Chips have become the dominant standard for high-volume parts.

There is no silver bullet in multicore programming, and formidable computer science problems underlie the programming of this new breed of parallel architectures. Traditional parallel programming paradigms and tools need to be put to the test and questioned. The heterogeneity of cores and accelerators is creating new challenges to the programming models. Locks and multithreading memory semantics are being redefined and transactional programming is on the horizon. With new programming paradigms and a shifting architecture target, new tools and analysis methodologies are also granted.

The goal of this workshop is to bring together researchers from academia and industry to discuss tools and methodologies for analysis, compilation, debugging, verification and simulation of parallel programs.

Topics

The topics of interest include, but are not limited to:

• Compiler support for explicit parallelism (threads, transactions)
• Tools to aid programmers to identify, exploit, verify, debug, and tune parallel applications
• Simulation methodology and tools for multicore/manycore/clustered parallelism
• Characterization of parallel applications and their scalability
• Reliability and Fault Tolerance for applications running on many-core and distributed architectures
• I/O issues in parallel computing and parallel applications
• Parallel programming languages, algorithms and applications
• Middleware and run time support for parallelism

Keynote

Getting C++ threads right, Hans Boehm, HP Labs.

For many application domains, threads and locks, particularly in the form of C or C++ with a threads library, remain the standard approach for writing parallel programs. Somewhat surprisingly, there are a number of often subtle, but generally fixable, industry-wide problems associated with this approach. Problems span the spectrum from system libraries through language implementations through the underlying architectures. They get in the way both in that they often make it difficult to write 100% reliable multithreaded software, and in that they confuse even the basics of the programming model, thus making it hard to teach. A surprising number of "experts" do not understand the basic rules. These problems largely carry over to transactional memory systems.

Since solutions to these problems generally require a coordinated industry effort, we helped to persuade the C++ standards committee to address them in the working paper for the next C++ standard. We outline the problems and proposed solutions.

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Hans Boehm is the primary author of a widely used multithreaded garbage collector library. He is leading an ongoing effort to extend the C++ standard with clean semantics for threads, and particularly shared variable accesses. He holds a Ph.D. from Cornell University, has published a number of influential papers on garbage collection, and a few on threads and synchronization. He is a past Chair of ACM SIGPLAN, and of the POPL, ISMM and VEE research symposia. He was awarded the 2003 PLDI most influential paper award, and the 2006 SIGPLAN Distinguished Service Award, and is an ACM Distinguished Scientist. He works for HP Laboratories.

Program

Session 1 - Compilation and Code Generation

• Compiling C to CLI for Heterogeneous Multicore System-on-Chips, by Erven Rohou, Andrea Ornstein and Marco Cornero [slides]
• Programming Multicore Systems Using Hierarchically Tiled Arrays, by Diego Andrade, James Brodman, Basilio B. Fraguela and David Padua [slides]
• Polyhedral code generation for GPUs, by Piotr Lesnicki, Cedric Bastoul, Albert Cohen, DaeGon Kim and Louis-Noel Pouchet [slides]
• Automating generation of data movement code for parallel architectures with distributed memories, by Lee Howes, Anton Lokhmotov, Paul Kelly and Alastair Donaldson [slides]

Session 2 - Tools

• COTSon: infrastructure for system-level simulation of clustered multicores, by Eduardo Argollo, Ayose Falcon, Paolo Faraboschi and Daniel Ortega [slides]
• A Tool Environment for Data Locality Optimization on Chip-Multiprocessors, by David Kramer, Oliver Mattes, Rainer Buchty and Wolfgang Karl [slides]
• Clock Synchronization in Cell BE Traces, by Marina Biberstein, Yuval Harel and Andre Heilper [slides]
• A Dynamic Analysis Tool for Finding Coarse-Grain Parallelism, by Sean Rul, Hans Vandierendonck and Koen De Bosschere [slides]

Session 3 - Methodology

• CAPSULE: A Symbiotic Hardware/Software Approach for Facilitating the Parallelization of Programs with Complex Control Flow and Data Structures, by Olivier Certner, Zheng Li and Olivier Temam [slides]
• MAPS: An Integrated Framework for MPSoC Application Parallelization, by Weihua Sheng, Jeronimo Castrillon, Jianjiang Ceng, Hanno Scharwaechter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki and Hiroaki Kunieda [slides]
• On-chip memories, the OS perspective, by Carlos Villavieja, Isaac Gelado, Alex Ramirez and Nacho Navarro [slides]
• Overhead of the spin-lock loop in UltraSPARC T2, by Vladimir Cakarevic, Petar Radojkovic, Francisco Cazorla, Robert Gioiosa, Mario Nemirovsky, Mateo Valero, Manuel A. Pajuelo Gonzalez and Javier Verdu [slides]

Important Dates

Submission deadline	April 25th, 2008
Notification of acceptance	May 2nd, 2008
Workshop	June 4th, 2008

Submissions

Authors should submit their contributions electronically to Daniel Ortega. Submissions must include a 2-page extended abstract describing the work that is going to be presented. Authors should feel free to present work in progress as well as already published material, and can include related documents with additional details on their research work. Authors should commit to present their research at the workshop in the case it gets selected. Abstract and other workshop material will be made available online at http://www.hipeac.net/. The workshop will not publish proceedings. While this workshop is organized by HiPEAC, the host (HP Labs) is solely responsible for the selection process.

You can get a pdf version of the Call for Papers here

How to get to HP Barcelona Site

You can get a pdf instructions of how to get to HP site in Barcelona here