Introduction

The goal of this cluster is to bring together the community around a common approach for modeling architectures. The motivation for this cluster is twofold: (1) modeling methodologies are facing significant challenges, especially due to the complexity of architectures and the emergence of multi-cores, (2) modeling/simulation tools are largely fragmented within the academic and industrial communities, making it exceedingly difficult to share, reuse or compare research or product achievements.
Within this cluster, we will put an emphasis on simulation, like in HiPEAC1, but we also want to investigate analytical/statistical modeling, and FPGA prototyping, as two major alternative approaches.

Within HiPEAC1, we had kick-started this effort, then exclusively focused on simulation, which led to the development of the UNISIM simulation framework (see https://www.unisim.org). Within HiPEAC2, our first goal is less to promote a single all-encompassing environment than to define methods for the different simulator efforts and tools to interoperate. The second goal of HiPEAC2 is to address a set of urgent research challenges.

The proposition for the main orientations of the cluster are the following.

Interoperability.

Rather than bringing every academic and industry researcher to the same environment, we wish to develop a set of interfaces to allow simulators and tools to interoperate. They include micro-architecture interfaces (e.g., processor/memory interface), at different levels of granularity (e.g., cycle-level, transaction-level), functional simulation/performance simulator interfaces, services interfaces (e.g., power modeling, area cost, temperature,...), and so on. To a certain extent, the cluster would then function as a small-scale standardizing body where researchers would agree on such interfaces. We believe this approach creates a win-win situation where anyone can preserve his/her tool investment, can disseminate it to many potential users, and can benefit from the work of others. As a result, it has the potential to foster a large and vivid community in the domain.

Library and Flagship simulators.

Beyond interoperability, researchers want ready-to-use tools. For that reason, it is important to identify and promote a few simulators, which can be considered as "flagship" simulators. The list of simulators will be by no means exclusive nor final, it is simply meant to highlight mature and useful tools that could readily benefit the whole community, to serve as a testbed for new features and interoperability, and as dissemination vehicles for our research. The first flagship simulators shall be identified in the next few months. Together with these simulators, we expect to progressively build a library of interoperable modules and models which will abide by the aforementioned interfaces.

Research Challenges.

Beyond methodology issues, there are severe research challenges in modeling and simulation which must be quickly addressed. Some of the key challenges are:

• Simulation speed. It is the #1 challenge as architectures evolve to multi-cores with tens of cores. Numerous solutions are emerging, such as transaction-level modeling, sampling, parallel simulators, native execution, statistical simulation, FPGA prototyping, but they should be rapidly investigated.
• Technology. Numerous technology issues are now creeping up into system design and can no longer be ignored: besides power and area cost issues, they include wire delays, clock domains, temperature,...
• Application complexity. With the advent of smartphones used for 3D games and GPS navigation, embedded applications are getting almost as complex as desktop applications. Moreover, these smartphones are now running Linux or MacOS, so that full-system simulation is a must have, especially with multi-core architectures where the scheduler is playing an increasingly important role.
• Heterogeneous architectures. Embedded architectures and even the new general-purpose architectures are heterogeneous architectures. Modeling/Simulating such architectures raises special challenges. These challenges will be considered, especially through a tight cooperation with the Design cluster.

Coordinating partner: INRIA

Contact: Olivier Temam