Design methodology and tools

Research challenge:

Electronic design automation (EDA) methodology and tools are key enablers for many HiPEAC research activities, such as multi-core and NoC architectures, or reconfigurable systems. In the light of moving towards 65nm and 45nm CMOS technologies, and thus the urgent need for higher design productivity, EDA is currently aiming at a new abstraction level: Electronic System Level (ESL). ESL focuses on system design aspects 'beyond RTL', e.g. efficient HW/SW modelling and partitioning, mapping applications to MPSoC architectures, ASIP design, etc. These and other research topics are being addressed in the 'Design methodology and tools' cluster. While ESL is currently mostly driven by the embedded system design community, due to the need to design efficient application specific systems with very limited resources (and thus with a higher acceptance of automation and tools), it can strongly benefit from many recent developments in the high-performance community (such as fast simulation, efficient compilation etc.), and vice versa. Therefore, another important goal of this cluster is to establish a closer link between these communities. Besides the regular cluster meetings, this is being implemented e.g. by coupling of existing platforms and tools, so as to achieve new heights in design productivity.

Scientific issues:

• Design methodology and tools driven by the trend towards multiprocessor system-on-chip (MPSoC) architectures.
• Applications include: wireless communications, multimedia, automotive.
• Very high efficiency goals (MIPS/Watt or Joule/bit), therefore programmable, yet application-specific and heterogeneous MPSoCs.
• Currently shift towards Electronic System Level (ESL) design methodologies, will provide the required next productivity boost beyond RTL design.
• Key for managing the complexity of today's and future digital chip designs in advanced CMOS technologies (45nm, 32nm, and beyond).
Research topics:
• Embedded processor design: ASIP design, design space exploration, configurable and reconfigurable processors, SW tools generation, retargetable compilation, processor/compiler co-design, loop parallelization, template based ASIP design, instruction set extensions, ultra-low power ASIPs, open source processor cores .
• MPSoC modelling and verification: modelling languages, SystemC based modelling, verification and design, high-speed instruction set simulation, virtual platforms, path from model to implementation, NoC simulation.
• MPSoC programming: application-to-architecture mapping, RTOS, task graph scheduling, sequential-to-parallel code generation, benchmarking.
• MPSoC HW/SW architectures: SW performance estimation, HW/SW integration, tightly coupled processor architectures, memory hierarchy, HW/SW interface synthesis, fault tolerance, loop transformations.

Major cluster activities in year 2009:

• Aachen-Edinburgh seminar: A joint seminar on tools and architectures was held in Aachen in Feb 2009.
• FORTH-Aachen seminar: A joint seminar on tools and architectures was held in Heraklion in June 2009.
• HiPEAC booth at DATE 2009: A booth was organized at DATE, the major annual European EDA event. New contacts have been established, and new members have been acquired.
• Student internships: For instance, one master student of Aachen joined Thales research in 2009 to work on an SDR project.
• Joint master theses: For instance, a joint ACE/Aachen thesis on compiler technology was performed.
• Paper awards: Cluster members received Best Paper Awards at DATE 2009 and the SoC Forum 2009.
• DATE special session: A special session on MPSoC programming with invited speakers was organized at DATE 2009.
• Collaboration grant: From March-June 2009, R. Velasquez from the ALaRI institute visited Aachen to work on "MPSoCs - Programming Models and Operating Systems". The collaboration continued beyond the HiPEAC grant and was concluded successfully in September with an accepted paper at DATE 2010.
• Cooperation with ARTIST-DESIGN NoE: Aachen is active in the SW synthesis cluster of the ARTIST-DESIGN NoE, and provides tool support for benchmarking.

Coordinating partner: RWTH Aachen